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A 10 bit 50 Msps SAR ADC in 65 nm CMOS with on chip reference voltage buffer

A10-bit50MS/s SAR ADC in65nm CMOS with on-chip reference

voltage buffer

Prakash Harikumar n,J.Jacob Wikner

Department of Electrical Engineering,Link?ping University,SE58183,Sweden

a r t i c l e i n f o

Article history:

Received4August2014

Received in revised form

11January2015

Accepted12January2015

Available online22January2015

Keywords:

SAR ADC

On-chip reference voltage buffer

Bootstrapped switches

a b s t r a c t

This paper presents the design of a10-bit,50MS/s successive approximation register(SAR)analog-to-

digital converter(ADC)with an on-chip reference voltage buffer implemented in65nm CMOS process.

The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling

reference voltage buffer are elaborated.Design details of a high-speed reference voltage buffer which

ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided.

The ADC uses bootstrapped switches for input sampling,a double-tail high-speed dynamic comparator

and split binary-weighted capacitive array charge redistribution DACs.The split binary-weighted array

DAC topology helps us to achieve low area and less capacitive load and thus enhances power ef?ciency.

Top-plate sampling is utilized in the DAC to reduce the number of switches.In post-layout simulation

which includes the entire pad frame and associated parasitics,the ADC achieves an ENOB of9.25bits at a

supply voltage of1.2V,typical process corner and sampling frequency of50MS/s for near-Nyquist input.

Excluding the reference voltage buffer,the ADC consumes697μW and achieves an energy ef?ciency of

25fJ/conversion-step while occupying a core area of0.055mm2.

1.Introduction

The proliferation of mobile devices supporting applications

such as DVB-T and DVB-H has created the demand for power-

ef?cient ADCs with resolutions of9–12bits and sampling speeds

of several tens of MS/s[1].Medium-resolution,high-speed analog-

to-digital conversion has traditionally been dominated by pipe-

lined ADCs.But the continued scaling of CMOS technologies

accompanied by the reduction of supply voltage poses signi?cant

hurdles for the design of power-ef?cient pipelined ADCs.Pipelined

ADCs require high-gain,linear opamps which are power-hungry

blocks.Due to the low output resistance of\short channel MOS

devices,multi-stage ampli?ers are necessary to attain high DC

gain which diminishes power ef?ciency.The reduced supply

voltages in sub-100nm CMOS processes result in lower signal

swings in the ampli?ers which further degrades the signal-to-

noise ratio(SNR)for a given value of sampling capacitance.On the

contrary,SAR ADCs eliminate the use of opamps and achieve

excellent power ef?ciency[2].Dynamic comparators are com-

monly used in SAR ADCs[3].Since the dynamic comparator does

not require static bias currents,the power consumption of the SAR

ADC linearly scales with the sampling frequency.Also the speed

and power ef?ciency of the digital logic in the SAR ADC improves

with CMOS process scaling.SAR ADCs have achieved sampling

rates from several tens of MS/s to low GS/s with10-bit resolution

[4–6].SAR-assisted pipelined ADCs[7]have achieved good power

ef?ciency at speeds exceeding200MS/s.

In this work,we present a power-ef?cient SAR ADC implemen-

ted in65nm CMOS.The design includes an on-chip reference

voltage buffer(RVBuffer)which helps us to eliminate the speed

limitation posed by incomplete DAC settling.The topology and

design details of the RVBuffer which satis?es the performance

requirements are discussed in https://www.wendangku.net/doc/cf5263464.html,prehensive simulation

results which verify the ADC performance are reported.

In medium-resolution,high-speed SAR ADCs,the speed limitation

is caused by incomplete DAC settling.Further performance degrada-

tion occurs when the DAC reference voltage is provided off-chip due to

the parasitic inductances on the reference voltage line.Achieving the

targeted ADC performance under such conditions requires a high-

speed on-chip reference voltage buffer.In addition to fast settling

behaviour,the reference voltage buffer should possess suf?ciently high

power-supply rejection ratio(PSRR),low noise and must remain stable

for all operating conditions.This paper presents a10-bit,50MS/s SAR

ADC with a power consumption of697μW implemented in65nm

CMOS technology.To overcome the performance degradation due to

Contents lists available at ScienceDirect

journal homepage:https://www.wendangku.net/doc/cf5263464.html,/locate/vlsi

INTEGRATION,the VLSI journal

https://www.wendangku.net/doc/cf5263464.html,/10.1016/j.vlsi.2015.01.002

0167-9260/&2015Elsevier B.V.All rights

reserved.

n Corresponding author.Tel:t4613286653.

E-mail addresses:prakash.harikumar@liu.se(P.Harikumar),

jacob.wikner@liu.se(J.J.Wikner).

INTEGRATION,the VLSI journal50(2015)28–38

ringing on the DAC reference caused by bondwire inductances,a high-speed on-chip reference voltage buffer has been designed and incorporated in the ADC.To reduce the area and capacitance values in the DAC,a split binary-weighted capacitive array has been used.A double-tail dynamic comparator has been optimized for noise and speed.Bootstrapped switches are used for input sampling in order to guarantee suf?cient linearity for the ADC.A synchronous SAR con-troller has been implemented using static CMOS logic.

The rest of the paper is organized as follows.Section2explains the DAC settling limitations in high-speed SAR ADCs and the nec-essity of a high-speed on-chip reference voltage buffer.Section3 describes the architecture of the proposed SAR ADC.Section4 presents the implementation of the important building blocks of the ADC.Section5provides the simulation results for the SAR ADC.Conclusions are drawn in Section6.

2.Limitations for DAC settling

In high-speed,medium-to-high resolutione49bitsTSAR ADCs, the speed bottleneck is caused by the settling time for the DAC. Assuming that one clock cycle is allocated for sampling the input,a conventional N-bit SAR ADC requires a minimum of(Nt1)clock cycles for one complete conversion.For a10-bit,50MS/s SAR ADC, this results in a minimum system clock frequency of550MS/s.In this work,a system clock frequency of f clk?600MHz is used which corresponds to12cycles of the sampling clock.Each period of the system clock is divided equally between the DAC settling phase and the comparison phase.Within the half-cycle time period,the DAC voltage has to charge/discharge to a new level and settle with an accuracy410bits.Incomplete DAC settling will introduce conversion errors and destroy the performance of the ADC.When the DAC reference voltage is provided off-chip,the DAC settling is worsened by the effect of the parasitic inductances of the bondwires,PCB traces,https://www.wendangku.net/doc/cf5263464.html,rge charging currents drawn from the off-chip reference voltage through the inductances will cause ringing on the DAC capacitor node being charged.This in turn will cause the DAC output to ring[8].The bondwire inductance depends on the dimensions of the gold wire used in bonding. The inductance of a gold wire of length l(mm)and radius r(mm) is given by[9]

L?l

à3

:e1T

Assuming a diameter of1mil(25.4μm)and a length of3mm for the bondwire,(1)results in an inductance L?3.24nH.With some margin for the PCB trace inductance,a minimum total inductance of4nH is allocated on the off-chip reference voltage line.It is shown in Section5that the magnitude of ringing on the DAC output voltage even for4nH inductance is many times higher than the least signi?cant bit(LSB)of the ADC which unacceptably degrades performance.

One method to solve the DAC settling issue in the presence of parasitic inductances is to ensure suf?cient timing margin such that the ringing effect diminishes to the required accuracy level. For high-speed SAR ADCs,this will considerably lower the max-imum sampling frequency that can be employed.On-chip decou-pling for the DAC reference is another technique to mitigate the ringing effect.But prohibitively large capacitance values will be required to limit the perturbations below1LSB rendering this technique impractical for most implementations.Incorporating a high-speed on-chip reference voltage buffer isolates the DAC reference voltage from ringing effects and helps us to attain the targeted ADC performance.Design details and implementation of the reference voltage buffer will be elaborated in Section4.1.3.ADC architecture

Fig.1shows the proposed SAR ADC architecture.It consists of bootstrapped sampling switches,split binary-weighted capacitive DACs,a high-speed dynamic comparator,synchronous SAR logic and an on-chip reference voltage buffer.In a conventional SAR ADC[10],the input voltage is sampled on the bottom plates of the capacitor array and the top plates are connected to a?xed voltage V cm.In the redistribution mode for the MSB,the output voltage of the DAC is given by[10]

V DAC?V cmàV int

V REF

:e2TIf one of the power rails is chosen as the value for the?xed voltage V cm,it is seen from(2)that V DAC exceeds the supply rails during conversion when the input voltage ranges from0to V DD.A remedy is to use a lower input range which has a detrimental effect on the signal-to-noise ratio(SNR)of the converter.In this work we use top-plate sampling with preset MSB for rail-to-rail analog inputs without using additional?xed voltages[2,11].It is assumed that the input common-mode level is V DD=2.During the entire con-version,the DAC outputs are limited to the supply rails and the common-mode voltage of the DAC outputs is kept at V DD=2.

During the sampling phase of the SAR ADC,the inputs V inP and V inN are connected to the top-plate node of the main DAC,the MSB is preset to high and all other bits are reset to low as shown in Fig.2.At the end of the sampling phase,the sampling switches are opened and the differential input voltages are sampled on the top-plate node of the main DAC.During the?rst comparison cycle,the comparator compares V DACP and V DACN.If V DACP4V DACN,the MSB is kept high.If V DACP o V DACN, the MSB is made low.Then MSB-1is set to high and the comparator compares its differential inputs.The associated timing diagram is shown in Fig.3.The process continues until all the10bits are determined.

4.Implementation of ADC building blocks

The important building blocks of the ADC are the RVBuffer, input sampling switches,dynamic comparator,capacitive DAC

and Fig.1.The proposed SAR ADC

architecture.

Fig.2.Capacitive DAC during sampling phase of the SAR ADC.

P.Harikumar,J.J.Wikner/INTEGRATION,the VLSI journal50(2015)28–3829

SAR controller.The RVBuffer facilitates the precise settling of the DAC reference voltage.For the simulations of the various circuit blocks,the process,supply voltage and temperature (PVT)corners encompass all process de ?ned corners for MOS devices,resistors and capacitors,temperature range [à401C t1251C]and 710%supply voltage variation.Monte Carlo (MC)simulations including process variation and device mismatch were performed to deter-mine offset voltage of the RVBuffer and comparator,INL/DNL of the DACs and the ENOB of the full ADC.The design details of these building blocks are described in the following subsections.4.1.Reference voltage buffer

When the DAC reference voltage is provided off-chip for SAR ADCs working at high sampling rates,the effect of bondwires and other parasitic inductances can severely degrade DAC settling [8].The switching of a capacitor in the DAC array to the high reference voltage causes charge to be drawn from the off-chip reference.The charge transfer through the bondwire inductance on the reference line causes ringing on the DAC output [8].For this ADC,the DAC output should settle with an accuracy higher than 10bits within the half-cycle time period of the 600MHz clock.Providing for 100ps delay in the digital logic,this leads to a DAC settling time requirement of around 733ps.Achieving such fast settling req-uires a voltage buffer with very low output impedance.Few published works on SAR ADCs include on-chip reference voltage buffers.

4.1.1.Calculation of design parameters

To aid the design of the RVBuffer,estimation of important design parameters such as peak output current during slewing,unity-gain frequency and DC gain of the ampli ?er was carried out.

The settling time is a critical speci ?cation for the RVBuffer.The total settling time consists of the constant-slope (slewing)regime and the linear settling https://www.wendangku.net/doc/cf5263464.html,ually the linear settling time takes much longer than the slewing time [12].It is dif ?cult to precisely demarcate the two regimes and hence we allocate 10%of the total settling time for slewing and the remaining 90%for linear settling [13].Based on this split-up,the minimum output current during slewing and unity-gain frequency are computed.From Fig.1,it can be found that the total effective DAC capacitance that is connected to the RVBuffer at any point of time is 31C u tC u ?32C u .The worst case settling scenario for the RVBuffer occurs when the MSB-1bit is preset to HIGH (V REF )with the MSB bit determined to be LOW (0V).In this case,24C u is switched from the low reference (GND)to the high reference (V REF )while the total effective load capacitance of the RVBuffer is 32C u .From charge-conservation,it is found that this switching causes a voltage change ΔV at the RVBuffer output where 32C u áΔV ?24C u eV REF àGND T:

e3T

Using V REF ?1.2V in (3),we have

ΔV ?24C u

32C u V REF ?0:75V REF ?900mV :

e4T

The slew-rate of the RVBuffer is given by

ΔV

t slew

0:9

0:1á733?10

?I out C L ;RVBuffer

;e5T

where C L ;RVBuffer ?32C u and I out is the peak output current during

slewing.The unit capacitor C u is chosen to be 15fF as explained in Section 4.4.Solving (5),we get I out ?5.9mA.

For a single-pole ampli ?er in closed-loop con ?guration,the step-response is given by V out et T?V step e1àe àt =τT;

e6T

where τ?1=βáωug with βbeing the feedback factor of the RVBuffer and ωug being the unity-gain frequency of the RVBuffer in rad/s.For unity-gain feedback,β?1.The settling error ??e àt =τ.Thus t ?

àln e?T

ωug

àln e?T

2πáf ug

;

e7T

where f ug is the unity-gain frequency of the buffer in Hz.Since the reference voltage has to settle with an accuracy 410bits,we have targeted 13-bit settling accuracy which provides suf ?cient design margin.From (7),for 13-bit settling,we ?nd the minimum f ug as f ug ?

àln e?T2πát ?àln e1=213T

2πá0:9á733?10à12

?2:17GHz :

e8T

A high open-loop DC gain (A 0)is necessary to achieve good PSRR performance [14].Since the PSRR is a key requirement for an RVBuffer,we have targeted an open-loop DC gain A 0?60d

B for the RVBuffer.A large D

C gain also helps us to minimize the static error on the buffered voltage.For a closed-loop ampli ?er,the ?nite A 0results in a gain error factor of ζ[12]:

ζ?1àA 0β0β

0β:e9TFor a unity-gain buffer,the feedback factor β?1,making ζ?1=A 0.

An open-loop DC gain ?60dB helps us to limit the gain error ζto 0.1%.

4.1.2.Circuit details of the reference voltage buffer

In this work,the high reference voltage V REF ?1:2V and the low reference voltage is ground.A single-ended reference voltage buffer for generating V REF has been designed with 2.5V thick oxide MOSFETs from the 65nm design kit.The topology of the RVBuffer shown in Fig.4has been adapted from [15].The selected RVBuffer topology is similar to a low-dropout (LDO)regulator.The source-follower stage achieves low output resistance and thus provides large output current when its gate-source voltage V GS changes.In Section 4.1.1,it was estimated that f ug %2GHz will be needed in a conventional single-stage opamp to meet the settling time requirement.However,use of the topology shown in Fig.4enables fast settling with a lower unity-gain frequency for the opamp OA 1.In Fig.4,the replica source-follower (SF)stage isolates the node V REF 0from the capacitive load of the DAC which is connected to node V REF .The feedback loop assures stability while the open-loop settling due to the replica SF stage enables fast operation.Hence the feedback loop can be designed with lower bandwidth which leads to a lower unity-gain frequency speci ?cation for OA 1.

In Fig.4,OA 1is a two-stage ampli ?er.This structure achieves an open-loop DC gain 460dB thus providing suf ?cient PSRR and low static gain error on the V REF voltage.A two-stage ampli ?er with conventional Miller compensation requires large transconductance in the second stage for ensuring suf ?cient phase margin (PM)

which

Fig.3.Timing diagram for the sampling phase of the SAR ADC.

P.Harikumar,J.J.Wikner /INTEGRATION,the VLSI journal 50(2015)28–38

increases power consumption.Also the presence of the right half plane zero degrades PM unless a nulling resistor is used.To circumvent these disadvantages,split-length compensation of op-amps has been pro-posed [16].Fig.5shows the schematic of the RVBuffer.The two-stage ampli ?er uses split-length current mirror load topology [16].The open-loop gain and phase plot of the RVBuffer for nominal PVT condition is shown in Fig.6.The open-loop DC gain ?70dB,phase margin ?681and unity-gain frequency ?600MHz.The worst (i.e minimum)values for these parameters across all PVT corners are provided in Table 1.

The supply nodes of the DAC driver inverters are connected to node V REF in Fig.5.During capacitor switching in the DAC,the voltage change on V REF will couple through the C gs of M 10;M 11and perturb the node V 2thus degrading DAC settling.This effect is mitigated by the capacitance C st [17]at node V 2.To eliminate body-effect,the bulks of M 10;M 11are connected to their respective sources through the use of deep-NWELL devices.The two SF stages in Fig.5are carefully laid out and dummy devices are included to improve matching.

The post-layout simulation results for the RVBuffer are summar-ized in Table 1.For all performance speci ?cations,the worst-case values over PVT corners and mismatch simulations are presented in Table 1.The RVBuffer provides a worst-case settling time of 692ps for V REF with 13-bit accuracy which satis ?es the DAC settling requirement for the SAR ADC.PSRRp signi ?es the rejection of disturbances on the 2.5V supply line.The integrated output noise of the RVBuffer is only 0.086LSB.The integration limits are [0Hz 180GHz].Due to the bene ?ts of the replica SF topology,the RVBuffer meets the settling time speci ?cation with a lower unity-gain frequency of 600MHz.The transient current consumption and open-loop DC gain for the implemented RVBuffer compare well with the estimated values in Section 4.1.1.The total offset voltage of the

RVBuffer is 4.18mV.The offset voltage contribution due to mismatch in the input differential pair is 690μV while mismatch in the replica SF stages contributes an offset of 1.72mV.The static error on the RVBuffer output due to the ?nite loop gain of the ampli ?er causes an offset of 1mV.It is seen that the mismatch in the replica SF stages makes the dominant contribution to the offset voltage.

In this work,the RVBuffer is implemented with 2.5V MOS devices.Although a higher supply voltage increases the power consumption of the RVBuffer,this allows the use of V REF ?1:2V and the SAR ADC can sample rail-to-rail inputs.Also the DAC drivers are simple inverters instead of transmission-gate switches which enhance speed and power ef ?ciency.If the RVBuffer is to be implemented with core 1.2V devices,the considerable V GS drop caused by the SF stages has to be surmounted so that an adequate input range for the ADC i.e.eV refp àV refn Tcan be guaranteed.Techniques such as forward body biasing [18]or level shifting with boosted supply voltages and additional SF stages [19]will need to be employed in the RVBuffer which will increase design complexity.With a lower input range for the ADC and assuming that the total DAC capacitance remains unchanged,a pre-ampli ?er for the dynamic comparator will become inevitable to reduce the noise at the cost of increased power consumption [20].

In this work,the ADC works at the core voltage (1.2V)while the RVBuffer works at the IO voltage (2.5V).From a system-on-chip (SoC)implementation perspective,this does not constitute a signi ?cant drawback since SoCs often employ multiple supply voltages (e.g.high-voltage devices are used to reduce leakage in certain critical blocks of the SoC).

The bias voltage V BiasP in Fig.5is generated by the constant-g m bias circuit [21]shown in Fig.7.The start-up circuitry consisting of M 9–M 11precludes the possibility of a zero-current state.Since the constant-g m bias circuit uses positive feedback and R Ext is an off-chip resistor,parasitic capacitances on node V R can cause oscilla-tions [21].A suf ?ciently high value for R Ext was chosen.

Extensive

Fig.4.Topology of the reference voltage

buffer.

Fig.5.Schematic of the reference voltage buffer.

?40

?2002040

6080Frequency [Hz]

G a i n [d B ]

?350

?300

?250?200?150?100

?50

050P h a s e [d e g ]

Fig.6.Open-loop gain and phase plot for the RVBuffer.

Table 1

Performance summary of reference voltage buffer.Parameter

Value

Supply voltage 2.5V Settling time 692ps PSRRp @10kHz 68dB PSRRp @600MHz 25dB σnoise ;out

201μV Offset voltage (σoffset ) 4.18mV Phase margin 581DC gain

62dB Unity-gain frequency 511MHz

Area

(55μm ?104μm)Current (I tran )

8mA

P.Harikumar,J.J.Wikner /INTEGRATION,the VLSI journal 50(2015)28–38

DC,transient simulations of the bias circuit involving estimated off-chip parasitics at node V R were performed to con ?rm circuit stability over PVT corners.It is important to bear in mind that the circuit in Fig.7provides an output current that is stable only over supply voltage variations in a certain range.Signi ?cant variation in the output current was found for the extreme temperature corners namely à401C and t1251C.4.2.Input sampling switches

The input sampling switches are crucial in determining the linearity of the ADC.Various non-ideal effects of the sampling switch such as signal-dependent on-resistance variation,charge-injection and clock feedthrough degrade linearity [22].Also the tracking bandwidth of the sampling switch must be suf ?ciently high.The tracking bandwidth of a sampling circuit for an N-bit converter should satisfy [23]f 3dB ?

12πR on C s 4eN t1Tln e2T

f s :

e10T

In this case,the sampling/acquisition period is one clock cycle of the SAR clock which sets f s ?12?50MHz ?600MHz.For the split binary-weighted array capacitive DAC with top-plate sampling as shown in Fig.11,the total sampling capacitance C s ?480fF.For N ?10bits,this results in an on-resistance (R on )upper bound for the sampling switch given by R on o 227Ω.Attaining such a low R on value without huge device sizes over PVT corners requires the use of bootstrapped sampling switches.In this work,the bootstrapped switch topology presented in [24]has been used.The transistor implementation of the bootstrapped switch is shown in Fig.8.Similar to [25],the dummy switch PD in Fig.8helps us to alleviate charge injection at node E.A MIM capacitor from the 65nm design kit has been used to implement the bootstrap capacitor.The value of the bootstrap capacitor was chosen such that the effect of parasitic capacitances on the switch performance is minimized.In Fig.8,the devices N 3,P 4,N 5are OFF during the acquisition phase ?1n .Hence high-threshold voltage devices were used to implement N 3;P 4;N 5in order to reduce leakage.Post-layout simulation results for the bootstrapped switch linearity (noise not included)over PVT corners is provided in Fig.9.The simulation testbench for switch linearity includes 50Ωresistors for the analog inputs.The analog input frequency is 21MHz (near-Nyquist).The worst linearity occurs for the slowest MOS corner combined with the highest temperature of

t1251C.From Fig.9,it is seen that the switch maintains 10-bit linearity even for the worst PVT conditions.In Fig.8,the main switch Sw remains OFF for 11clock cycles during which the ADC outputs are generated.Hence the effect of Sw leakage has to be considered.For the NMOS Sw ,a standard-threshold voltage device combined with careful sizing has been used to balance speed and leakage.Since the absolute gate voltage of the switch exceeds the supply voltage V DD ,suf ?cient precautions have to be taken to guarantee reliability of the switch.A long circuit lifetime is assured for the switch by ensuring that the critical terminal voltages V gs ;V gd and V ds are kept within the rated supply voltage V DD [26].4.3.Dynamic comparator

Dynamic comparators are a popular choice in SAR ADC imple-mentations since they eliminate static bias currents and thus improve power ef ?ciency.Fig.10shows the schematic of the double-tail dynamic comparator [27].Inverters have been added at the outputs to make the output loading identical.During the reset state eClk ?0V T,transistors M 4and M 5charge the nodes Di àand Di tto V DD which causes the devices M 10and M 11to discharge the output nodes to ground.During the evaluation phase eClk ?V DD T,the cross-coupled inverters regenerate the input voltage difference to provide digital output levels.The devices M 10and M 11help us to reduce kickback noise [27].The double-tail architecture provides a number

Fig.7.Schematic of the constant-g m bias

circuit.

Fig.8.Schematic of the bootstrapped switch.

9.5

10.5

11.5

PVT Corner

E N O B (b i t s )

BootStrap Switch ENOB vs PVT Corner

Fig.9.Linearity performance of the bootstrapped switch.

P.Harikumar,J.J.Wikner /INTEGRATION,the VLSI journal 50(2015)28–38

bene ?ts over the conventional sense-ampli ?er latch [28].Since the number of stacked devices is less,the double-tail comparator can operate at lower supply voltages.Due to the double-tail structure,the current in the input stage can be decoupled from that in the latching stage.According to [29],the input-referred noise of the dynamic comparator can be lowered by using smaller current,i.e.lower size for the tail-source transistor M 3,in the input stage.In the double-tail comparator,lower current is used in the input stage to reduce noise,offset while higher current is used in the latching stage to meet the speed requirement.Increasing the capacitance on nodes Di à;Di tnot only helps us to lower the comparator noise [29]but also results in increased comparator delay.As a trade-off,minimum size metal-plate capacitors from the design kit were added to the nodes Di à;Di t.Simulated performance of the dynamic comparator is summarized in Table 2.In post-layout simulation over PVT corners,the comparator achieves a worst-case standard-deviation of the input-referred noise σnoise ;in ?471μV which is equivalent to 0.2LSB.In this SAR ADC,the input common-mode level of the comparator remains at mid-rail eV DD =2Tthroughout the conversion and hence the offset of the comparator appears as a static offset which does not affect linearity of the converter [30].Taking 3σoffset ;in ,the input-referred offset will reduce SNR by 0.2dB which corresponds to an ENOB loss of 0.03bits.The worst-case delay of the comparator working with an input voltage difference o LSB =2is 641ps which ?ts well within the half clock cycle time period of 833ps.Further reduction in input-referred noise and offset of the comparator can be achieved by including preampli ?er stage(s)in front of the comparator.Since a high-speed preampli ?er will signi ?cantly increase power consumption,it has been excluded in this work.

4.4.Split binary-weighted array DAC

The capacitive array DAC in a SAR ADC samples the input voltage and performs the DAC function of generating and subtracting the scaled reference voltage.Although the binary-weighted capacitor array provides high linearity,the exponential increase of the array

capacitance with resolution imposes area and power penalties.The speed limitation in SAR ADCs stems from the large settling times for the DAC caused by the RC time constants of the DAC capacitors and driver switches.Charging large capacitors in a binary-weighted array at high speeds will require extremely fast reference voltage buffers that consume enormous amount of power.Alternative DAC topologies are the C-2C ladder DAC [31]and split binary-weighted capacitive DAC [32].The C-2C ladder DAC suffers poor linearity due to parasitic capacitance at the interconnection nodes and hence is not widely employed in medium-to-high resolution SAR ADCs.The split binary-weighted capacitive DAC is commonly used to reduce the total DAC capacitance and the spread of the capacitor values in the array,thus providing area and power savings and also relaxing the settling time requirements.

Fig.11shows the 10-bit split array DAC which is composed of two binary-weighted capacitive arrays,a 5-bit main DAC and a 5-bit sub DAC separated by a bridge capacitor C B in the middle.The bridge capacitor C B is chosen to be a unit capacitor instead of a fractional value for better matching and ease of layout [32].Also the dummy unit capacitor at the end of the sub DAC has been avoided.Such a modi ?cation introduces a gain error of approximately 1LSB which can be readily corrected in the digital domain.The selection of the unit capacitor in the DAC involves important considerations such as thermal noise,mismatch and technology limitations.First we consider the thermal noise constraint.For an N-bit ADC with a full-scale range of V REF ,the quantization noise is given by P Q ?

V 2REF 12á22N

e11T

If the thermal noise is designed to be equal to the quantization

noise,a 3dB loss in SNR will occur.For such a scenario,the minimum value of sampling capacitance is given by C s ?

12kT á22N

V REF

e12T

For N ?10bits,V REF ?1.2V,the minimum sampling capacitance is

C s ?36fF.In this work,since a split-array capacitive DAC with top-plate sampling is used,the total sampling capacitance is 480fF which satis ?es the thermal noise constraint with good

margin.

Fig.10.Schematic of the double-tail dynamic comparator.

Table 2

Performance summary of the dynamic comparator.Parameter Value Supply voltage 1.2V Delay 641ps σnoise ;in 471μV σoffset ;in 8.24mV Current

115μ

Fig.11.Split-array DAC.

P.Harikumar,J.J.Wikner /INTEGRATION,the VLSI journal 50(2015)28–3833

Next we determine the mismatch-limited minimum value for C u assuming a single-ended implementation.Due to the bridge capacitor,the effect of capacitor mismatch in the sub DAC is reduced by 1=2M where M is the main DAC resolution.For relatively large values of M ,the main DAC dominates the total mismatch https://www.wendangku.net/doc/cf5263464.html,ually M Z N =2is chosen.Following the analysis given in [33],the worst-case standard deviation of the differential nonlinearity (DNL)for the M-bit main DAC is

σDNL ;MAX ???????????????2M à1p σu u

LSB M ;e13T

where LSB M ?V REF =2M ,C u and σu are the nominal value and standard deviation of the unit capacitor,respectively.For suf ?cient accuracy in the N-bit ADC [33],3σDNL ;MAX o LSB

;e14T

where LSB ?V REF =2N .Combining (13)and (14)we have

σu

C u

3á2N àM t1á

??????????????2M à1

p :e15T

For the typical metal capacitor,σΔC C ?K σ

???A

p ;e16T

C ?K C áA ;e17T

where σΔC =C àá

is the standard deviation of capacitor mismatch,K σis the matching coef ?cient,A is the capacitor area and K C is the capacitance density parameter.Also

σu C u ?1???2p áσΔC

:e18TCombining (15)–(18)results in a mismatch limited lower bound

for the unit capacitor given by C u Z 18áe2M à1Tá22eN àM TáK 2σáK C :

e19T

Using N ?10;M ?5and K σ;K C values from the design kit doc-umentation in (19)give C u Z 6fF.For a fully differential imple-mentation,the value of C u will be halved resulting in a mismatch-limited minimum C u ?3fF.Considering the minimum capacitor value de ?ned by the design kit and also the layout parasitics,C u ?15fF has been chosen in this work.

One potential drawback of the split-array architecture is its vulnerability to the parasitic capacitances connected to the nodes A and B as shown in Fig.11.The parasitic capacitances C P ;A and C P ;B are caused by the top-plate and bottom-plate parasitics of C B as well as the top-plate parasitic capacitance of the sub DAC and main DAC respectively.In [34],it is shown that C P ;B contributes only a gain error at the DAC output while C P ;A causes both gain error and code-dependent errors.The code-dependent errors degrade the linearity of the ADC.Hence it is bene ?cial to lower the value of C P ;A .One design technique is to ensure that the bottom-plate of C B ,which usually has higher parasitic capacitance,is connected to node B,i.e.the top-plate node of the main DAC thus lowering C P ;A .

The linearity of the split-array DAC was veri ?ed by computing the DNL,INL over MC simulations on the post-layout netlist.The plot of 3σINL ,3σDNL vs output code for 250MC runs is shown in Fig.12.From Fig.12,it is seen that the requirements on DAC INL/DNL for 10-bit linearity are satis ?ed.Similar to [30],inverters have been used to switch between the high and low reference voltages of the DAC.The power supply nodes of these inverters are connected to the V REF node (1.2V)output from the RVBuffer.The sizes of the inverters have been scaled such that the different capacitors of the DAC constitute approximately the same RC constant.

4.5.SAR controller

In this work,a synchronous binary search successive approx-imation register which utilizes a ring counter and shift register has

been implemented [35].A simpli ?ed block diagram of the SAR logic is shown in Fig.13.Static CMOS logic has been used to implement the SAR controller.The timing sequence of the SAR logic is shown in Fig.14.An entire conversion requires 12clock cycles of the SAR clock.A 600MHz SAR clock is used and the 50MHz sampling clock is generated by the SAR logic.Power consumption in the SAR block is mainly due to the 22?ip –?ops (FFs).The lower chain of FFs in Fig.13drives the inverter switches of the DAC.The delay through the FF and the RC settling time of the DAC should ?t within the half clock cycle period (833ps).Hence the FFs were designed to minimize the clock-to-Q https://www.wendangku.net/doc/cf5263464.html,yout of the ADC

The layout of the SAR ADC with on-chip RVBuffer is shown in Fig.15.The core-area of the chip is (225μm ?245μm).Approximately 70%of the core-area is taken up by the capacitive DAC arrays.NMOS capacitors enhanced by additional metal layers have been used for supply decoupling.The ADC uses two 1.2V supplies (analog,digital)and a 2.5V supply for the RVBuffer.Total decoupling capacitance for supplies used in the ADC is 85pF.For the RVBuffer,a supply decoupling capacitance of 25pF is used.Decoupling capacitance of 35pF and 25pF are used for the digital and analog supplies respectively.5.Simulation results

The simulation test-bench for the SAR ADC includes the entire pad frame,decoupling capacitors and source resistors for the

00.050.10.150.20.250.30.353σI N L , 3σ

D N L

[L S B ]

Code

Fig.12.INL/DNL of 10-bit split-array

DAC.

Fig.13.Synchronous SAR logic.

P.Harikumar,J.J.Wikner /INTEGRATION,the VLSI journal 50(2015)28–38

signal sources.The impact of the IO pads manifests in the form of parasitic capacitance and resistance.An inductance of 4nH is added in series to every IO pad connection to the ADC to mimic the bondwire.Since there is no on-chip bandgap reference gen-erator in this work,the input reference voltage V RefIn shown in Fig.5is provided through an analog input pad to the SAR ADC.Fig.16illustrates the necessity of the RVBuffer in the SAR ADC when an inductance of 4nH is used on the V RefIn input pad.Without the RVBuffer,the DAC ouput voltage V DACP suffers large ringing due to the bondwire inductance.From Fig.16,it is evident that the magnitude of ringing is much higher than 1LSB.Inclusion of the RVBuffer suf ?ciently lessens the ringing.

Without the RVBuffer,the SNDR of the ADC is a meagre 25dB which corresponds to an ENOB of 4bits further con ?rming the harmful impact of bondwire inductances.An ENOB 49bits is achieved after addition of the RVBuffer.

Simulations were performed to determine the impact of the bondwire inductance connected to the 2.5V supply node of the RVBuffer.The inductance connected to the V DD node of the RVBuffer was increased from 4nH up to 10nH.Simulations show that the ringing voltage on the V DD node due to transient current ?ow in the transistor M 11shown in Fig.5has a frequency of approximately 300MHz.For a frequency of 300MHz,the RVBuffer has a PSRRp ?27dB.The PSRRp of the RVBuffer suf ?ciently suppresses the impact of the ringing on V DD at the RVBuffer output node.Thus the output voltage V REF of the RVBuffer is not signi ?cantly disturbed.With an inductance of 10nH added to the power supply node of the RVBuffer,the ADC achieves a linearity corresponding to 9.6bits in the nominal PVT corner for post-layout simulation indicating that accurate settling of the DAC voltages is maintained.

Due to the varying current ?ow through the inductances,ringing will occur on the different supply domains of the SAR ADC.Based on simulation,the decoupling capacitance required for each supply domain has been estimated such that the ringing on the supplies is kept at acceptable limits.Digital output pads with in-built level-shifter and driver are used for the output bits of the

ADC.Simulations with realistic capacitance value of the logic analyzer probe were done to determine the required drive strength of the digital output pads.

The output spectrum of the SAR ADC for a low input frequency of 1MHz obtained using post-layout simulation is shown in Fig.17.For a 1MHz input,the ADC achieves an SNDR ?59.9dB and the corresponding ENOB ?9.66bits.The output spectrum of the SAR ADC for a near-Nyquist input frequency of 21MHz obta-ined using post-layout simulation is shown in Fig.18.

Post-layout simulation result for the dynamic performance of the SAR ADC with varying input frequency and a sampling rate of 50MS/s is shown in Fig.20.At an input frequency of 23MHz,the SNDR degrades by 2.7dB from its value at 1MHz.Hence the Effective Resolution Bandwidth (ERBW)is taken as 23MHz.The FoM of the ADC has been calculated as [30]FoM ?

Power 2ámin 2áERBW ;f s

àá:

e20T

The block-wise power breakdown for the SAR ADC in typical PVT corner with a total power consumption of 697μW is shown

Fig.14.Timing sequence of the SAR

logic.

https://www.wendangku.net/doc/cf5263464.html,yout of the SAR ADC.

0.40.450.50.550.60.650.70.750.8V D A C P [V ]

time [ns]

Fig.16.Ringing on DAC ouput due to inductance.

104

106

107108

?120

?100?80?60?40?200Frequency(Hz)

M a g n i t u d e (d B )

Fig.17.Output spectrum of the SAR ADC for low-frequency input.

P.Harikumar,J.J.Wikner /INTEGRATION,the VLSI journal 50(2015)28–3835

Fig.19.It is seen that the SAR logic forms the dominant source of power consumption which agrees well with that of SAR ADCs with similar speci?cation reported in[3,30,36,37].

Post-layout simulation of the ADC including device noise was performed for the typical and worst PVT corners with near-Nyquist differential inputs and a sampling rate of50MS/s.Tran-sient noise simulation,which has been previously used to deter-mine ADC performance[38],was utilized to incorporate device noise.Table3compares the performance of the proposed ADC with other state-of-the-art SAR ADCs.It is seen that the proposed ADC is very competitive in terms of FoM and area when compared with SAR ADCs of similar speci?cations.

To ascertain the impact of process variation and device mis-match on the ADC performance,MC simulations were run on the post-layout netlist of the full ADC including the on-chip RVBuffer. For50MC runs with transient noise enabled,the SAR ADC with on-chip RVBuffer achievesμENOB?9:2bits andσENOB?0:46bits for sinusoidal inputs at near-Nyquist frequency.

5.1.Assessing noise simulation in the SAR ADC

The simulation results of the ADC in the Worst column of Table3are analysed to verify the noise performance.The total input-referred noise power in the SAR ADC is given by

P N?N QtN ComptN BufftN SH;e21Twhere N Q is the quantization noise,N Comp is the input-referred noise power of the comparator,N Buff is the input-referred noise power of the RVBuffer,and N SH is the thermal noise of the sampling network.For the fully differential SAR ADC,the quanti-zation noise is given by

N Q?LSB2

e2á1:2T2

e2á12T

?4:578eà07V2;e22T

From the data provided in Sections4.3,4.4and4.1,we have the

worst-case noise power from the circuit blocks as

N Comp?σ2noise;in;comp?e0:2LSBT2?0:48N Q V2;e23T

N Buff?σ2noise;in;Buff?e0:086LSBT2?0:09N Q V2;e24T

N SH?

2kT

C s

?2á1:38eà23á398

480eà15

V2%0:05N Q V2:e25T

Using(21)–(25),the total noise power in the ADC can be

determined.The input signal power for the ADC is given by

P S?

2V in;pp

2á

???

V2:e26T

The SNR can be derived as

SNR?10log

P S

:e27T

Initially the ADC is simulated for the worst corner without

including noise.This resulted in an SNDR?57.2dB for a

V in;pp?1:14V.Since there is no thermal noise involved,the SNDR

is due to the quantization noise and non-linearities alone.The

power of the(quantization noisetnon-linearities)P N;QD is found

to be

P N;QD?1:2382eà06V2:e28T

Using(23)–(25),the total worst-case noise contribution from the

circuit blocks is found as

P N;Ckt?0:62N Q V2?2:8230eà07V2:e29T

The total noise and non-linearities in the ADC is given by

P N;total?P N;QDtP N;Ckt?1:5205eà06V2:e30T

For a V in;pp?1:14V,the SNDR is found as

SNDR calc?10log

P S

P N;total

?56:31dB;e31T

which corresponds to an ENOB of9.1bits.The ADC was simulated

for the worst corner with transient noise enabled which resulted

SNDR sim?55:99dB;e32T

which corresponds to an ENOB of9bits.From(31)and(32),it is

found that the noise estimation for the ADC is suf?ciently accurate.

101010108

?120

?100

?80

?60

?40

?20

Frequency(Hz)

(

)

Fig.18.Output spectrum of the SAR ADC for near-Nyquist input

frequency.

Fig.19.Power breakdown for the SAR ADC(typical PVT corner).

Input frequency (Hz)

(

)

Fig.20.Dynamic performance versus input frequency.

P.Harikumar,J.J.Wikner/INTEGRATION,the VLSI journal50(2015)28–38 36

6.Conclusion

In this paper,a power-ef?cient SAR ADC implemented in65nm CMOS was presented.An on-chip reference voltage buffer alle-viates the ringing on the DAC reference due to bondwire induc-tances.The design of the RVBuffer and its impact on the ADC performance have been elaborated with relevant simulation results.The performance of the various circuit blocks has been characterised through extensive post-layout simulations.The ADC achieves an FoM of25fJ/conversion-step with a power consump-tion of697μW at a sampling rate of50MS/s.The ADC occupies an active area of0.055mm2only.

Acknowledgments

The authors would like to express their gratitude to Dai Zhang, Pavel Angelov and Ameya Bhide for the valuable technical discus-sions pertaining to the design aspects and layout of the SAR ADC.

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Speci?cation JSSC'10[30]a JSSC'11[39]a CICC'12[40]a ISSCC'13[41]a ISSCC'12[42]a TVLSI'13[20]a This work

Typ Worst

Technology(nm)130130909040906565 Supply voltage(V) 1.2 1.2 1.2 1.2 1.11 1.2 1.2 Sampling rate(MS/s)5040505040305050 ENOB(bit)9.188.1110.511.59.159.169.259 Power(mW)0.8260.55 4.7 4.2NA0.980.6970.718

FoM(fJ/conv.-step)295063.936.163572530 Active area(mm2)0.0520.320.1180.0970.080.10.0550.055

a Chip measurement results.

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Prakash Harikumar received the Master of Science in electrical engineering from Link?ping University,Sweden in2011.He is currently working towards the Ph.D degree at the Division of Integrated Circuits and Systems at Link?ping University. His researchmainly focuses on analog-to-digital converters and analog front-end circuits.

J Jacob Wikner(M’12)received his PhD from the Department of Electrical Engineering,Link?ping University,Sweden,in2001.He has worked as research engineer at Ericsson Microelectronics,senior analog design engineer at In?neon Technologies,and senior design engineer and chip architect at Sicon Semiconduc-tor.Dr.Wikner is an associate professor at Link?ping University since2009.His research interests include biologically inspired architectures,high-speed A/D and D/A converters,and general analog and mixedsignal designs.He holds six patents, has published40scienti?c papers,and has co-authored“CMOS Data Converters for Telecommunication”.He is the co-founder of CogniCatus and AnaCatum Design AB.

P.Harikumar,J.J.Wikner/INTEGRATION,the VLSI journal50(2015)28–38 38

包络函数方法

包络函数方法低维纳米结构中电子态的计算是一个基本而重要的问题。一般来说，计算纳米结构中的电子态有两种方法，一种是利用第一性原理计算，第二种是有效质量包络函数近似。第一性原理是比较常用的一种方法，它的计算结果相对来说比用有效质量包络函数近似的结果更可靠，但是用第一性原理来计算较大的纳米结构(里面含有几百万个原子)是非常困难的，因为它需要一个超级计算系统。相比之下，用有效质量包络函数近似的方法就比较合适了，在个人计算机上就能实现，所以Burt提出的包络函数方法被认为是描述纳米结构电子态的最有前景的方法。先将包络函数方法的基本理论介绍如下：首先，包络函数方法是在以下近似条件下得到的计算纳米结构电子态的方法：（1）有限质量近似。（2）忽略了真实离子势场中迅速变化的震荡分量，近似认为载流子只受外场的作用。（3）保证异质结两边的态具有同样的对称性，例如对于GaAs/AlGaAs系统，要保证电子同处于导带的Γ谷中。此时，如果晶体中存在微扰势称V p(r)，则电子运动的薛定谔方程为： ( 其中是没有微扰的晶体哈密顿量。如果微扰势是个空间缓变量，且其强度小到不足以引起带之间的耦合，则电子波函数可以表示为一个空间缓变函数与带边波函数的乘积。称为包络函数。如果能带是非简并的，例如导带，在导带底附近的能量可近似用有效质m*表示其中是导带边能量，则包络函数满足

如果能带是简并的，例如价带顶，则波函数可表示为包络函数与带边波函数)乘积的线性组合满足一组联立的有效质量方程组其中称为有效质量参数。若无外界的微扰势，则在每种材料内部就电子而一言，有效质量方程简化为一平面波方程。在界面附近，势是突变的，有效质量近似不再成立，暂时先不考虑这一点。对于两种材料，它们的有效质量和带边能量是不同的。引入(z)和有效势V(z)，其中 (z)= (z)= 是两种材料导带边能量之差，也就是导带带阶。包络函数方程可写为:

英语花费四种用法的区别

spend的主语必须是人，常用于以下结构： (1)sb. spend time ／money on sth. 在……上花费时间(金钱)。 (2) sb.spend time ／ money (in) doing sth.花费时间(金钱)做某事。例：I spent fifty yuan on the coat. = I spent fifty yuan (in) buying the coat. 我花50元买了这件大衣。 He spent three days on the work. = He spend three days (in) doing the work. 我干这项工作用了3天。 (3). spend money for sth. 花钱买例如： His money was spent for books. 他的钱用来买书了。 cost的主语是物或某种活动，还可以表示"值"，常见用法如下： (1)sth. costs (sb.) ＋金钱,某物花了(某人)多少钱。例：A new computer costs a lot of money. 买一台新电脑要花一大笔钱。 (2) (doing) sth. costs (sb.) ＋时间,某物(做某事)花了(某人)多少时间。例：Remembering these new words cost him a lot of time. 他花了大量时间才记住了这些单词。注意：cost的过去式及过去分词都是cost,并且不能用于被动句。 take后面常跟双宾语，常见用法有以下几种： (1) It takes sb. ＋时间＋to do sth. 做某事花了某人多少时间。例：It took them three years to build this road. 他们用了三年时间修完了这条路。 (2)doing sth. takes sb. ＋时间,做某事花了某人多少时间。例：Repairing this car took him the whole afternoon. 他花了一下午修车。 pay的基本用法是： (1) pay (sb.) money for sth. 付钱(给某人)买……。例：I have to pay them 20 pounds for this room each month. 我每个月要付20英磅的房租。 (2)pay for sth. 付……的钱。例：I have to pay for the book lost. 我不得不赔丢失的书款。 (3)pay for sb.替某人付钱。例：Don‘t worry!I'll pay for you. 别担心，我会给你付钱的。 (4)pay sb.付钱给某人。例: They pay us every month.他们每月给我们报酬。 (5)pay money back 还钱。(6)pay off one's money还清钱。例：May I borrow 12 yuan from you? I'll pay it back next week. 你能借给我12块钱吗？下周还你。

包络解调法及其诊断

包络解调法及其诊断包络解调法是故障诊断中较常用的一种方法，它可非常有效地识别某些冲击振动。从而找到该冲击振动的振源。例如，当轴承或齿轮表面因疲劳或应力集中而产生剥落和损伤时，会产生周期性的冲击振动信号，如图4—25所示。从图4—25个可以看出，信号包括两部分：—部分是载频信号，即系统的自由振荡信号及各种随机干扰信号的频率，是图形中频率成分较高的信号；第二部分是调制信号，即包络线所包围的信号。它的频率较低，多为故障信号。因此．若要对故障源进行分析，就必须把低频信号(或调制信号)从高频信号(或载频信号)中分离出来。这一信号分离、提取过程，被称为信号的包络解调。对分离提取出来的包络信号进行特征频率和幅度分析，就能准确可靠地诊断出如轴承和齿轮的疲劳、切齿、剥落等故障。

目前分析高频冲击的有效方法之一是共振解调(包络处理)，即取振动时域波形的包络线，然后对包络线进行频谱分析。由于包络线处理可找出反复发生振动的规律，根据轴承的特征频率，就可诊断出轴承或齿轮故障的部位。研究表明，当轴承或齿轮无故障时，在共振解调频谱中没有高阶谱线;有故障时，共振解调频谱中出现高阶谱线。当齿轮发生疲劳裂纹时，齿轮刚度的变化会引起齿轮振动噪声信号瞬时频率(相位)和幅值的变化。但裂纹由于只影响齿轮刚度，齿形无大变化，故振动噪声信号在频域中无明显征兆，因此频谱分析对裂纹诊断基本无效。可采用时域平均法分析。如果齿轮同时存在其它类型的故障，则时域平均法的可靠性不高。此时可试用希尔伯特变换或自适应滤波技术提取相位信息，也可试用共振解调分析技术即包络谱分析法。一、包络分析法进行故障诊断的原理当轴承或齿轮某一元件表面出现局部损伤时，在受载运行过程中

现在完成时的用法解析

Lead in 一般过去时导入：一般过去时的概念一般过去时表示过去某个时间发生的动作或存在的状态。 I lost my pen.(过去时) I have lost my pen.（现在完成时）过去时一般表示过去所发生的动作或存在的状态。“我把笔丢了”，说话人只是想告诉对方在过去的某一个时间里他的笔丢了，仅此而已。（仅仅是在陈诉过去的一个事实，与现在没有关系） New lesson 一．现在完成时的构成：助动词have/has(not) +动词过去分词 She has turned on the lights. 肯定式：have/ has+过去分词否定式：haven’t/hasn’t+过去分词疑问式：把have/has 提到主语前面肯定回答：Yes,…have/has 否定回答：No,…..haven’t/hasn’t 二．用法 1.表示过去发生的动作对现在造成的影响或结果. 例如:She has gone. 她走了. She went in the past.(She is not here

now.) I have just cleaned my hands. 我刚洗过手。（“洗手”是发生在过去的动作，对现在造成的结果是“手干净了”） I have closed the door. (The door is close now.) She has turned on the lights. (The lights are on now.) He has written his name on the blackboard. (The name is on the blackboard now.) Mother has cooked the dinner. (We can have dinner now.) You have seen the film. （You know what the film is about.) We have cleaned the classroom. (The classroom is clean now.) 2. 表示动作发生在过去，并且一直延续到现在，甚至还可能继续延续下去。这时常和since所引导的短语或从句或for引导的短语连用(for有时可以省去)。以及so far, by now, these days, in the last/past … years/days…等连用。 I have lived here for over ten years. （表示他现在还在这里居住，并且还有可能继续住下去）比较：I lived here ten years ago.(仅仅说明了他十年前在这里记住过的事实,不代表现在他还住在这里) He has studied here since 2006. 都用How long 提问，例： We have learned English for three years. We have learned English since three years ago.

四种花费和四种提供的用法

英语中“花费”的四种用法王朝红的工作室英语花费四种用法 spend的主语通常是人，往往用于以下句型： 1. (sb) spend some money/some time on sth。 2. (sb)spend some money/some time(in)doing sth。例如： I spent fifty yuan on the coat。 = I spent fifty yuan (in) buying the coat. 我花50元买了这件大衣。 He spent three days on the work. = He spend three days (in) doing the work. 我干这项工作用了3天。 3.spend money for sth. 花钱买……。例如：His money was spent for books. 他的钱用来买书了。 take常用于“占用、花费”时间，后面常跟双宾语，其主语通常为形式主语“it”或物。句式是： 1. It takes/took sb.some time to do sth 例如：It will take me two days to do the work. 这项工作花了2天时间。 2. Doing sth./Sth.takes sb.some time. 例如： The work will take me two days。这项工作花了2天时间。

Repairing this car took him the whole afternoon. 他花了一下午修车。 It took me three years to draw the beautiful horses。 =Drawing the beautiful horses took me three years。画这些漂亮的马花费了我3年时间。 pay为“付款、赔偿”之意，主语通常是人，句型 1. sb. pays some money for sth 例如： I paid fifty yuan for the coat。我花50元买了这件大衣。 2. pay (sb。) money for sth. 付钱(给某人)买……。例如：I have to pay them 20 pounds for this room each month. 我每个月要付20英磅的房租。 3. pay money back 还钱。例如：May I borrow 12 yuan from you? I'll pay it back next week. 你能借给我12块钱吗?下周还你。 4. pay off one's money 还清钱。 cost的主语是物或某种活动，还可以表示“值”。句型 1. sth. costs (sb。) +money, 某物花了(某人)多少钱。

常用短语及搭配精粹

枷Cd)一点，一些扒；Olooksabitlarge．看起来有点大。 l“HeknowsabitOfGermam他懂点德语。轴蛔chof一束；一捆 He gave his girlfriend a bunch Of roses 9s a birthday gift．他送女友一束玫瑰作为生日礼物。 la'0wdOf一群；许多 A crowd Of children with bouquets 1n their hands rushed Over tO the foreign guests，一群孩尸手持鲜花向外国客人咆去． afew几个；一些 HewiIIbe here in a Jew days．他过几天就来。．goed／greatmany很多：许多 Mr Liu rang her up a good many times．刘先生多次打电话给她．．good／greatdeal(O，)大量；很多 I'm afraid I've gtven you s good deal“trouble．我恐怕给你添了很多麻烦。 After taking the medicine he i'nOW a great deal better．服药后，他现在觉得好多了。 alot(d)许多；大量 The students learned a lot from the teacher．学生们从老师那里学到了许多知识。 He borrowed s lot Of books from the old胴n．他从那位老人那里借丁很多书． alargeamotmtOf许多(按不可数名词) A 1arge amountOfmoney has been wasted．大量的金钱被浪费掉丁。 9(1arge)quantityOf许多(接可数或不可数名词) Heateo smallquantityO{rice．他吃了少量的米饭。 anmberOf一壁：若干 Quite a number 9f students inour department are from the north．我们系有许多学生来刨[方。 aseriesOf一系列的 A series Of reports will be given On the war．关于这场战争将有一系列的报道。 asetOf一组，，一套 The factory bought a set Of equtpment from abroad．这家工厂从国外买厂一套设备。 ovametyOt多样，种种，多种类 The shoppingcentresellsavartetyOrgoods．这个购物中心出售许多种商品。 ~,all首要的；最重要的·：．That心what IP陀f畸above，11．那是我最喜欢的东西．删lqto根据；依照 According tO theweather reagort,出CrC will加rain this afternoolL

包络定理

2．包络定理1 在上图表示的最大值函数与目标函数的关系中，我们看到，当给定参数a 之后，目标函数中的选择变量x 可以任意取值。如果x 恰好取到此时的最优值，则目标函数即与最大值函数相等。而且，我们还可以注意到，当目标函数与最大值函数恰好相等时，相应的目标函数曲线与最大值函数曲线恰好相切，即它们对参数的一阶导数相等。对这一特点的数学描述就是所谓的“包络定理”。 ⑴ 包络定理：无约束模型设最大值函数为： ()((),)V a f x a a = 对参数a 求导有： (0)a x a a x dx V f f f f da =+== 其中，a f 在最优解处取值。 ▼ 另一种表述设模型 max (,)x f x a 的最优解为()x x a **=；代入原目标函数(,)f x a 即得最大值函数： ()((),)V a f x a a * 上式两边对参数a 求导得： [][((),)]a a x a a dx V f x a a f f f da * *** ??==+=???? 其中，方括号右边的下标“a ”表示对参数a 求导，上标“*”表示求导后的结果在最优解处取值。由于是在最优解处取值，故由一阶必要条件可知0x f =。于是有第三个等式。第三个等式中的[]a f *表示原目标函数(,)f x a 对a 求导后在最优解处取值。 ⑵ 包络定理：等式约束模型设最大值函数为： ()((),(),)V a L x a a a λ= 对参数a 求导有： (0)a x a a x dx d V L L L L L L da da λλλ=++=== 其中，a L 在最优解处取值。 ▼ 另一种表述

(英语语法)四种完成时态

LESSON EIGHT 四种完成时态主系表现在：You are rich. 过去：You were rich. 将来：You will be rich. 过去将来：You would be rich. There be 现在：There is a book on the desk . 过去：There was a book on the desk. 将来：There will be a book on the desk. 过去将来：There would be a book on the desk.主谓宾状现在：You study English in the school. 过去时：You studied English in the school. 将来时: You will study English in the school. You are going to study English. You are to study English. are about to study English would study English in the scho You were going to study English. You were to study English. You were about to study English. You are studying English. You were studying English. You will be studying English. You woud be studying English.

设计SAR ADC驱动电路,第一部分：ADC工作原理详解

Designing SAR ADC Drive Circuitry by Rick Downs, Applications Engineering Manager and Miro Oljaca, Systems Engineer Data Acquisition Products, Texas Instruments, Incorporated Part I: A Detailed Look at SAR ADC Operation Designing buffer circuitry for driving successive-approximation (SAR) ADCs requires knowledge of the load that the inputs present. Specifications in data sheets may mislead the user into thinking that analog inputs, for example, are static when in fact they are a very dynamic load. This three-part article will look at the architecture of modern SAR ADCs, and examine the conversion process in detail. In this first part the operation of a modern SAR ADC is discussed. A detailed, step-by-step analysis is then given, illustrating the sampling and conversion process. The final part discusses charge distribution during the sampling process. This analysis will give the user of these devices a better understanding of the inner operations of a charge-redistribution ADC. 1. The SAR ADC Structure Fig. 1: Representative SAR Input Stage Fig. 1 shows a representative three bits of a typical SAR ADC (the ADS8361). Looking at this example, we will examine a three-bit conversion sequence. For our analysis, we will assume that the most significant bit (MSB) capacitor has a value of 20 pF. The capacitor nearest to the MSB capacitor will have half its value, or 10 pF and the least significant bit (LSB) capacitor will have one-quarter of the MSB capacitor value, or 5 pF. A termination capacitor has the same value as the LS B capacitor. The effect of this is that the sum of all the capacitors below the MSB capacitor becomes 20 pF, or the same value as the MSB capacitor.

“四个花费”spend,cost,take, pay讲解及对应中考练习

“四个花费”讲解及对应中考练习 spend，cost，take, pay spend，cost，take和pay的区别是历年考试的必考内容之一，虽然它们都可以表示"花费"，但用法却不尽相同，讲解如下： spend的主语必须是人，常用于以下结构： (1) spend time ／money on sth. 在……上花费时间(金钱)。例：I spent two hours on this maths problem. 这道数学题花了我两个小时。 (2) spend time ／money (in) doing sth. 花费时间(金钱)做某事。例：They spent two years (in) building this bridge. 造这座桥花了他们两年时间。 (3)spend money for sth. 花钱买……。例：His money was spent for books. 他的钱用来买书了。 cost的主语是物或某种活动，还可以表示"值"，常见用法如下： (1)sth. costs (sb.) ＋金钱,某物花了(某人)多少钱。例：A new computer costs a lot of money. 买一台新电脑要花一大笔钱。 (2) (doing) sth. costs (sb.) ＋时间,某物(做某事)花了(某人)多少时间。例：Remembering these new words cost him a lot of time. 他花了大量时间才记住了这些单词。注意：cost的过去式及过去分词都是cost,并且不能用于被动句。 take后面常跟双宾语，常见用法有以下几种： (1) It takes sb. ＋时间＋to do sth. 做某事花了某人多少时间。例：It took them three years to build this road. 他们用了三年时间修完了这条路。 (2)doing sth. takes sb. ＋时间,做某事花了某人多少时间。例：Repairing this car took him the whole afternoon. 他花了一下午修车。 pay的基本用法是： (1) pay (sb.) money for sth. 付钱(给某人)买……。例：I have to pay them 20 pounds for this room each month. 我每个月要付20英磅的房租。 (2)pay for sth. 付……的钱。例：I have to pay for the book lost. 我不得不赔丢失的书款。 (3)pay for sb. 替某人付钱。例：Don‘t worry!I'll pay for you. 别担心，我会给你付钱的。 (4)pay sb. 付钱给某人。例: They pay us every month.他们每月给我们报酬。 (5)pay money back 还钱。例：May I borrow 12 yuan from you? I'll pay it back next week. 你能借给我12块钱吗？下周还你。 (6)pay off one's money还清钱。【真题对应练习】 1.（广州某校2015期中）--- How much does your new bike ___________ ?

初二英语上册语法的复习方法与详细解释

初二英语上册语法的复习方法与详细解释初二英语上册语法的复习方法与详细解释 38)help用法举例 help既可以作名词，也可以作动词。 1.help作名词，意为"帮助"。如： Heneedssomehelp.他需要一些帮助。 2.help作动词，也是"帮助"的意思。如： Canyouhelpme?你能帮帮我吗？ 3.help的结构： helpsb(to)dosth帮助某人做某事 =helpsbwithsth帮助某人做某事如：Theywanttohelptheboycarrytheheavybox. =Theywanttohelptheboywiththeheavybox. 他们想要帮助那位男孩搬那个重箱子。 20)关于like的用法 like可以作动词，也可以作介词。 Doyoulikethecolor?你喜爱这种颜色吗？ like后可接不定式（liketodosth），也可接动词的-ing分词（likedoingsth），有时意思不尽相同。如： Shelikeseatingapples.她喜爱吃苹果。（习惯） Shelikestoeatanapple.她喜爱吃一粒苹果。（平常不喜欢吃）

like与would连用，后接不定式，表示愿望或客气的请求。如： Wouldyoulikeacupoftea?您愿意喝杯茶吗？ "喜欢某人做某事"可以用结构"likesbtodosth/doingsth"。如：Theyalllikemetosing/singingEnglishsongs. 他们都喜欢我唱英文歌。 2、like作介词，可译成"像......"。如： Sheisfriendlytouslikeamother.她对我们友好，就像母亲一样。 Itlookslikeanorange.它看起来像个桔子。 3、区分以下句子： A.Whatdoeshelooklike?他长相如何？(指一个人的外貌特征) B.Whatishelike?他人怎么样？(指人的性格特点) C.TheboylikePeterisoverthere.(句指外貌相似) D.AboylikePetercan'tdoit.(指性格相似) 19)alittle,afew与abit(of)alittle,afew与abit(of)都有" 一些、少量"的意义。他们的区别: 1.alittle意为"一些、少量"，后接不可数名词。如： Thereisalittlewaterinthebottle.瓶子里有一点水。还可以接形容词。如： Heisalittleshy.他有些害羞。 2.afew意为"一些、少数"，后接复数的可数名词。如： Thereareafewpeopleintheroom.房间里有一些人。 3.abit意为"一点儿"，后接形容词。如： It'sabitcold.有点冷。

包络检波器的设计与实现

2013~2014学年第一学期《高频电子线路》课程设计报告题目：包络检波器的设计与实现专业：电子信息工程班级：11电信1班姓名：指导教师：冯锁电气工程学院 2013年12月12日

任务书

摘要调幅波的解调即是从调幅信号中取出调制信号的过程，通常称为检波。检波广义的检波通常称为解调，是调制的逆过程，即从已调波提取调制信号的过程。对调幅波来说是从它的振幅变化提取调制信号的过程；对调频波，是从它的频率变化提取调制信号的过程；对调相波，是从它的相位变化提取调制信号的过程。工程实际中，有一类信号叫做调幅波信号，这是一种用低频信号控制高频信号幅度的特殊信号。为了把低频信号取出来，需要专门的电路，叫做检波电路。使用二极管可以组成最简单的调幅波检波电路。调幅波解调方法有二极管包络检波器、同步检波器。目前应用最广的是二极管包络检波器，不论哪种振幅调制信号，都可采用相乘器和低通滤波器组成的同步检波电路进行解调。但是，普通调幅信号来说，它的载波分量被抑制掉，可以直接利用非线性器件实现相乘作用，得到所需的解调电压，而不必另加同步信号，通常将这种振幅检波器称为包络。为了生动直观的分析检波电路，利用了最新电子仿真软件Multisim11.0进行二极管包络检波虚拟实验,Multisim具有组建电路快捷、波形生动直观、实验效果理想等优点。计算机虚拟仿真作为高频电子线路实验的辅助手段,是一种很好的选择,可以加深学生对一些抽象枯燥理论的理解,从而达到提高高频电子线路课程教学质量的目的。

目录第1章设计目的及原理 (4) 1.1设计目的和要求 (4) 1.1设计原理 (4) 第2章指标参数的计算 (8) 2.1电压传输系数的计算 (8) 2.2参数的选择设置 (8) 第3章 Multisim的仿真结果及分析 (11) 总结 (16) 参考文献 (17) 答辩记录及评分表 (18)

四种花费和四种提供的用法

四种花费和四种提供的用法公司内部编号：（GOOD-TMMT-MMUT-UUPTY-UUYY-DTTI-

例如：It will take me two days to do the work. 这项工作花了2天时间。 2. Doing sth./Sth.takes sb.some time. 例如： The work will take me two days。这项工作花了2天时间。 Repairing this car took him the whole afternoon. 他花了一下午修车。 It took me three years to draw the beautiful horses。 =Drawing the beautiful horses took me three years。画这些漂亮的马花费了我3年时间。 pay为“付款、赔偿”之意，主语通常是人，句型 1. sb. pays some money for sth 例如： I paid fifty yuan for the coat。我花50元买了这件大衣。 2. pay (sb。) money for sth. 付钱(给某人)买……。例如：I have to pay them 20 pounds for this room each month.我每个月要付20英磅的房租。

包络检波器的设计与实现

目录前言 (1) 1 设计目的及原理 (2) 1.1设计目的和要求 (2) 1.1设计原理 (2) 2包络检波器指标参数的计算 (6) 2.1电压传输系数的计算 (6) 2.2参数的选择设置 (6) 3 包络检波器电路的仿真 (9) 3.1 Multisim的简单介绍 (10) 3.2 包络检波电路的仿真原理图及实现 (10) 4总结 (13) 5参考文献 (14)

前言调幅波的解调即是从调幅信号中取出调制信号的过程，通常称为检波。广义的检波通常称为解调，是调制的逆过程，即从已调波提取调制信号的过程。对调幅波来说是从它的振幅变化提取调制信号的过程；对调频波，是从它的频率变化提取调制信号的过程；对调相波，是从它的相位变化提取调制信号的过程。工程实际中，有一类信号叫做调幅波信号，这是一种用低频信号控制高频信号幅度的特殊信号。为了把低频信号取出来，需要专门的电路，叫做检波电路。使用二极管可以组成最简单的调幅波检波电路。调幅波解调方法有二极管包络检波器、同步检波器。目前应用最广的是二极管包络检波器，不论哪种振幅调制信号，都可采用相乘器和低通滤波器组成的同步检波电路进行解调。但是，对普通调幅信号来说，它的载波分量被抑制掉，可以直接利用非线性器件实现相乘作用，得到所需的解调电压，而不必另加同步信号，通常将这种振幅检波器称为包络。为了生动直观的分析检波电路，利用最新电子仿真软件Multisim11.0进行二极管包络检波虚拟实验。Multisim具有组建电路快捷、波形生动直观、实验效果理想等优点。计算机虚拟仿真作为高频电子线路实验的辅助手段，是一种很好的选择，可以加深学生对一些抽象枯燥理论的理解，从而达到提高高频电子线路课程教学质量的目的。

SAR ADC

SARADC逐次逼近寄存器型ADC设计报告课程名称：数模混合集成电路设计专业（年级）：集成电路设计与集成系统（09）组员（学号）：提交日期：2012/12/26 序号评分规则得分 1 电路结构合理正确，工作原理描述准确详细（10分） 2 理论计算清晰准确，参数设计合理（10分） 3 仿真网表完整正确，仿真结果正确，结果说明准确详实（20分） 4 版图绘制准确，标注明确（10分） 5 撰写格式规范，结构合理，层次清晰，内容详细充实（10分）

总分

一、课程设计参数要求: 设计一个10bit 逐次逼近寄存器型模数转换器SAR ADC 分辨率 10bit 采样频率 100KHz 功耗 < 1mW 电源电压 2.5V 面积 < 1mm 2 工作温度 0~80℃ 工艺技术 0.25um 二、基本结构及原理： 1. 逐次逼近寄存器型模数转换器（SAR ADC ）整体结构： 2. 逐次逼近寄存器型模数转换器（SAR ADC ）工作原理： SAR ADC 其基本结构如图1所示，包括采样保持电路(S/H)、比较器(COMPARE)、数/模转换器(DAC)、逐次逼近寄存器(SAR REGISTER)和逻辑控制单元(SAR LOGIC)。模拟输入电压V IN 由采样保持电路采样并保持，为实现二进制搜索算法，首先由SAR LOGIC 控制N 位寄存器设置在中间刻度，即令最高有效位MSB 为“1”电平而其余位均为“0”电平，此时数字模拟转换器DAC 输出电压V DAC 为0.5V REF ，其中V REF 为提供给ADC 的基准电压。由比较器对V IN 和V DAC 进行比较，若V IN >V DAC ，则比较器输出“1”电平，N 位寄存器的MSB 保持“1”电平；反之，若V IN

四种花费用法讲解

Take\spend\pay\cost表示花费的时候用法1、It takes sb some time to do sth. 该句型只表示花费时间，it是形式主语，真正的主语是动词不定式。sb是宾格形式，some time 是一段时间。 Eg： a.It took the boys two weeks to plant the trees last spring. b.It takes me ten minutes to walk to school every day. c.It will take us about 30 minutes to finish listening the story. 2. Sb spends some time/money (in) doing sth. Sb spends some time/money on sth. 该句型可表示花费时间，也可以表示花费金钱。主语必定是人，做某事可以用动词表示，也可用名词表示。 d.We spent the whole day going hiking in Mount Tai last summer. e.Did you spend ten yuan on the pen? f.All the boys spent about five minutes

remembering the ten English words. 除此之外，还有pay和cost也可以表示花费金钱。 Pay 常用for连用，构成pay for 意思是赔尝、付款。主语必须是人。 I paid for the book yesterday. 昨天我买了这本书。 I paid ten yuan for the book yesterday. 昨天我花了十元钱买了这本书。 You should pay for the book if you lose it. 如果你丢了这本书，你就应该赔偿。 Cost 表示值多少钱，也表示花费。 The magazine costs twenty yuan. The bicycle cost me eight hundred and fifty yuan.

A 10 bit 50 Msps SAR ADC in 65 nm CMOS with on chip reference voltage buffer

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最新现在完成时讲解和练习(有答案)

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“四个花费”spend,cost,take, pay讲解及对应中考练习

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包络检波器的设计与实现

四种花费和四种提供的用法

包络检波器的设计与实现

SAR ADC

四种花费用法讲解

英语花费四种用法的区别