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74ALVCH16269DLG4中文资料

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FEATURES

DESCRIPTION/ORDERING INFORMATION

DGG OR DL PACKAGE

(TOP VIEW)

NC ? No internal connection

SN74ALVCH16269 12-BIT TO24-BIT REGISTERED BUS EXCHANGER

WITH3-STATE OUTPUTS

SCES019N–JULY1995–REVISED JULY2004

?Member of the Texas Instruments Widebus?

Family

?Operates From1.65V to3.6V

?Max t pd of5ns at3.3V

?±24-mA Output Drive at3.3V

?Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

?Latch-Up Performance Exceeds250mA Per

JESD17

?ESD Protection Exceeds JESD22

–2000-V Human-Body Model(A114-A)

–200-V Machine Model(A115-A)

This12-bit to24-bit registered bus exchanger is

designed for1.65-V to3.6-V V CC operation.

The SN74ALVCH16269is used in applications in

which two separate ports must be multiplexed onto,

or demultiplexed from,a single port.The device is

particularly suitable as an interface between

synchronous DRAMs and high-speed

microprocessors.

Data is stored in the internal B-port registers on the

low-to-high transition of the clock(CLK)input when

the appropriate clock-enable(CLKENA)inputs are

low.Proper control of these inputs allows two

sequential12-bit words to be presented as a24-bit

word on the B port.For data transfer in the B-to-A

direction,a single storage register is provided.The

select(SEL)line selects1B or2B data for the A

outputs.The register on the A output permits the

fastest possible data transfer,extending the period

during which the data is valid on the bus.The control

terminals are registered so that all transactions are

synchronous with CLK.Data flow is controlled by the

active-low output enables(OEA,OEB1,OEB2).

ORDERING INFORMATION

T A PACKAGE(1)ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube SN74ALVCH16269DL

SSOP-DL ALVCH16269

Tape and reel SN74ALVCH16269DLR

-40°C to85°C TSSOP-DGG Tape and reel SN74ALVCH16269DGGR ALVCH16269

VFBGA-GQL SN74ALVCH16269KR

Tape and reel VH269

VFBGA-ZQL(Pb-free)74ALVCH16269ZQLR

(1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at

https://www.wendangku.net/doc/ca6045483.html,/sc/package.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

GQL OR ZQL PACKAGE

(TOP VIEW)J H G F E D C B A 2

SN74ALVCH16269

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

SCES019N–JULY 1995–REVISED JULY 2004

To ensure the high-impedance state during power up or power down,a clock pulse should be applied as soon as possible,and OE should be tied to V CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.Due to OE being routed through a register,the active state of the outputs cannot be determined before the arrival of the first clock pulse.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic https://www.wendangku.net/doc/ca6045483.html,e of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

TERMINAL ASSIGNMENTS

23456A 2B3OEB1OEA OEB2CLKENA22B4B 2B12B2GND GND 2B52B6C A2A1V CC V CC 2B72B8D A4A3GND

GND

2B92B10E A6A52B112B12F A7A81B111B12G A9A10GND GND 1B91B10H A11A12V CC V CC 1B71B8J 1B11B2GND GND 1B51B6K

1B3

SEL

CLK

CLKENA1

1B4

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FUNCTION TABLES SN74ALVCH16269

12-BIT TO24-BIT REGISTERED BUS EXCHANGER

WITH3-STATE OUTPUTS

SCES019N–JULY1995–REVISED JULY2004

OUTPUT ENABLE

INPUTS OUTPUTS

CLK OEA OEB A1B,2B

↑H H Z Z

↑H L Z Active

↑L H Active Z

↑L L Active Active

A-TO-B STORAGE(OEB=L)

INPUTS OUTPUTS

CLKENA1CLKENA2CLK A1B2B

L H↑L L2B0(1)

L H↑H H2B0(1)

L L↑L L L

L L↑H H H

H L↑L1B0(1)L

H L↑H1B0(1)H

H H X X1B0(1)2B0(1)

(1)Output level before the indicated steady-state input conditions were

established

B-TO-A STORAGE(OEA=L)

INPUTS OUTPUT

CLK SEL1B2B A

X H X X A0(1)

X L X X A0(1)

↑H L X L

↑H H X H

↑L X L L

↑L X H H

(1)Output level before the indicated

steady-state input conditions

were established

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1B1

2B1

Pin numbers shown are for the DGG and DL packages.

SN74ALVCH16269

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

SCES019N–JULY 1995–REVISED JULY 2004

LOGIC DIAGRAM (POSITIVE LOGIC)

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ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDITIONS(1)

SN74ALVCH16269 12-BIT TO24-BIT REGISTERED BUS EXCHANGER

WITH3-STATE OUTPUTS

SCES019N–JULY1995–REVISED JULY2004

over operating free-air temperature range(unless otherwise noted)

MIN MAX UNIT

V CC Supply voltage range-0.5 4.6V

Except I/O ports(2)-0.5 4.6

V I Input voltage range V

I/O ports(2)(3)-0.5V CC+0.5

V O Output voltage range(2)(3)-0.5V CC+0.5V

I IK Input clamp current V I<0-50mA

I OK Output clamp current V O<0-50mA

I O Continuous output current±50mA

Continuous current through each V CC or GND±100mA

DGG package81

θJA Package thermal impedance(4)DL package74°C/W

GQL/ZQL package42

T stg Storage temperature range-65150°C (1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratings

only,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

(3)This value is limited to4.6V maximum.

(4)The package thermal impedance is calculated in accordance with JESD51-7.

MIN MAX UNIT

V CC Supply voltage 1.65 3.6V

V CC=1.65V to1.95V0.65×V CC

V IH High-level input voltage V CC=2.3V to2.7V 1.7V

V CC=2.7V to3.6V2

V CC=1.65V to1.95V0.35×V CC

V IL Low-level input voltage V CC=2.3V to2.7V0.7V

V CC=2.7V to3.6V0.8

V I Input voltage0V CC V

V O Output voltage0V CC V

V CC=1.65V-4

V CC=2.3V-12

I OH High-level output current mA

V CC=2.7V-12

V CC=3V-24

V CC=1.65V4

V CC=2.3V12

I OL Low-level output current mA

V CC=2.7V12

V CC=3V24

?t/?v Input transition rise or fall rate10ns/V

T A Operating free-air temperature-4085°C (1)All unused control inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs,literature number SCBA004.

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ELECTRICAL CHARACTERISTICS

SN74ALVCH16269

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

SCES019N–JULY 1995–REVISED JULY 2004

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V CC

MIN TYP (1)

MAX

UNIT

I OH =-100μA 1.65V to 3.6V

V CC -0.2

I OH =-4mA 1.65V 1.2I OH =-6mA

2.3V 2V OH

2.3V 1.7V

I OH =-12mA 2.7V 2.23V 2.4I OH =-24mA 3V 2

I OL =100μA 1.65V to 3.6V

0.2I OL =4mA

1.65V 0.45I OL =6mA

2.3V 0.4V OL

V 2.3V 0.7I OL =12mA 2.7V 0.4I OL =24mA

3V 0.55I I

V I =V CC or GND 3.6V ±5

μA V I =0.58V 1.65V 25V I =1.07V 1.65V -25V I =0.7V

2.3V 45I I(hold)

V I =1.7V 2.3V -45μA

V I =0.8V 3V 75V I =2V 3V -75

V I =0to 3.6V (2)

3.6V ±500I OZ (3)V O =V CC or GND 3.6V ±10μA I CC V I =V CC or GND,I O =0

3.6V 40μA ?I CC One input at V CC -0.6V,Other inputs at V CC or GND 3V to 3.6V 750

μA C i Control inputs V I =V CC or GND 3.3V 3.5pF C io A or B ports

V O =V CC or GND

3.3V

pF (1)All typical values are at V CC =3.3V,T A =25°C.

(2)This is the bus-hold maximum dynamic current.It is the minimum overdrive current required to switch the input from one state to another.

(3)

For I/O ports,the parameter I OZ includes the input leakage current.

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TIMING REQUIREMENTS SWITCHING CHARACTERISTICS OPERATING CHARACTERISTICS

SN74ALVCH16269 12-BIT TO24-BIT REGISTERED BUS EXCHANGER

WITH3-STATE OUTPUTS

SCES019N–JULY1995–REVISED JULY2004

over recommended operating free-air temperature range(unless otherwise noted)(see Figure1)

V CC=2.5V V CC=3.3V

V CC=1.8V V CC=2.7V

±0.2V±0.3V UNIT

MIN MAX MIN MAX MIN MAX MIN MAX

f clock Clock frequency(1)135135135MHz t w Pulse duration,CLK high or low(1) 3.3 3.3 3.3ns

A data before CLK↑(1)22 1.7

B data before CLK↑(1) 2.2 2.1 1.8

t su Setup time SEL before CLK↑(1) 1.6 1.6 1.3ns CLKENA1or CLKENA2before CLK↑(1)1 1.20.9

OE before CLK↑(1) 1.5 1.6 1.3

A data after CLK↑(1)0.70.60.6

B data after CLK↑(1)0.70.60.6

t h Hold time SEL after CLK↑(1) 1.10.70.7ns CLKENA1or CLKENA2after CLK↑(1)10.8 1.1

OE after CLK↑(1)0.80.80.8

(1)This information was not available at the time of publication.

over recommended operating free-air temperature range(unless otherwise noted)(see Figure1)

V CC=2.5V V CC=3.3V

V CC=1.8V V CC=2.7V

FROM TO±0.2V±0.3V PARAMETER UNIT (INPUT)(OUTPUT)

MIN TYP MIN MAX MIN MAX MIN MAX

f max(1)135135135MHz

B(1)18.27.31 6.2 t pd CLK ns

A(1)1 6.4 5.815

B(1)17.9 6.71 6.1 t en CLK ns

A(1)17.6 6.21 5.9

B(1)18.1 6.91 6.1 t dis CLK ns

A(1)17.5 6.81 5.6

(1)This information was not available at the time of publication.

=25°C

V CC=1.8V V CC=2.5V V CC=3.3V PARAMETER TEST CONDITIONS UNIT

TYP TYP TYP

All outputs enabled(1)87120 Power dissipation

C pd C L=50pF,f=10MHz pF

capacitance per exchanger All outputs disabled(1)80.5118

(1)This information was not available at the time of publication.

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PARAMETER MEASUREMENT INFORMATION

V OH V OL

From Output Under Test

LOAD CIRCUIT

Open Output Control (low-level enabling)

Output Waveform 1S1 at V LOAD (see Note B)

Output Waveform 2S1 at GND (see Note B)0 V

0 V

V I 0 V

0 V

V I

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS PULSE DURATION

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES

Timing Input

Data Input

Input

t pd t PLZ /t PZL t PHZ /t PZH

Open V LOAD GND

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .

H.All parameters and waveforms are not applicable to all devices.

0 V

V I

Input

Output

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

V LOAD /2

1.8 V

2.5 V ± 0.2 V

2.7 V 3 V ± 0.3 V

1 k ?500 ?500 ?500 ?

V CC R L 2 × V CC 2 × V CC 6 V 6 V

V LOAD C L 30 pF 30 pF 50 pF 50 pF

0.15 V 0.15 V 0.3 V 0.3 V

V ?V CC V CC 2.7 V 2.7 V

V I V CC /2V CC /21.5 V 1.5 V

V M t r /t f ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns

INPUT SN74ALVCH16269

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

SCES019N–JULY 1995–REVISED JULY 2004

Figure 1.Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)

Lead/Ball Finish MSL Peak Temp (3)74ALVCH16269DGGRE4ACTIVE TSSOP DGG 562000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74ALVCH16269DGGRG4ACTIVE TSSOP DGG 562000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74ALVCH16269DLG4ACTIVE SSOP DL 5620

Green (RoHS &no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 74ALVCH16269DLRG4ACTIVE SSOP DL 561000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74ALVCH16269ZQLR

ACTIVE

BGA MI CROSTA R JUNI OR ZQL

1000Green (RoHS &

no Sb/Br)

SNAGCU

Level-1-260C-UNLIM

SN74ALVCH16269DGGR ACTIVE TSSOP DGG 562000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16269DL ACTIVE SSOP DL 5620

Green (RoHS &no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16269DLR ACTIVE SSOP DL 561000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16269KR

NRND

BGA MI CROSTA R JUNI OR

GQL

1000

TBD

SNPB

Level-1-240C-UNLIM

(1)

The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.

(2)

Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check https://www.wendangku.net/doc/ca6045483.html,/productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt):This component has a RoHS exemption

for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.

Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)

(3)

MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

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27-Sep-2007

TAPE AND REEL BOX

INFORMATION

Device

Package Pins Site

Reel Diameter (mm)Reel Width (mm)A0(mm)B0(mm)K0(mm)

P1(mm)W (mm)Pin1Quadrant 74ALVCH16269ZQLR ZQL 56SITE 3233016 4.87.3 1.45816Q1SN74ALVCH16269DGGR DGG 56SITE 41330248.615.6 1.81224Q1SN74ALVCH16269DLR DL 56SITE 413303211.3518.67 3.11632Q1SN74ALVCH16269KR GQL 56SITE 3233016 4.87.3 1.45816Q1SN74ALVCH16269KR

GQL

SITE 60

330

4.8

7.3

1.5

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4-Oct-2007

Device

Package Pins Site Length (mm)

Width (mm)Height (mm)

74ALVCH16269ZQLR ZQL 56SITE 32346.0346.033.0SN74ALVCH16269DGGR DGG 56SITE 41346.0346.041.0SN74ALVCH16269DLR DL 56SITE 41346.0346.049.0SN74ALVCH16269KR GQL 56SITE 32346.0346.033.0SN74ALVCH16269KR

GQL

SITE 60

342.9

336.6

28.58

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4-Oct-2007

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.

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