CJC5150_Datasheet_V3.0

CHINAIC SEMICONDUCTOR CORP., LTD.
CJC5150
Ultralow-power NTSC/PAL/SECAM Video Decoder
Edition V3.0
RD By tf
Date 2012.01
Description Ultralow-power NTSC/PAL/SECAM Video Decoder
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CJC5150
Contents
CJC5150 ....................................................................................................................................- 1 1. INTRODUCTION ..........................................................................................................- 3 2. FEATUREA....................................................................................................................- 3 3. APPLICATION ..............................................................................................................- 4 4. FUNCTIONAL BLOCK DIAGRAM ............................................................................- 5 5. TERMINAL ASSIGNMENT .........................................................................................- 6 5.1. Terminal Functions .....................................................................................................- 6 6. FUNCTIONAL DESCRIPITON ....................................................................................- 9 6.1. Analog Front End .......................................................................................................- 9 6.2. Output format ..............................................................................................................- 9 6.3. Synchronization Signals ..........................................................................................- 10 6.4. Active Video(AVID) Cropping .................................................................................- 12 6.5. Embedded Syncs .....................................................................................................- 13 6.6. I2C Host Interface ....................................................................................................- 13 6.6.1. I2C Write/Read Operation..................................................................................- 14 6.7. Reset and Power Down ..........................................................................................- 15 6.8. Genlock Control(GLCO) and RTC .........................................................................- 15 6.9. GLCO Interface ........................................................................................................- 15 6.10. RTC Mode ................................................................................................................- 16 7. REGISTER SUMMARY..............................................................................................- 17 8. REGISTER DEFINITIONS .........................................................................................- 18 8.1. Video Input Source Selection #1 Register (0x00) ...............................................- 18 8.2. Analog Channel Controls Register (0x01)............................................................- 19 8.3. Operation Mode Controls Register (0x02) ...........................................................- 19 8.4. Miscellaneous Controls Register (0x03) ...............................................................- 20 8.5. Autoswitch Mask Register (0x04) ..........................................................................- 22 8.6. Color Killer Threshold Control Register (0x06) ....................................................- 23 8.7. Luminance Processing Control #1 Register (0x07) ............................................- 23 8.8. Luminance Processing Control #2 Register (0x08) ............................................- 24 8.9. Brightness Control Register (0x09) .......................................................................- 25 8.10. Color Saturation Control Register (0x0A) ...........................................................- 25 8.11. Hue Control Register (0x0B) .................................................................................- 25 8.12. Contrast Control Register (0x0C) .........................................................................- 25 8.13. Outputs and Data Rates Select Register (0x0D) ...............................................- 26 8.14. Luminance Processing Control #3 Register (0x0E) ..........................................- 27 8.15. Configuration Shared Pins Register (0x0F) ........................................................- 27 8.16. Active Video Cropping Start Pixel MSB Register (0x11) ..................................- 28 8.17. Active Video Cropping Start Pixel LSB Register (0x12) ...................................- 28 8.18. Active Video Cropping Stop Pixel MSB Register (0x13) ..................................- 28 8.19. Active Video Cropping Stop Pixel LSB Register (0x14) ...................................- 29 8.20. Genlock and RTC Register (0x15) .......................................................................- 29 8.21. Horizontal Sync Start Register (0x16) .................................................................- 30 https://www.wendangku.net/doc/cb6722624.html, -11/9/2012 V3.0

CJC5150
8.22. Vertical Blanking Start Register (0x18) ................................................................- 30 8.23. Vertical Blanking Stop Register (0x19) ................................................................- 31 8.24. Chrominance Control #1 Register (0x1A) ...........................................................- 31 8.25. Chrominance Control #2 Register (0x1B) ...........................................................- 32 8.26. Interrupt Reset Register B (0x1C) ........................................................................- 32 8.27. Interrupt Enable Register B (0x1D) ......................................................................- 33 8.28. Interrupt Configuration Register B (0x1E)...........................................................- 34 8.29. Interrupt Status Register B (0x86) ........................................................................- 34 8.30. Interrupt Active Register B (0x87) ........................................................................- 35 8.31. Status Register #1 (0x88) ......................................................................................- 36 8.32. Status Register #2 (0x89) ......................................................................................- 37 8.33. Status Register #3 (0x8A) .....................................................................................- 38 8.34. Status Register #4 (0x8B) .....................................................................................- 38 8.35. Status Register #5 (0x8C) .....................................................................................- 38 8.36. Video Standard Register (0x28) ...........................................................................- 39 8.37. Interrupt Status Register A (0xC0) .......................................................................- 39 8.38. Interrupt Enable Register A (0xC1) ......................................................................- 40 8.39. Interrupt Configuration Register A (0xC2) ...........................................................- 41 8.40. Line Number Interrupt Register (0xCA)...............................................................- 41 8.41. Cb Gain Factor Register (0x2C) ...........................................................................- 42 8.42. Cr Gain Factor Register (0x2D) ............................................................................- 42 8.43. 656 Revision Select Register (0x30) ...................................................................- 42 9. ELECTRICAL SPECIFICATIONS .............................................................................- 43 9.1. Absolute Maximum Rating ......................................................................................- 43 9.2. Recommended Operating Conditions ...................................................................- 43 9.3. Electrical Characteristics .........................................................................................- 43 9.4. Clocks, Video Data, Sync Timing...........................................................................- 44 10. EXAMPLE REGISTER SETTINGS............................................................................- 44 10.1. Example 1 ................................................................................................................- 44 10.1.1. Assumptions ...................................................................................................- 44 10.1.2. Recommended Settings ...............................................................................- 44 10.2. Example 2 ................................................................................................................- 45 10.2.1. Assumptions ...................................................................................................- 45 10.2.2. Recommended Settings ...............................................................................- 45 10.3. Interrupt Register Description ...............................................................................- 45 11. APPLICATION INFORMATION ...............................................................................- 46 12. PACKAGING ...............................................................................................................- 47 -
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1. INTRODUCTION
The CJC5150 device is an ultra-low power PAL/NTSC/SECAM video decoder. Available in a popular space saving TQFP32 package. The CJC5150 decoder converter PAL/NTSC/SECAM video signals to 8-bit CCIR 656 format. Discrete sync are also available.
The CJC5150 decoder has an ultra-low power comsumption, around 110mW of power in typical operation and consumes less than 1mW in power down mode, which increasing battery life in hand-held application. The decoder uses just one crystal of 14.31818MHz for all supported standards. The CJC5150 decoder can be programmed using an I2C serial interface. The decoder uses a 1.8V power supply for its digital and analog circuits and 3.3V/1.8V power supply for its I/O.
The CJC5150 decoder converts base band analog video into digital YcbCr 4:2:2 component video. CVBS and S-Video inputs are supported. The CJC5150 decoder includes one 10-bit ADC with 2x sampling rate. Sampling is CCIR 601(27.0MHz, generated from internal PLL). The output format can be 8-bit 4:2:2 or 8-bit CCIR 656 with embedded syncronization.
Video characteristics including hue, contrast, brightness, saturation, and sharpness may be programmed using the industry standard I2C serial interface. The CJC5150 decoder generates synchronization, blanking, lcok, and clock signals in addition to digtial video outputs.
2. FEATUREA
● ● ● ● ● ● ●
Accepts NTSC(M, 4.43), PAL(B, D, G, H, I, M, N), and SECAM Video Data. Two Composite Inputs or One S-video Input. Supports ITU-R BT.601 Standard Sampling. High-speed 10-bit Analog-to-Digtial converter. Power-down mode : < 1mW. Ultra-low power consumption: around 110mW typcial. Standard Programmable Video Output Formats. － ITU-R BT.656, 8-Bit 4:2:2 With Embedded Syncs.
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CJC5150 － 8-Bit 4:2:2 With Discrete Syncs.
● ● ● ● ● ●
Brightness, Contrast, Hue, Saturation, and Sharpness control through I2C. Single 14.31818MHz crystal for all standards. Special architecture for locking to weak, noisy, or unstable signals. Subcarrier Genlock output for synchronizing color subcarrier of extern encoder. Power-on reset. Package: TQFP32.
3. APPLICATION
Following is a partical list of suggested application:
● ● ● ● ● ● ● ● ●
Digital TV PDA Notebook PC Cellular phone Handheld games Security system Video capture Personal media player Video recorder/players
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4. FUNCTIONAL BLOCK DIAGRAM
4.1 Functional Block Diagram
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5. TERMINAL ASSIGNMENT
5.1. Terminal Functions
PIN 1 AIP1A NAME I/O I DESCRIPTION Analog input. Connect to the video analog input via 0.1uF capacitor. The maximum input range is 0-1.2Vpp, and may require an divided network by resistor to attenuate the input amplitude for the desire level. If not used, connect to AGND via 0.1uF capacitor. Analog input. Connect to the video analog input via 0.1uF capacitor. The maximum input range is 0-1.2Vpp, and may require an divided network by resistor to attenuate the input amplitude for the desire level. If not used, connect to AGND via 0.1uF capacitor. PLL ground. Connect to analog ground.
2
AIP1B
I
3
PLL_AGND
I
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CJC5150 4 5 6 PLL_AVDD XTAL1/OSC XTAL2 I I O PLL power suply. Connect to 1.8V analog power supply. External clock reference. XTAL1/OSC can be connected to an oscillator or to one terminal of a crystal oscillator. XTAL2 may be connected to the other terminal of the crystal or not connected at all. One signal 14.31818 MHz or other common used crystal is needed for CCIR 601 sampling, for all supported standards. Substrate. Connect to analog ground. Active-low reset. RESETB can be used only when PDN=1. When RESETB is pulled low, it resets all the registers. System clock at either 1x or 2x the frequency of the pixel clock. Digital I/O supply. Connect to 3.3V. Also attach 1.8V if slave device interface level is 1.8V and can saving power consumption. I2CSEL: Determines address for I2C (sampled during reset). A pullup or pulldown register is needed (>1 k?) to program the terminal to the desired address. 1 = Address is 0xBA; 0 = Address is 0xB8; YOUT7: Most-significant bit (MSB) of output decoded ITU-R BT.656 output/YCbCr 4:2:2 output. Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync. Digital ground. Digital core supply. Connect to 1.8V digital supply. I2C serial clock(open drain). I2C serial clock(open drain). FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd field. GLCO: This serial output carries color PLL information. A slave device can decode the information to allow chroma frequency control from the CJC5150 decoder. Data is transmitted at the SCLK rate in Genlock mode. In RTC mode, SCLK/4 is used. VSYNC: Vertical synchronization signal PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator: 1 = Noninverted line 0 = Inverted line
7 8 9 10
AGND RESTEB PCLK/SCLK IO_DVDD
I I O I
11
YOUT7/I2CSEL
I/O
12-18 19 20 21 22 23
YOUT[6:0] DGND DVDD SCL SDA FID/GLCO
I/O I I I/O I/O O
24
VSYNC/PALI
O
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CJC5150 25 26 HSYNC AVID O O Horizontal synchronization. Active video indicator. This signal is high during the horizontal active time of the video output. AVID toggling during vertical blanking intervals is controlled by bit 2 of the active video cropping start pixel LSB register at address 12h. INTREQ: Interrupt request output. GPCL/VBLK: General-purpose control logic. This terminal has two functions: · GPCL: General-purpose output. In this mode the state of GPCL is directly programmed. · VBLK: Vertical blank output. In this mode the GPCL terminal indicates the vertical blanking interval of the output video. The beginning and end times of this signal are programmable via I2C. Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value of the registers. A/D reference supply. Connect to analog ground through a 1uF capacitor. A/D reference ground. Connect to analog ground through a 1uF capacitor. Also, it is recommended to connect directly to REFP through a 1uF capacitor. Analog ground. Analog supply. Connect to 1.8V analog supply.
27
INTREQ/GPCL/VBLK
I/O
28 29 30
PDN REFP REFM
I I I
31 32
CH_AGND CH_AVDD
I I
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6. FUNCTIONAL DESCRIPITON 6.1. Analog Front End
The CJC5150 decoder has an analog input channel that accepts two video inputs that are ac-coupled. The decoder supports a maximum input voltage of 1.2V; therefore, if the video input voltage is very large, then may be require an attenuator to reduce the input amplitude to the desire level. The maximum parallel termination before the input to the device is 75?. There are have two analog input ports can be connected as follows:
● ●
Two selectable composite video inputs One S-video input
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The programmable gain amplifier(PGA) and the automatic gain control(AGC) circuit work together to make sure that the input signal is amplified sufficiently to ensure the proper input range for the ADC.
6.2. Output format
The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface standard. Table 6-1. Summary of line Frequencies, Data Rates, and Pixel Counts Standards Horizontal Line Rate(KHz) 15.73426 15.625 15.73426 15.625 15.625 Pixels Per Line Active Pixels Per Line 720 720 720 720 720 SCLK Frequency( MHz) 27.00 27.00 27.00 27.00 27.00
NTSC(M, 4.43), ITU-R BT.601 PAL(B, D, G, H, I),ITU-R BT.601 PAL(M), ITU-R BT.601 PAL(N), ITU-R BT.601 SECAM, ITU-R BT.601
858 864 858 864 864
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6.3. Synchronization Signals
External(discrete) syncs are provided via the following signals:
● ● ● ● ● ●
VSYNC(vertical sync) FID/VLK(field indicator or vertical lock indicator) GPCL/VBLK(general-purpose I/O or vertical blanking indicator) PALI/HLK(PAL switch indicator or horizontal lock indicator) HSYNC(horizontal sync) AVID(active video indicator)
VSYNC, FID, PALI, and VBLK are software set and programmable to the SCLK pixel count. This allows any possible alignment to the internal pixel count and line count. The default settings for a 525-/625-line video output are given as an example.
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Figure 6-1. 8-Bit 4:2:2, Timing With 2x Pixel Clock (SCLK) Reference
ITU-R BT.656 Timing
Figure 6-2. Horizontal Synchronization Signals
Table 6-2. Clock Delays (SCLKs) STANDARD NTSC PAL SECAM Nhbhs 16 20 20 Nhb 272 284 280
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6.4. Active Video(AVID) Cropping
AVID cropping provides a means to decrease bandwidth of the video output. This is accomplished by horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. The horizontal AVID cropping is controlled using registers 11h and 12h for start pixels MSB and LSB,respectively.
Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID cropping is controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and 19h. Figure 6-3 shows an AVID application.
Figure 6-3. AVID Application
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6.5. Embedded Syncs
Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V change on EAV. Table 6-1 gives the format of the SAV and EAV codes. H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard. See ITU-R BT.656 for more information on embedded syncs. The P bits are protection bits: P3 = V xor H P2 = F xor H P1 = F xor V P0 = F xor V xor H Table 6-3. EAV and SAV Sequence 8-BIT DATA D7(MSB) Preamble Preamble Preamble Status word 1 0 0 1 D6 1 0 0 F D5 1 0 0 V D4 1 0 0 H D3 1 0 0 P3 D2 1 0 0 P2 D1 1 0 0 P1 D0 1 0 0 P0
6.6. I2C Host Interface
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. The address of I2C is selected by YOUT7, and YOUT7 must connect a resistor to ground or IO_DVDD. Table 6-4. I2C Write/Read Address Selection I2CSEL(YOUT7) 0 1 Write Address B8h BAh Read Address B9h BBh
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6.6.1. I2C Write/Read Operation
The Write and Read of CJC5150 I2C according to industrial standard, can support basic writing and reading operation perfectly. A> Random Write Mode
B> Continue Write Mode
C> Random Read Mode
D> Continue Read Mode
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CJC5150 E> Current Read Mode
6.7. Reset and Power Down
Terminals 9 (RESETB) and 35 (PDN) work together to put the CJC5150 decoder into one of the two modes. Table 6-5 shows the configuration. Table 6-5. Reset and Power-Down Modes PDN 0 0 1 1 RESETB 0 1 0 1 CONFIGURATION Reserved (unknown state) Powers down the docoder Resets the decoder Normal operation
6.8. Genlock Control(GLCO) and RTC
A Genlock control function is provided to support a standard video encoder to synchronize its internal color oscillator for properly reproduced color with unstable timebase sources such as VCRs. The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the subcarrier phase reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit binary number. The frequency of the DTO can be calculated from the following equation: Fdto = (Fctrl/223) × Fsclk where Fdto is the frequency of the DTO, Fctrl is the 23-bit DTO frequency control, and Fsclk is the frequency of the SCLK.
6.9. GLCO Interface
A write of 1 to bit 4 of the chrominance control register at I2C subaddress 1Ah causes the subcarrier DTO phase reset bit to be sent on the next scan line on GLCO. The active-low reset bit occurs seven SCLKs after the transmission of the last bit of DCO frequency control. Upon the transmission of the reset bit, the phase of the CJC5150 internal subcarrier DCO is reset to zero.
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CJC5150 A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to synchronize its internal color phase DCO to achieve clean line and color lock. Figure 6-4 shows the timing diagram of the GLCO mode.
Figure 6-4. GLCO Timing
6.10. RTC Mode
Figure 6-5 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower than the GLCO clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the last bit of PLL frequency control.
Figure 6-5. RTC Timing
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7. REGISTER SUMMARY
REGISTER Video input source selection #1 Analog channel controls Operation mode controls Miscellaneous controls Autoswitch mask Reserved Color killer threshold control Luminance processing control #1 Luminance processing control #2 Brightness control Color saturation control Hue control Contrast control Outputs and data rates select Luminance processing control #3 Configuration shared pins Reserved Active video cropping start pixel MSB Active video cropping start pixel LSB Active video cropping stop pixel MSB Active video cropping stop pixel LSB Genlock and RTC Horizontal sync start Reserved Vertical blanking start Vertical blanking stop Chrominance control #1 Chrominance control #2 Interrupt reset register B Interrupt enable register B Interrupt configuration register B Reserved Video standard Reserved Cb gain factor Cr gain factor Reserved 656 revision select Reserved
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ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh – 27h 28h 29h – 2Bh 2Ch 2Dh 2Eh – 2Fh 30h 31h – 7Fh
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DEFAULT 00h 15h 00h 01h DCh 00h 10h 60h 00h 80h 80h 00h 80h 47h 00h 08h 00h 00h 00h 00h 01h 80h 00h 00h 0Ch 14h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R 00h R/W
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CJC5150 MSB of device ID LSB of device ID ROM major version ROM minor version Vertical line count MSB Vertical line count LSB Interrupt status register B Interrupt active register B Status register #1 Status register #2 Status register #3 Status register #4 Status register #5 Reserved Interrupt status register A Interrupt enable register A Interrupt configuration register A Reserved 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh – BFh C0h C1h C2h C3h – FFh 00h 00h 04h R/W R/W R/W 51h 50h 04h 00h R R R R R R R R R R R R R
8. REGISTER DEFINITIONS 8.1. Video Input Source Selection #1 Register (0x00)
Address Default 7 00h 00h 6 Reserved 5 4 3 Black output 2 Reserved 1 Channel 1 source selection 0 s-video selection
Channel 1 source selection 0 = AIP1A selected(default) 1 = AIP1B selected Table 8-1. Analog Channel and Video Mode Selection Inputs selection CVBS S-Video AIP1A(default) AIP1B AIP1A(luma), AIP1B(chroma) Address (00h) BIT1 0 1 x BIT0 0 0 1
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CJC5150 Black output 0 = Normal operation(default) 1 = Force black screen output(outputs synchronized)
8.2. Analog Channel Controls Register (0x01)
Address Default 7 01h 15h 6 5 4 3 2 1 0 Automatic offset control Automatic offset control 00 = Disabled 01 = Automatic offset enabled(default) 10 = Reserved 11 = Offset level frozen to the previously set value Automatic gain control(AGC) 00 = Disabled(fixed gain value) 01 = AGC enabled(default) 10 = Reserved 11 = AGC frozen to the previously set value
Automatic gain control
8.3. Operation Mode Controls Register (0x02)
Address Default 7 02h 00h 6 Color burst reference enable 5 4 3 White peak disable 2 Color subcarrier PLL frozen 1 Luma peak disable 0 Power-down mode
Reserved
TV/VCR mode
Color burst reference enable 0 = Color burst reference for AGC disabled(default) 1 = Color burst reference for AGC enabled TV/VCR mode 00 = Automatic mode determined by the internal detection 01 = Reserved 10 = VCR(nonstandard video) mode 11 = TV(standard video) mode
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