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LTC6802-2

LTC6802-2

1

68022f

TYPICAL APPLICATION

DESCRIPTION

Battery Stack Monitor

The L TC ?6802-2 is a complete battery monitoring IC that includes a 12-bit ADC, a precision voltage reference, a high voltage input multiplexer and a serial interface. Each L TC6802-2 can measure 12 series connected battery cells, with a total input voltage up to 60V . The voltage on all 12 input channels can be measured within 13ms.

Many L TC6802-2 devices can be stacked to measure the voltage of each cell in a long battery string. Each L TC6802-2 has an individually addressable serial interface, allowing up to 16 L TC6802-2 devices to interface to one control processor and operate simultaneously.

To minimize power , the L TC6802-2 offers a measure mode to monitor each cell for overvoltage and undervoltage conditions. A standby mode is also provided to reduce supply current to 50μA.

Each cell input has an associated MOSFET switch that can discharge any overcharged cell.

The related L TC6802-1 offers a serial interface that allows the serial ports of multiple L TC6802-1 devices to be daisy chained without opto-couplers or isolators.

L , L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

FEATURES

APPLICATIONS

n

Measures up to 12 Li-Ion Cells in Series (60V Max)n Stackable Architecture Enables Monitoring High Voltage Battery Stacks

n Individually Addressable with 4-Bit Address n 0.25% Maximum Total Measurement Error n 13ms to Measure All Cells in a System n Cell Balancing:

On-Chip Passive Cell Balancing Switches Provision for Off-Chip Passive Balancing n T wo Thermistor Inputs Plus On-board Temperature Sensor

n 1MHz Serial Interface with Packet Error Checking n High EMI Immunity

n Delta Sigma Converter With Built In Noise Filter n Open Wire Connection Fault Detection n Low Power Modes n 44-Lead SSOP Package

n

Electric and Hybrid Electric Vehicles n High Power Portable Equipment n Backup Battery Systems

n

High Voltage Data Acquisition Systems

LTC6802-2

LTC6802-2

12-CELL BATTERY STRING

100k NTC

M E A S U R E M E N T E R R O R (%)

TEMPERATURE (°C)

125

–50

0.30–0.30

–25

025*******–0.20–0.25–0.100.1000.20–0.15–0.050.150.050.2568022 TA01b

Measurement Error Over Extended Temperature

2

68022f

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

Total Supply Voltage (V + to V –) .................................60V Input Voltage (Relative to V –)

C1 ............................................................–0.3V to 9V C12 ..........................................V + – 0.3V to V + + 0.3V Cn (Note 5) .........................–0.3V to min (9 ? n, 60V)Sn (Note 5) .........................–0.3V to min (9 ? n, 60V)CSBO, SCKO, SDOI ..................V + – 0.6V to V + + 0.3V All other pins ...........................................–0.3V to 7V Voltage Between Inputs

Cn to Cn-1 ...............................................–0.3V to 9V Sn to Cn-1 ...............................................–0.3V to 9V Operating Temperature Range..................–40°C to 85°C Speci? ed Temperature Range ..................–40°C to 85°C Junction Temperature ...........................................150°C Storage Temperature Range ...................–65°C to 150°C *n = 1 to 12

(Note 1)

LTC6802-2

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L TC6802IG-2#PBF

L TC6802IG-2#TRPBF

L TC6802G-2

44-Lead Plastic SSOP

–40°C to 85°C

Consult L TC Marketing for parts speci? ed with wider operating temperature ranges.Consult L TC Marketing for information on non-standard lead based ? nish parts.

For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel speci? cations, go to: http://www.linear .com/tapeandreel/

ELECTRICAL CHARACTERISTICS

The

l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at T A = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Speci? cations

V ACC Measurement Resolution Quantization of the ADC l 1.5mV/Bit ADC Offset Voltage(Note 2)l–0.50.5mV

ADC Gain Error(Note 2)

l –0.12

–0.22

0.12

0.22

%

%

V ERR Total Measurement Error(Note 4)

V CELL = 0V

V CELL = 2.3V V CELL = 2.3V V CELL = 3.6V V CELL = 3.6V V CELL = 4.2V V CELL = 4.2V V CELL = 4.6V V TEMP = 2.3V V TEMP = 3.6V V TEMP = 4.2V l

l

l

l

l

l

–2.8

–5.1

–4.3

–7.9

–5

–9.2

–5.1

–7.9

–9.2

0.8

±8

2.8

5.1

4.3

7.9

5

9.2

5.1

7.9

9.2

mV

mV

mV

mV

mV

mV

mV

mV

mV

mV

mV

V CELL Cell Voltage Range Full Scale Voltage Range5V

V CM Common Mode Voltage Range Measured Relative to V–Range of Inputs CN for <0.25% Gain Error, N = 3 to 11

Range of Inputs C3 for <1% Gain Error

Range of Inputs CN for <0.25% Gain Error, N = 1 or 2

l

l

l

3.7

1.8

5 ? N

15

5 ? N

V

V

V

Overvoltage (OV) Detection Level Programmed for 4.2V l 4.182 4.200 4.218V Undervoltage (UV) Detection Level Programmed for 2.3V l 2.290 2.300 2.310V Die Temperature Measurement Error Error in Measurement at 125°C3°C

V REF Reference Pin Voltage R LOAD = 100k to V–

l 3.020

3.015

3.065

3.065

3.110

3.115

V

V

Reference Voltage Temperature Coef? cient8ppm/°C Reference Voltage Thermal Hysteresis25°C to 85°C and 25°C to –40°C100ppm Reference Voltage Long Term Drift60ppm/√khr

V REG Regulator Pin Voltage10 < V+ < 50, No Load

I LOAD = 4mA l

l

4.5

4.1

5.0

4.8

5.5V

V

Regulator Pin Short Circuit Current Limit l58mA

V S Supply Voltage, V+ Relative to V–V ERR Speci? cations Met

Timing Speci? cations Met l

l

10

4

50

50

V

V

I B Input Bias Current In/Out of Pins C1 Thru C12

When Measuring Cells

When Not Measuring Cells l–10

1

10μA

nA

I S Supply Current, Active Current Into the V+ Pin when Measuring Voltages

with the ADC l 0.8 1.1

1.2

mA

mA

I M Supply Current, Monitor Mode Average Current Into the V+ Pin While Monitoring

for UV and OV Conditions

Continuous Monitoring Monitor Every 130ms Monitor Every 500ms Monitor Every 2s 800

250

175

130

μA

μA

μA

μA

I QS Supply Current, Idle Current into the V+ Pin When Idle

All Serial Port Pins at Logic ‘1’l 305070

75

μA

μA

Discharge Switch On-Resistance V CELL > 3V (Note 3)l1020Ω

368022f

4

68022f

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The ADC speci? cations are guaranteed by the Total Measurement Error (V ERR ) speci? cation.

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

Temperature Range

l

–40

85

°C Thermal Shutdown Temperature 145°C Thermal Shutdown Hysteresis

5

°C

Timing Speci? cations t CYCLE

Measurement Cycle Time

Time Required to Measure 11 or 12 Cells

Time Required to Measure Up to 10 Cells Time Required to Measure 1 Cell

l l 13111.2

1613.5

ms ms ms t 1SDI Valid to SCKI Rising Setup l 10ns t 2SDI Valid to SCKI Rising Hold l 250ns t 3SCKI Low l 400ns t 4SCKI High l 400ns t 5CSBI Pulse Width l 400ns t 6SCKI Rising to CSBI Rising l 100ns t 7CSBI Falling to SCKI Rising l 100

ns

t 8

SCKI Falling to SDO Valid l 250ns Clock Frequency

l 1

MHz Watchdog Timer Time Out Period

l

1 2.5

s Digital I/O Speci? cations V IH Digital Voltage Input High l 2

V V IL Digital Voltage Input Low l 0.8V V OL

Digital Voltage Output Low

Sinking 500μA

l

0.3V

ELECTRICAL CHARACTERISTICS The l denotes the speci? cations which apply over the full operating

temperature range, otherwise speci? cations are at T A = 25°C. V + = 43.2V , V –

= 0V , unless otherwise noted.

Note 3: Due to the contact resistance of the production tester , this

speci? cation is tested to relaxed limits. The 20Ω limit is guaranteed by design.

Note 4: V CELL refers to the voltage applied across the following pin combinations: Cn to Cn-1 for n = 2 to 12, C1 to V –. V TEMP refers to the voltage applied from V TEMP1 or V TEMP2 to V –

Note 5: These absolute maximum ratings apply provided that the voltage between inputs do not exceed their absolute maximum ratings.

5

68022f

TYPICAL PERFORMANCE CHARACTERISTICS

Cell Measurement Total Unadjusted Error vs Input Resistance

Cell Measurement Total Unadjusted Error

CELL VOL TAGE (V)

T O T A L U N A D J U S T E D E R R O R (m V )

10–8840–462–2–6–10

2.5 4.51.5

3.568022 G09

5.0

2.0 4.01.0

3.0

LTC6802-2

0.5CELL VOL TAGE (V)

T O T A L U N A D J U S T E D E R R O R (m V )

100–20–40–60–10–30–50–70–80

2.5 4.51.5

3.568022 G10

5.0

2.0 4.01.0

3.00.5

LTC6802-2

Measurement Gain Error Hysteresis

Measurement Gain Error Hysteresis

CHANGE IN GAIN ERROR (ppm)

–250N U M B E R O F U N I T S

25

2015

10

5

–50150–15050

LTC6802-2

68022 G20

200

–100100–2000CHANGE IN GAIN ERROR (ppm)

–250N U M B E R O F U N I T S

2016128418141062

–50150–15050

LTC6802-2

68022 G21

200

–100100–2000ADC Normal Mode Rejection vs Frequency

Cell Measurement Common Mode Rejection

0–10–30–50–20–40–60–70

LTC6802-2

FREQUENCY (Hz)

R E J E C T I O N (d b )

68022 G14

1010k 100k

1k 100

–10–30–50–20–40–60–70

FREQUENCY (Hz)

R E J E C T I O N (d b )

68022 G15

10

10k

LTC6802-2

10M

1M

100k 1k 100

V CM(IN) = 5V P-P 72dB REJECTION CORRESPONDS TO

LESS THAN 1 BIT AT ADC OUTPUT ADC INL

ADC DNL

0550

LTC6802-2

00

LTC6802-2

550

5

3

08

246064

LTC6802-2

280

5

3

Cell Input Bias Current in Standby

TEMPERATURE (°C)

–40C P I N B I A S C U R R E N T (n A )

50403020

10–10

20–20

400

8010060

LTC6802-2

68022 G03

120

6

68022f

TYPICAL PERFORMANCE CHARACTERISTICS

TEMPERATURE (°C)

–40C P I N B I A S C U R R E N T (μA )

2.702.652.602.552.502.35

2.402.4520–20

400

801006068022 G04

120

LTC6802-2

SUPPL Y VOL TAGE (V)

0S T A N D B Y S U P P L Y C U R R E N T (μA )

6050

40

3020100

204010

305068022 G01

60

LTC6802-2

Cell Input Bias Current During Conversion

Supply Current vs Supply Voltage Standby

Supply Current vs Supply Voltage in CDC = 2

SUPPL Y VOL TAGE (V)

0S U P P L Y C U R R E N T (m A )

0.900.850.800.750.700.650.60

204010

3050

LTC6802-2

68022 G02

60

Internal Die Temperature Measurement vs Ambient Temperature

External Temperature

Measurement Total Unadjusted Error vs Input

5–4420–231–1–3–5AMBIENT TEMPERATURE (°C)

–50

D I F F

E R E N C E B E T W E E N I N T E R N A L D I E T E M P E R A T U R E M E A S U R E M E N T A N D A M B I E N T T E M P E R A T U R E (°C )

500100

LTC6802-2

68022 G12125

25–2575TEMPERATURE INPUT VOL TAGE (V)

T O T A L U N A D J U S T E D E R R O R (m V )

10–150–55–10–20

2.5 4.51.5

3.568022 G13

5.02.0 4.01.0 3.0

LTC6802-2

0.5V REF Load Regulation

V REF Line Regulation

SOURCING CURRENT (μA)

V R E F (V )

3.09

3.08

3.07

3.06

3.04

3.05

10100

LTC6802-2

68022 G07

1000

SUPPL Y VOL TAGE (V)

0V R E F (V )

3.0743.0723.070

3.0683.0663.064

3.062

3.060

204010

3050

LTC6802-2

68022 G08

60

V REG Load Regulation

SUPPL Y CURRENT (mA)

0V R E G (V )

5.45.25.04.84.64.44.0

4.22

4135

LTC6802-2

68022 G16

10

6789V REF Output Voltage vs Temperature

TEMPERATURE (°C)

–50V R E F (V )

3.0703.0683.0643.0603.0663.0623.058

3.056

50

0100

LTC6802-2

68022 G22

125

25–2575

7

68022f

TYPICAL PERFORMANCE CHARACTERISTICS

V REG Line Regulation

Die Temperature Increase vs Discharge Current in Internal FET

Cell Conversion Time

SUPPL Y VOL TAGE (V)

5

V R E G (V )

5.5

5.0

4.5

4.0

3.0

3.5

254515

3555

68022 G17

LTC6802-2

DISCHARGE CURRENT PER CELL (mA)

I N C R E A S E I N D I E T E M P E R A T U R E (°C )

505453525154030201004080206068022 G18

307010

LTC6802-2

50TEMPERATURE (°C)

–40C O N V E R S I O N T I M E (m s )13.2013.1513.1013.0513.0012.80

12.8512.9012.9520–20

400

80

LTC6802-2

1006068022 G19

120

Internal Discharge Resistance vs Cell Voltage

CELL VOL TAGE (V)

D I S C H A R G

E R E S I S T A N C E (Ω)

50545352515403020100 2.5 4.51.5 3.568022 G11

5.0

2.0 4.01.0

3.0

LTC6802-2

0.5

PIN FUNCTIONS

V+ (Pin 1): Tie pin 1 to the most positive potential in the battery stack. V+ must be approximately the same potential as C12.

C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24): C1 through C12 are the inputs for monitoring battery cell voltages. Up to 12 cells can be monitored. The lowest potential is tied to the V– pin. The next lowest potential is tied to C1 and so forth. See the ? gures in the Applications Informa-tion section for more details on connecting batteries to the L TC6802-2.

S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25): S1 though S12 pins are used to balance battery cells. If one cell in a series becomes over charged, an S output can be used to discharge the cell. Each S output is an internal N-channel MOSFET for discharging. See the Block D iagram. The NMOS has a maximum on resistance of 20Ω. An external resistor should be connected in series with the NMOS to dissipate heat outside of the L TC6802-2 package. When using the internal MOSFETs to discharge cells, the die temperature should be monitored. See Power Dissipation and Thermal Shutdown in the Applications Information section.

The S pins also feature an internal 10k pull-up resistor. This allows the S pins to be used to drive the gates of external P-channel MOSFETs for higher discharge capability.

V– (Pin 26): Connect V– to the most negative potential in the series of cells.

NC (Pin 27): Pin 27 is internally connected to V– through 10Ω. Pin 27 can be left unconnected or connect pin 27 to pin 26 on the PCB.

V TEMP1, V TEMP2 (Pins 28, 29): Temperature Sensor Inputs. The ADC will measure the voltage on V TEMPx with respect to V– and store the result in the TMP register. The ADC measurements are relative to the V REF pin voltage. Therefore a simple thermistor and resistor combination connected to the V REF pin can be used to monitor temperature. The V TEMP inputs can also be general purpose ADC inputs.V REF (Pin 30): 3.075V Voltage Reference Output. This pin should be bypassed with a 1μF capacitor. The V REF pin can drive a 100k resistive load connected to V–. Larger loads should be buffered with an L T6003 op amp, or similar device.

V REG (Pin 31): Linear Voltage Regulator Output. This pin should be bypassed with a 1μF capacitor. The V REG is capable of sourcing up to 4mA to an external load. The V REG pin does not sink current.

TOS (Pin 32): Top of Stack Input. The TOS pin can be tied to V REG or V– for the L TC6802-2. The state of the TOS pin alters the operation of the SDO pin in the toggle polling mode. See the Serial Port description.

MMB (Pin 33): Monitor Mode Input (Active Low). When MMB is low (same potential as V–), the L TC6802-2 goes into monitor mode. See Modes of Operation in the Ap-plications Information section.

WDTB (Pin 34): Watchdog Timer Output (Active Low). If there is no activity on the SCKI pin for 2.5 seconds, the WDTB output is asserted. The WDTB pin is an open drain NMOS output. When asserted it pulls the output down to V– and resets the con? guration register to its default state. The watchdog timer function can be disabled by setting WDTEN = 0 in the con? guration register. See Watchdog Timer Circuit in the Applications Information section. GPIO1, GPIO2 (Pins 35, 36): General Purpose Input/Out-put. The operation of these pins depends on the state of the MMB pin.

When MMB is high, the pins behave as traditional GPIOs. By writing a “0” to a GPIO con? guration register bit, the open drain output is activated and the pin is pulled to V–. By writing a logic “1” to the con? guration register bit, the corresponding GPIO pin is high impedance. An external resistor is needed to pull the pin up to V REG.

By reading the con?guration register locations GPIO1 and GPIO2, the state of the pins can be determined. For example, if a “0” is written to register bit GPIO1, a “0” is always read back because the output NMOSFET pulls pin 38 to V–. If a “1” is written to register bit GPIO1, the pin

868022f

PIN FUNCTIONS

becomes high impedance. Either a “1” or a “0” is read back, depending on the voltage present at pin 38. The GPIOs makes it possible to turn on/off circuitry around the L TC6802-2, or read logic values from a circuit around the L TC6802-2.

When the MMB pin is low, the GPIO pins and the WDTB pin are treated as inputs that set the number of cells to be monitored. See Monitor Mode in the Applications Information section.

A0, A1, A2, A3 (Pins 37, 38, 39, 40): Address Inputs. These pins are tied to V REG or V–. The state of the address pins (V REG = 1, V– = 0) determines the L TC6802-2 address. See L TC6802-2 Address Commands in the Serial Port subsection of the Applications Information section.SCKI (Pin 41): Serial Clock Input. The SCKI pin interfaces to any logic gate (TTL levels). See Serial Port in the Ap-plications Information section.

SDI (Pin 42): Serial Data Input. The SDI pin interfaces to any logic gate (TTL levels). See Serial Port in the Applica-tions Information section.

SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS open drain output. See Serial Port in the Applications Information section.

CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI pin interfaces to any logic gate (TTL levels). See Serial Port in the Applications Information section.

BLOCK DIAGRAM

LTC6802-2

968022f

10

68022f

TIMING DIAGRAM

LTC6802-2

PREVIOUS COMMAND

CURRENT COMMAND

SCKI

SDI CSBI

SDO

68022TD

OPERATION

THEORY OF OPERATION

The L TC6802-2 is a data acquisition IC capable of mea-suring the voltage of 12 series connected battery cells. An input multiplexer connects the batteries to a 12-bit delta-sigma analog to digital converter (ADC). An internal 5ppm voltage reference combined with the ADC give the L TC6802-2 its outstanding measurement accuracy. The inherent bene? ts of the delta-sigma ADC vs other types of ADCs (e.g. successive approximation) are explained in Advantages of Delta-Sigma ADCs in the Applications Information section.

Communication between the L TC6802-2 and a host pro-cessor is handled by a SPI compatible serial interface. Multiple L TC6802-2s can be connected to a single serial interface. This is shown in Figure 1. The L TC6802-2s are isolated from one another using digital isolators. A unique addressing scheme allows all L TC6802-2s to connect to the same serial port of the host processor . Further explanation of the L TC6802-2 can be found in the Serial Port section of the data sheet.

The L TC6802-2 also contains circuitry to balance cell volt-ages. Internal MOSFETs can be used to discharge cells. These internal MOSFETs can also be used to control external balancing circuits. Figure 1 illustrates cell balancing by

internal discharge. Figure 4 shows the S pin controlling an external balancing circuit. It is important to note that the L TC6802-2 makes no decisions about turning on/off the internal MOSFETs. This is completely controlled by the host processor . The host processor writes values to a con? guration register inside the L TC6802-2 to control the switches. The watchdog timer on the L TC6802-2 can be used to turn off the discharge switches if communication with the host processor is interrupted.OPEN CONNECTION DETECTION

The open connection detection algorithm assures that an open circuit is not misinterpreted as a valid cell reading.In the absence of external noise ? ltering, the input resis-tance of the ADC will cause open wires to produce a near zero reading. Internal current sources can be used to determine if the wire is truly open. For example, an open on input C3 will result in a near zero reading for both cells connected to C3. For illustration these cells are labeled B3 and B4 in Figure 2. If a near zero reading is encountered for B3 and B4, the MPU can command the L TC6802-2 to place 100μA current sources from the ADC inputs to V –. If input C3 is open, the new reading will show B3 to be zero and B4 to be approximately B3 + B4 + 0.5V .

Timing Diagram of the Serial Interface

OPERATION

LTC6802-2

Figure 1. 96-Cell Battery Stack, Isolated Interface. In this Diagram the Battery Negative is Isolated from

Module Ground. Opto Couplers or Digital Isolators Allow Each IC to be Addressed Individually

1168022f

12

68022f

Figure 2. Open Connection

Some applications may include external noise ? ltering to improve the quality of the ADC readings. When an RC net-work is used to ? lter noise, an open wire may not produce a zero reading because the ADC input resistance is too large to discharge the capacitors on the input pin.Consider the example in Figure 3 where input C3 is open. After several cycles of measuring battery cells B3 and B4, the ADC input resistance charges capacitors C F3 and C F4. The resulting potential on input C3 will be approximately midway between C2 and C4. The AD C readings of B3 and B4 may indicate a valid cell voltage when in fact the exact state of B3 and B4 is unknown. If the 100μA current sources are engaged, the potential at C3 will be pulled down. The ADC reading for B3 will approach zero and the reading for B4 will approach full scale. The amount

of change in the cell voltage reading is a function of the external ? lter capacitor and time that the 100μA current sources are connected to the cell. The best way to detect an open wire on CN is to compare the ADC readings for B N+1 with and without the internal 100μA current source. If the difference is more than 0.2V , CN is open.DISCHARGING DURING CELL MEASUREMENTS

The primary cell voltage A/D measurement commands (STCVAD and STOWAD ) automatically turn off a cell’s discharge switch while its voltage is being measured. The discharge switches for the cell above and the cell below will also be turned off during the measurement. For example, discharge switches S4, S5, and S6 will be disabled while cell 5 is being measured.

In some systems it may be desirable to allow discharging to continue during cell voltage measurements. The cell voltage A/D conversion commands STCVD C and STOWD C allow any enabled discharge switches to remain on during cell voltage measurements. This feature allows the system to perform a self-test to verify the discharge functionality and multiplexer operation.

When using the STCVDC for all cells (command 0x60), for each cell (CN) that is discharging, the adjacent lower cell (CN-1) will return a cell voltage value near 0V . To avoid misinterpretation of the cell voltages read after using this command, there are two recommendations:

1. Use the STCVDC command for all cell voltages (com-mand 0x60) with only one discharge switch on at a time. The value returned for the cell directly below the cell being discharged will be invalid and read close to 0V . The voltage reading of all other cells, including the cell being discharged, will be valid.

2. Use the individual cell commands with discharge permitted (STCVDC commands 0x61 thru 0x6c) and only turn on the discharge switch for the cell being measured. The voltage reading for the individual cell being measured and discharged will be valid.All discharge switches are automatically disabled during OV and UV comparison measurements.

Figure 3. Open Connection with RC Filtering

OPERATION

LTC6802-2

B4B3

LTC6802-2

13

68022f

OPERATION

Figure 4. External Discharge FET Connection (One Cell Shown)

POWER DISSIPATION AND THERMAL SHUTDOWN The MOSFETs connected to the pins S1 through S12 can be used to discharge battery cells. An external resistor should be used to limit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is limited by the amount of heat that can be tolerated by the L TC6802-2. Excessive heat results in elevated die temperatures. The electrical characteristics are guaranteed for die tempera-tures up to 85°C. Little or no degradation will be observed in the measurement accuracy for die temperatures up to 105°C. Damage may occur near 150°C, therefore the recommended maximum die temperature is 125°C.To protect the L TC6802-2 from damage due to overheating, a thermal shutdown circuit is included. Overheating of the device can occur when dissipating signi? cant power in the cell discharge switches. The problem is exacerbated when operating with a large voltage between V + and V – or when the thermal conductivity of the system is poor .

The thermal shutdown circuit is enabled whenever the device is not in standby mode (see Modes of Operation). If the temperature detected on the device goes above ap-proximately 145°C, the con? guration registers will be reset to default states, turning off all discharge switches and disabling A/D conversions. When a thermal shutdown has occurred, the THSD bit in the temperature register group will go high. The bit is cleared by performing a read of the temperature registers (RDTMP command).

Since thermal shutdown interrupts normal operation, the internal temperature monitor should be used to determine when the device temperature is approaching unacceptable levels.

LTC6802-2

A/D CONVERTER DIGITAL SELF TEST

T wo self test commands can be used to verify the func-tionality of the digital portions of the ADC. The self tests also verify the cell voltage registers and cell temperature registers. During these self tests a test signal is applied to the ADC. If the circuitry is working properly the cell voltage or cell temperature registers will contain identical codes. For Self Test 1 the registers will contain 0x555. For Self Test 2, the registers will contain 0xAAA. The time required for the self test function is the same as required to measure all cell voltages or all temperature sensors. Perform the self test function with CDC[2:0] set to 1 in the con? guration register .USING THE S PINS AS DIGITAL OUTPUTS OR GATE DRIVERS

The S outputs include an internal 10k pull-up resistor . Therefore the S pins will behave as a digital output when loaded with a high impedance, e.g. the gate of an external MOSFET . For applications requiring high battery discharge currents, connect a discrete PMOS switch device and suit-able discharge resistor to the cell, and the gate terminal to the S output pin, as illustrated in Figure 4.

APPLICATIONS INFORMATION

USING THE L TC6802-2 WITH LESS THAN 12 CELLS The L TC6802-2 can be used with as few as 4 cells. The minimum number of cells is governed by the supply voltage requirements of the L TC6802-2. The sum of the cell voltages must be 10V to guarantee that all electrical speci? cations are met.

Figure 5 shows an example of the L TC6802-2 when used to

monitor 7 cells. The lowest C inputs connect to the 7 cells

and the upper C inputs connect to V +. Other con? gura-tions, e.g. 9 cells, would be con? gured in the same way: the lowest C inputs connected to the battery cells and the unused C inputs connected to V +. The unused inputs will result in a reading of 0V for those channels.

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The ADC can also be commanded to measure a stack of cells by making 10 or 12 measurements, depending on the state of the CELL10 bit in the control register . Data from all 10 or 12 measurements must be down loaded when reading the conversion results. The AD C can be commanded to measure any individual cell http://www.wendangku.net/doc/c72057d084254b35eefd342a.htmlING THE GENERAL PURPOSE INPUTS/OUTPUTS (GPIO1, GPIO2)

The L TC6802-2 has 2 general purpose digital inputs/out-puts. By writing a GPIO con? guration register bit to a logic low, the open drain output can be activated. The GPIOs give the user the ability to turn on/off circuitry around the L TC6802-2. One example might be a circuit to verify the operation of the system.

When a GPIO con? guration bit is written to a logic high, the corresponding GPIO pin may be used as an input.

Figure 5. Monitoring 7 Cells with the L TC6802-2

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The read back value of that bit will be the logic level that appears at the GPIO pin.

When the MMB pin is low, the GPIO pins and the WDTB pin are treated as inputs that set the number of cells to be monitored. See the Monitor Mode section.WATCHDOG TIMER CIRCUIT

The L TC6802-2 includes a watchdog timer circuit. If no activity is detected on the SCKI pin for 2.5 seconds, the WDTB open drain output is asserted low. The WDTB pin remains low until an edge is detected on the SCKI pin.When the watchdog timer circuit times out, the con? gura-tion bits are reset to their default (power-up) state.In the power-up state, the S outputs are off. Therefore, the watchdog timer provides a means to turn off cell discharg-ing should communications to the MPU be interrupted. The IC is in the minimum power standby mode after a time out. Note that externally pulling the WDTB pin low will not reset the con? guration bits.The con? guration bit WDTEN (byte CFG0, bit 7) allows the user to disable the watchdog timer operation. The default value is WDTEN = 1 (enabled).

The watchdog timer operation is disabled when MMB is low.

When reading the con? guration register , byte CFG0 bit 7 will re? ect the state of the WDTB pin, independent of what value was written to the WDTEN bit. Consequently, if the watchdog timer is disabled by writing the WDTEN bit to 0, the WDTB pin can be used as a general purpose input, with the read value of the WDTEN bit re? ecting an input applied to the WDTB pin.REVISION CODE

The temperature register group contains a 3-bit revision code. If software detection of device revision is neces-sary, then contact the factory for details. Otherwise, the code can be ignored. In all cases, however , the values of all bits must be used when calculating the packet error code (PEC) CRC byte on data reads.

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MODES OF OPERATION

The L TC6802-2 has three modes of operation: standby, measure, and monitor. Standby mode is a power saving state where all circuits except the serial interface are turned off. In measure mode, the L TC6802-2 is used to measure cell voltages and store the results in memory. Measure mode will also monitor each cell voltage for overvoltage (OV) and undervoltage (UV) conditions. In monitor mode, the device will only monitor cells for UV and OV conditions.

A signal is output on the SDO pin to indicate the UV/OV status. The serial interface is disabled.

Standby Mode

The L TC6802-2 defaults (powers up) to standby mode. Standby mode is the lowest possible supply current state. All circuits are turned off except the serial interface and the voltage regulator. The L TC6802-2 can be programmed for standby mode by setting con? guration bits CDC[2:0] to 0. If the part is put into standby mode while AD C measurements are in progress, the measurements will be interrupted and the cell voltage registers will be in an indeterminate state. To exit standby mode, the CDC bits must be written to a value other than 0.

Measure Mode

The L TC6802-2 is in measure mode when the CDC bits are programmed with a value from 1 to 7. The IC monitors each cell voltage and produces an interrupt signal on the SDO pin indicating all cell voltages are within the UV and OV limits. There are two methods for indicating the UV/OV interrupt status: toggle polling (using a 1kHz output signal) and level polling (using a high or low output signal). The polling methods are described in the Serial Port section. The UV/OV limits are set by the VUV and VOV values in the con? guration registers. When a cell voltage exceeds the UV/OV limits a bit is set in the ? ag register. The UV and OV ? ag status for each cell can be determined using the Read Flag Register Group.If fewer than 12 cells are connected to the L TC6802-2 then it is necessary to mask the unused input channels. The MCxI bits in the con? guration registers are used to mask channels. If the CELL10 bit is high, then the inputs for cells 11 and 12 are automatically masked.

The L TC6802-2 can monitor UV and OV conditions con-tinuously. Alternatively, the duty cycle of the UV and OV comparisons can be reduced or turned off to lower the overall power consumption. The CD C bits are used to control the duty cycle.

To initiate cell voltage measurements while in measure mode, a Start A/D Conversion and Poll Status command must be sent. After the command has been sent, the L TC6802-2 will send the A/D converter status using either the toggle polling or the level polling method, as described in the Serial Port section. If the CELL10 bit is high, then only the bottom 10 cell voltages will be measured, thereby reducing power consumption and measurement time. By default the CELL10 bit is low, enabling measurement of all 12 cell voltages. During cell voltage measurement com-mands, UV and OV ? ag conditions, re? ected in the ? ag register group, are also updated. When the measurements are complete, the part will go back to monitoring UV and OV conditions at the rate designated by the CDC bits. Monitor Mode

The L TC6802-2 can be used as a simple monitoring circuit with no serial interface by pulling the MMB pin low. When in this mode, the interrupt status is indicated on the SDO pin using the toggle polling mode described in the Serial Port section. Unlike serial port polling commands, however, the toggling is independent of the state of the CSBI pin. When the MMB pin is low, all the device con? guration values are reset to the default states shown in Table 15 Memory Bit Descriptions. When MMB is held low the VUV, VOV, and CDC register values are ignored. Instead VUV and VOV use factory-programmed setings. CDC is set to state 5. The number of cells to be monitored is set by the logic levels on the WDTB and GPIO pins, as shown in Table 1.

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(logic high) for polling commands. All interface pins are voltage mode, with voltage levels sensed with respect to the V – supply. See Figure 1.Data Link Layer

Clock Phase And Polarity: The L TC6802-2 SPI-compat-ible interface is con? gured to operate in a system using CPHA=1 and CPOL=1. Consequently, data on SDI must be stable during the rising edge of SCKI.

Data Transfers: Every byte consists of 8 bits. Bytes are transferred with the most signi? cant bit (MSB) ? rst. On a write, the data value on SDI is latched into the device on the rising edge of SCKI (Figure 6). Similarly, on a read, the data value output on SDO is valid during the rising edge of SCKI and transitions on the falling edge of SCKI (Figure 7).

CSBI must remain low for the entire duration of a com-mand sequence, including between a command byte and subsequent data. On a write command, data is latched in on the rising edge of CSBI.

After a polling command has been entered, the SDO output will immediately be driven by the polling state, with the SCKI input ignored (Figure 8). See the Toggle Polling and Level Polling http://www.wendangku.net/doc/c72057d084254b35eefd342a.htmlwork Layer

Broadcast Commands: A broadcast command is one to which all devices on the bus will respond, regardless of device address. See the Bus Protocols and Commands sections.

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Table 1. Monitor Mode Cell Selection

WDTB GPIO2GPIO1CELL INPUTS MONITORED

000Cells 1 to 5001Cells 1 to 6010Cells 1 to 7011Cells 1 to 8100Cells 1 to 9101Cells 1 to 10110Cells 1 to 111

1

1

Cells 1 to 12

If MMB is low then brought high, all device con? guration values are reset to the default states including the VUV , VOV , and CDC con? guration bits.SERIAL PORT Overview

The L TC6802-2 has an SPI bus compatible serial port. D evices can be connected in parallel, using digital isolators. Multiple devices are uniquely identi? ed by a part address determined by the A0 to A3 pins.Physical Layer

On the L TC6802-2, four pins comprise the serial interface: CSBI, SCKI, SDI and SDO. The SDO and SDI may be tied together , if desired, to form a single, bi-directional port. Four address pins (A0 to A3) set the part address for ad-dress commands. The TOS pin designates the top device

CSBI

SCKI

SDI

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Figure 6. T ransmission Format (Write)

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With broadcast commands all devices can be sent com-mands simultaneously. This is useful for A/D conversion and polling commands. It can also be used with write commands when all parts are being written with the same data. Broadcast read commands should not be used in the parallel con? guration.

Address Co mmands:An address command is one in which only the addressed device on the bus responds. The ? rst byte of an address command consists of 4 bits with a value of 1000 and 4 address bits. The second byte is the command byte. See the Bus Protocols and Com-mands section.PEC Byte:The packet error code (PEC) byte is a CRC value calculated for all of the bits in a register group in the order they are read, using the following characteristic polynomial:

x8 + x2 + x + 1

On a read command, after sending the last byte of a reg-ister group, the device will shift out the calculated PEC, MSB ? rst.

Toggle Polling:Toggle polling allows a robust determina-tion both of device states and of the integrity of the con-nections between the devices in a stack. Toggle polling

CSBI SCKI SDI SDO

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Figure 7. T ransmission Format (Read) Figure 8. T ransmission Format (Poll)

CSBI SCKI SDI SDO

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APPLICATIONS INFORMATION

is enabled when the LVLPL bit is low. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the A/D converter status, data out will be low when any device is busy performing an A/D conversion and will toggle at 1kHz when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will toggle at 1kHz when none has an interrupt condition.

Toggle Polling—Address Polling: The addressed device drives the SD O line based on its state alone—low for busy/in interrupt, toggling at 1kHz for not busy/not in interupt. Toggle Polling—Parallel Broadcast Polling: No part ad-dress is sent, so all devices respond simultaneously. If a device is busy/in interrupt, it will pull SDO low. If a device is not busy/not in interrupt, then it will release the SDO line (TOS = 0) or attempt to toggle the SDO line at 1kHz (TOS =1).

The master controller pulls CSBI high to exit polling. Level polling: Level polling is enabled when the LVLPL bit is high. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the A/D converter status, data out will be low when any device is busy performing an A/D conversion and will be high when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will be high when none has an interrupt condition.

Level po lling—Address Po lling: The addressed device drives the SD O line based on its state alone—pulled low for busy/in interrupt, released for not busy/not in interupt.Level polling—Parallel Broadcast Polling: No part address is sent, so all devices respond simultaneously. If a device is busy/in interrupt, it will pull SDO low. If a device is not busy/not in interrupt, then it will release the SDO line. If any device is busy or in interrupt the SDO signal will be low. If all devices are not busy/not in interrupt, the SDO signal will be high.

The master controller pulls CSBI high to exit polling. Polling Methods: For A/D conversions, three methods can be used to determine A/D completion. First, a controller can start an A/D conversion and wait for the speci? ed conversion time to pass before reading the results. The second method is to hold CSBI low after an A/D start command has been sent. The A/D conversion status will be output on SDO. A problem with the second method is that the controller is not free to do other serial communication while waiting for A/D conversions to complete. The third method overcomes this limitation. The controller can send an A/D start command, perform other tasks, and then send a Poll A/D Converter Status (PLADC) command to determine the status of the A/D conversions.

For OV/UV interrupt status, the poll interrupt status (PLINT) command can be used to quickly determine whether any cell in a stack is in an overvoltage or undervoltage condition.

Bus Protocols

There are 6 different protocol formats, depicted in Table 3 through Table 8. Table 2 is the key for reading the protocol diagrams.

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Table 5. Broadcast Write

88888

Shift Byte N

Command Data Byte Low…Data Byte High Shift Byte 1…

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Table 8. Address Write

44888

1000Address Command Data Byte Low…Data Byte High

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