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NCV4275

NCV4275

5.0 V Low?Drop Voltage Regulator

This industry standard linear regulator has the capability to drive loads up to 450 mA at 5.0 V. It is available in DPAK and D2PAK. This device is pin?for?pin compatible with Infineon part number TLE4275.

Features

?5.0 V, ±2%, 450 mA Output Voltage

?V ery Low Current Consumption

?Active RESET

?Reset Low Down to V Q = 1.0 V

?500 mV (max) Dropout V oltage

?Fault Protection

?+45 V Peak Transient V oltage

??42 V Reverse V oltage

?Short Circuit

?Thermal Overload

?NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes

I

D

Q

GND

RO

Figure 1. Block Diagram

https://www.wendangku.net/doc/cb8718078.html,

D2PAK

5?PIN

DS SUFFIX

CASE 936A

DPAK

5?PIN

DT SUFFIX

CASE 175AA

Pin 1. I

2. RO

T

ab,3. GND*

4. D

5. Q

* T ab is connected to

Pin 3 on all packages

Device Package Shipping?

ORDERING INFORMATION

NCV4275DT DPAK75 Units/Rail NCV4275DTRK DPAK2500 T ape & Reel NCV4275DS D2PAK50 Units/Rail NCV4275DSR4D2PAK800 T ape & Reel ?For information on tape and reel specifications, including part orientation and tape sizes, please refer to our T ape and Reel Packaging Specification Brochure, BRD8011/D.

MARKING

DIAGRAMS

NCV4275

AWLYYWW

1

1

A= Assembly Location

WL, L= Wafer Lot

YY, Y= Year

WW= Work Week

PIN FUNCTION DESCRIPTION

MAXIMUM RATINGS?

(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

THERMAL CHARACTERISTICS

2.10 seconds max.

3.?5°C/+0°C allowable conditions.

4. 1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.62″thick FR4.

5. 1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.62″thick FR4.

6. 1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.62″thick FR4.

7. 1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.62″thick FR4.

?During the voltage range which exceeds the maximum tested voltage of I, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely.

ELECTRICAL CHARACTERISTICS (I = 13.5 V; ?40°C < T

< 150°C; unless otherwise noted)

Output

Reset Timing D and Output RO TYPICAL PERFORMANCE CHARACTERISTICS

Figure 2. Output Stability with Output

Capacitor ESR

OUTPUT CURRENT (mA)

E S R (W )

100

200

300

400

500

APPLICATION INFORMATION

V I

V Q

V RO Figure 3. Test Circuit

Circuit Description

The error amplifier compares a temperature?stable reference voltage to a voltage that is proportional to the output voltage (Q) (generated from a resistor divider) and drives the base of a series transistor via a buffer. Saturation control as a function of the load current prevents oversaturation of the output power device, thus preventing excessive substrate current (quiescent current).

Typical drop out voltage at 300 mA load is 250 mV, 500 mV maximum. Test voltage for drop out is 5.0 V input. Stability Considerations

The input capacitors (C I1 and C I2) are necessary to control line influences. Using a resistor of approximately 1.0 ? in series with C I2 can solve potential oscillations due to stray inductance and capacitance.

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start?up delay, load transient response and loop stability.

The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (?25°C to ?40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information.

The value for the output capacitor C Q shown in Figure 3 should work for most applications, however it is not necessarily the optimized solution. Stability is guaranteed for C Q > 22 m F and an ESR ≤ 5.0 ?.Calculating Power Dissipation

in a Single Output Linear Regulator

The maximum power dissipation for a single output regulator (Figure 4) is:

P D(max)+[V I(max)*V Q(min)]I Q(max)(1) )V I(max)I q

where

V I(max)is the maximum input voltage,

V Q(min)is the minimum output voltage,

I Q(max)is the maximum output current for the

application,

I q is the quiescent current the regulator

consumes at I Q(max).

Once the value of P D(max) is known, the maximum permissible value of R q JA can be calculated:

R q JA+150°C*T A

D

(2) The value of R q JA can then be compared with those in the package section of the data sheet. Those packages with R q JA’s less than the calculated value in Equation 2 will keep the die temperature below 150°C.

In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.

Figure 4. Single Output Regulator with Key

Performance Parameters Labeled

V I V Q

Heat Sinks

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.

Each material in the heat flow path between the IC and the outside environment will have a thermal resistance.Like series electrical resistances, these resistances are summed to determine the value of R q JA :

R q JA +R q JC )R q CS )R q SA

(3)

where

R q JC is the junction?to?case thermal resistance,R q CS is the case?to?heatsink thermal resistance,R q SA is the heatsink?to?ambient thermal

resistance.R q JC appears in the package section of the data sheet.Like R q JA , it too is a function of package type. R q CS and R q SA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.

Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note

AN1040/D.

V

V Delay Time

Reaction Time

Power?on?Reset

Thermal Shutdown

Voltage Dip at Input

Undervoltage

Secondary Spike

Overload at Output

Figure 5. Reset Timing

The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula:

R(t)+

n S

i+1

R iǒ1?e?tńtau iǔ

150Figure 6. q JA vs. Copper Spreader Area,

DPAK 5?Lead Figure 7. q JA vs. Copper Spreader Area,

D 2PAK 5?Lead

200250300350400450500550600650700750

COPPER AREA (mm 2)

q J A

(C °/W )

150200250300350400450500550600650700750

COPPER AREA (mm 2)

100

101.0

0.1

0.01TIME (sec)

R (t ) C °/W

0.0000001

0.0000010.000010.00010.0010.010.1 1.010*******

Figure 8. Single?Pulse Heating Curves, DPAK 5?Lead

100

101.0

0.1

0.01TIME (sec)

R (t ) C °/W

0.0000001

0.0000010.000010.00010.0010.010.1 1.010*******

Figure 9. Single?Pulse Heating Curves, D 2PAK 5?Lead

100

10

1.0

0.1

0.01

PULSE WIDTH (sec)

R q J A 788 m m 2 C °/W

0.0000001

0.000001

0.00001

0.0001

0.001

0.01

0.1

1.0

10

100

1000

100

10

1.0

0.1

0.01

PULSE WIDTH (sec)

R q J A 736 m m 2 C °/W

0.0000001

0.000001

0.00001

0.0001

0.001

0.01

0.1

1.0

10

100

1000

Figure 10. Duty Cycle for 1” Spreader Boards, DPAK 5?Lead

Figure 11. Duty Cycle for 1” Spreader Boards, D 2PAK 5?Lead

R R R

R Figure 12. Grounded Capacitor Thermal Network (“Cauer” Ladder)

R R R R time constant; amplitudes are the resistances.(thermal ground)

Figure 13. Non?Grounded Capacitor Thermal Ladder (“Foster” Ladder)

DPAK 5 CENTER LEAD CROP

DT SUFFIX

CASE 175AA?01

ISSUE O

NOTES:

D 2PAK 5 LEAD DS SUFFIX CAS

E 936A?02

ISSUE B

5 REF

NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198

2.

2.CONTROLLING DIMENSION: INCH.

3.TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K.

4.DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6.

5.DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM.

DIM A MIN MAX MIN MAX MILLIMETERS 0.3860.4039.80410.236INCHES B 0.3560.3689.0429.347C 0.1700.180 4.318 4.572D 0.0260.0360.6600.914E 0.0450.055 1.143 1.397G 0.067 BSC 1.702 BSC H 0.5390.57913.69114.707K 0.050 REF 1.270 REF L 0.0000.0100.0000.254M 0.0880.102 2.235 2.591N 0.0180.0260.4570.660P 0.0580.078 1.473 1.981R 5 REF S 0.116 REF 2.946 REF U 0.200 MIN 5.080 MIN V

0.250 MIN

6.350 MIN

_

_

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.

SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION

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