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ADP3110AKRZ中文资料

ADP3110A

Dual Bootstrapped, 12 V MOSFET Driver with Output Disable

The ADP3110A is a single Phase 12 V MOSFET gate drivers optimized to drive the gates of both high?side and low?side power MOSFETs in a synchronous buck converter. The high?side and low?side driver is capable of driving a 3000 pF load with a 25 ns propagation delay and a 30 ns transition time.

With a wide operating voltage range, high or low side MOSFET

gate drive voltage can be optimized for the best efficiency. Internal adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both MOSFETs.

The floating top driver design can accommodate VBST voltages as high as 35 V, with transient voltages as high as 40 V. Both gate outputs can be driven low by applying a low logic level to the Output Disable (OD) pin. An Undervoltage Lockout function ensures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the IC with overtemperature protection. Features

?All?In?One Synchronous Buck Driver ?Bootstrapped High?Side Drive

?One PWM Signal Generates Both Drives

?Anticross Conduction Protection Circuitry

?OD for Disabling the Driver Outputs Meets CPU VR Requirement when Used with Patented FlexMode t Controller

?These are Pb?Free Devices

Applications

?Multiphase Desktop CPU Supplies

?Single?Supply Synchronous Buck Converters

Device Package Shipping?

ORDERING INFORMATION

SO?8

(Pb?Free)

98 Units / Rail ADP3110AKRZ

A= Assembly Location

L= Wafer Lot

Y= Year

W= Work Week

G= Pb?Free Package

MARKING

DIAGRAMS

PIN CONNECTIONS

SO?8

D SUFFIX

CASE 751

DRVL

PGND

SWN

DRVH

https://www.wendangku.net/doc/cf10315444.html,

?For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

DFN8

MN SUFFIX

CASE 506BJ

DRVL

V CC

PGND

SWN

DRVH

BST

(Top View)

SO?8

(Pb?Free)

2500 Tape & Reel ADP3110AKRZ?RL

DFN8

(Pb?Free)

5000 Tape & Reel ADP3110AKCPZ?RL

L3E

ALYW G

Figure 1. Block Diagram

V CC DRVH BST

SWN

DRVL PGND

PIN DESCRIPTION

SO ?8DFN8Symbol Description

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this bootstrap voltage for the high ?side MOSFET as it is switched. The recommended capacitor value is between 100 nF and 1.0 m F. An external diode is required with the ADP3110A.22IN Logic ?Level Input. This pin has primary control of the drive outputs.

33OD Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.44V CC Input Supply. A 1.0 m F ceramic capacitor should be connected from this pin to PGND.55DRVL Output drive for the lower MOSFET.

66PGND Power Ground. Should be closely connected to the source of the lower MOSFET.77SWN Switch Node. Connect to the source of the upper MOSFET.8

DRVH

Output drive for the upper MOSFET.

MAXIMUM RATINGS

Rating Value Unit Operating Ambient Temperature, T A0 to 85°C Operating Junction Temperature, T J (Note 1)0 to 150°C

Package Thermal Resistance: SO?8

Junction?to?Case, R q JC

Junction?to?Ambient, R q JA (2?Layer Board) Package Thermal Resistance: DFN8 (Note 2) Junction?to?Case, R q JC (From die to exposed pad) Junction?to?Ambient, R q JA 45

123

7.5

°C/W

Storage Temperature Range, T S?65 to 150°C Lead Temperature Soldering (10 sec): Reflow (SMD styles only)Pb?Free (Note 3)260 peak°C JEDEC Moisture Sensitivity Level SO?8 (260 peak profile)1?Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1.Internally limited by thermal shutdown, 150°C min.

2. 2 layer board, 1 in2 Cu, 1 oz thickness.

3.60?180 seconds minimum above 237°C.

NOTE:This device is ESD sensitive. Use standard ESD precautions when handling.

MAXIMUM RATINGS

Pin Symbol Pin Name V MAX V MIN V CC Main Supply Voltage Input15 V?0.3 V

PGND Ground0 V0 V

BST Bootstrap Supply Voltage Input35 V wrt/PGND

40 V < 50 ns wrt/PGND

15 V wrt/SW

?0.3 V wrt/SW

SW Switching Node

(Bootstrap Supply Return)

35 V

40 V < 50 ns

?5.0 V

?10 V < 200 ns

DRVH High?Side Driver Output BST + 0.3 V?0.3 V wrt/SW

? 2.0 V < 200 ns wrt/SW

DRVL Low?Side Driver Output V CC + 0.3 V?0.3 V DC

?5.0 V < 200 ns IN DRVH and DRVL Control Input 6.5 V?0.3 V

OD Output Disable 6.5 V?0.3 V NOTE:All voltages are with respect to PGND except where noted.

ELECTRICAL CHARACTERISTICS (Note 4)(V CC = 12 V, T A = 0°C to +85°C, T J= 0°C to +125°C unless otherwise noted.) Characteristic Symbol Condition Min Typ Max Unit Supply

Supply Voltage Range V CC? 4.6?13.2V Supply Current I SYS BST = 12 V, IN = 0 V?0.7 5.0mA OD Input

Input Voltage High V OD_HI? 2.0??V Input Voltage Low V OD_LO???0.8V Hysteresis??400?mV Input Current No internal pullup or pulldown resistors?1.0?+1.0m A PWM Input

Input Voltage High V PWM_HI? 2.0??V Input Voltage Low V PWM_LO???0.8V Hysteresis???400?mV Input Current?No internal pullup or pulldown resistors?1.0?+1.0m A High?Side Driver

Output Resistance, Sourcing Current?BST ? SW = 12 V? 2.2 3.4W Output Resistance, Sinking Current?BST ? SW = 12 V? 1.0 1.8W Output Resistance, Unbiased?BST ? SW = 0 V?15?k W

Transition Times t rDRVH

t fDRVH BST ? SW = 12 V, C LOAD = 3.0 nF

(See Figure 3)

?20

Propagation Delay Times (Note 5)t pdhDRVH

t pdlDRVH

t pdlOD

t pdhOD BST ? SW = 12 V, C LOAD = 3.0 nF

BST ? SW = 12 V, C LOAD = 3.0 nF

(See Figure 3)

(See Figure 2)

3245

SW Pulldown Resitance?SW to PGND?15?k W Low?Side Driver

Output Resistance, Sourcing Current?? 1.8 3.4W Output Resistance, Sinking Current?? 1.0 1.8W Output Resistance, Unbiased?V CC = PGND?15?k W

Transition Times t rDRVL

t fDRVL C LOAD = 3.0 nF, (See Figure 3)?16

Propagation Delay Times (Note 5)t pdhDRVL

t pdlDRVL

t pdlOD

t pdhOD C LOAD = 3.0 nF, (See Figure 3)

(Note 6, t pdhDRVL only)

(See Figure 2)

?12

Timeout Delay?DRVH ? SW = 0?85?ns Undervoltage Lockout

UVLO Startup?? 3.9 4.3 4.5V UVLO Shutdown?? 3.7 4.1 4.3V Hysteresis??0.10.20.4V

4.All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).

5.For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.

6.Guaranteed by design; not tested in production.

APPLICATIONS INFORMATION

Theory of Operation

The ADP3110A are single phase MOSFET drivers designed for driving two N?channel MOSFETs in a synchronous buck converter topology. The ADP3110A will operate from 5.0 V or 12 V, but have been optimized for high current multi?phase buck regulators that convert 12 V rail directly to the core voltage required by complex logic chips.

A single PWM input signal is all that is required to properly drive the high?side and the low?side MOSFETs. Each driver is capable of driving a 3 nF load at frequencies up to 1 MHz. Low?Side Driver

The low?side driver is designed to drive a ground?referenced low R DS(on) N?Channel MOSFET. The voltage rail for the low?side driver is internally connected to the V CC supply and PGND.

High?Side Driver

The high?side driver is designed to drive a floating low R DS(on) N?channel MOSFET. The gate voltage for the high side driver is developed by a bootstrap circuit referenced to Switch Node (SW) pin.

The bootstrap circuit is comprised of an external diode, and an external bootstrap capacitor. When the ADP3110A are starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to V CC through the bootstrap diode See Figure 4. When the PWM input goes high, the high?side driver will begin to turn on the high?side MOSFET using the stored charge of the bootstrap capacitor. As the high?side MOSFET turns on, the SW pin will rise. When the high?side MOSFET is fully on, the switch node will be at 12 V, and the BST pin will be at 12 V plus the charge of the bootstrap capacitor (approaching 24 V).

The bootstrap capacitor is recharged when the switch node goes low during the next cycle.

Safety Timer and Overlap Protection Circuit

It is very important that MOSFETs in a synchronous buck regulator do not both conduct at the same time. Excessive shoot?through or cross conduction can damage the MOSFETs, and even a small amount of cross conduction will cause a decrease in the power conversion efficiency. The ADP3110A prevent cross conduction by monitoring the status of the external mosfets and applying the appropriate amount of “dead?time” or the time between the turn off of one MOSFET and the turn on of the other MOSFET.

When the PWM input pin goes high, DRVL will go low after a propagation delay (tpdlDRVL). The time it takes for the low?side MOSFET to turn off (tfDRVL) is dependent on the total charge on the low?side MOSFET gate. The ADP3110A monitor the gate voltage of both MOSFETs and the switchnode voltage to determine the conduction status of the MOSFETs. Once the low?side MOSFET is turned off an internal timer will delay (tpdhDRVH) the turn on of the high?side MOSFET

Likewise, when the PWM input pin goes low, DRVH will go low after the propagation delay (tpdDRVH). The time to turn off the high?side MOSFET (tfDRVH) is dependent on the total gate charge of the high?side MOSFET. A timer will be triggered once the high?side mosfet has stopped conducting, to delay (tpdhDRVL) the turn on of the low?side MOSFET

Power Supply Decoupling

The ADP3110A can source and sink relatively large currents to the gate pins of the external MOSFETs. In order to maintain a constant and stable supply voltage (V CC) a low ESR capacitor should be placed near the power and ground pins. A 1 m F to 4.7 m F multi layer ceramic capacitor (MLCC) is usually sufficient.

Input Pins

The PWM input and the Output Disable pins of the ADP3110A have internal protection for Electro Static Discharge (ESD), but in normal operation they present a relatively high input impedance. If the PWM controller does not have internal pulldown resistors, they should be added externally to ensure that the driver outputs do not go high before the controller has reached its under voltage lockout threshold. The NCP5381 controller does include a passive internal pull?down resistor on the drive?on output pin. Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor (C BST) and the internal (or an external) diode. Selection of these components can be done after the high?side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitance is determined using the following equation:

C BST+Q GATE

D V BST

where Q GATE is the total gate charge of the high?side MOSFET, and D V BST is the voltage droop allowed on the high?side MOSFET drive. For example, a NTD60N03 has a total gate charge of about 30 nC. For an allowed droop of 300 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used.

The bootstrap diode must be rated to withstand the maximum supply voltage plus any peak ringing voltages that may be present on SW. The average forward current can be estimated by:

I F(AVG)+Q GATE f MAX

where f MAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in?circuit, since this is dependent on the source impedance of the 12 V supply and the ESR of C BST.

Figure 2. Output Disable Timing Diagram

DRVH or DRVL

Figure 3. Nonoverlap Timing Diagram

DRVL

DRVH ?SW

Vout

Output Enable

PWM in

Figure 4. ADP3110A Example Circuit

DFN8 3x3, 0.5P

CASE 506BJ?01

ISSUE O

*For additional information on our Pb?Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERMASK DEFINED

NOTES:

1.DIMENSIONS AND TOLERANCING PER ASME

Y14.5M, 1994.

2.CONTROLLING DIMENSION: MILLIMETERS.

3.DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND 0.30

MM FROM TERMINAL.

4.COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A10.000.05

A30.20 REF

b0.180.30

D 3.00 BSC

D2 1.64 1.84

E 3.00 BSC

E2 1.35 1.55

e0.50 BSC

K0.20???

L0.300.50

DETAIL A

OPTIONAL

CONSTRUCTION

DETAIL A

DETAIL B

OPTIONAL

CONSTRUCTION

OPTIONAL

CONSTRUCTION

L10.000.03

DIMENSION: MILLIMETERS

MOUNTING FOOTPRINT

SOIC ?8D SUFFIX CASE 751?07ISSUE AJ

0.6ǒmm inches

ǔSCALE 6:1

*For additional information on our Pb ?Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6.751?01 THRU 751?06 ARE OBSOLETE. NEW STANDARD IS 751?0

DIM A MIN MAX MIN MAX INCHES

4.80

5.000.1890.197MILLIMETERS B 3.80 4.000.1500.157C 1.35 1.750.0530.069D 0.330.510.0130.020G 1.27 BSC 0.050 BSC H 0.100.250.0040.010J 0.190.250.0070.010K 0.40 1.270.0160.050M 0 8 0 8 N 0.250.500.0100.020S

5.80

6.20

0.2280.244

0.25 (0.010)

Z S

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FlexMode is a trademark of Analog Devices, Inc.

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