pwm控制直流电机_verilog_l9110
module pwm (clk,
en,
speed,
dir_in,
pwm1,
pwm2);
input clk;
input en;
input [2:0] speed;
input dir_in;
output pwm1;
output pwm2;
//reg dir_out1;
//reg dir_out2;
//reg pwm_signal;
wire w_dir1,w_dir2;
counter u1(.clk(clk),
.en_dir1(w_dir1),
.en_dir2(w_dir2),
.speed(speed),
.out1(pwm1),
.out2(pwm2));
direction u2(.clk(clk),
.dir_in(dir_in),
.dir_out1(w_dir1),
.dir_out2(w_dir2)); endmodule
module counter(clk,
en_dir1,
en_dir2,
speed,
out1,
out2);
input clk; //系统时钟
input en_dir1; //正转使能端
input en_dir2; //反转使能端
input [2:0] speed; //速度调节，3个档，100最快
output out1; //输出正转
output out2; //输出反转
reg out1;
reg out2;
reg [6:0] cnt; //计数，用来产生波形
always@(posedge clk)
begin
if(cnt < 7'd100)
cnt <= cnt + 7'b1;
else
cnt <= 7'b0;
end
always@(posedge clk)
begin
if(en_dir1)
if(speed == 3'b100) //3档，占空比90%
if(cnt < 7'd10)
out1 <= 1'b0;
else
out1 <= 1'b1;
else if(speed == 3'b010) //2档，占空比60%
if(cnt < 7'd80)//40)
out1 <= 1'b0;
else
out1 <= 1'b1;
else if(speed != 3'b000 ) //1档，占空比30%(实际上操作条件为“只要不等于000，就执行30%占空比”，挡位间能平滑过渡)
if(cnt < 7'd95)//70)
out1 <= 1'b0;
else
out1 <= 1'b1;
else //档位为0，输出0
out1 <= 1'b0;
else
out1 <= 1'b0;
end
always@(posedge clk)
begin
if(en_dir2)
if(speed == 3'b100) //3档，占空比90%
if(cnt < 7'd10)
out2 <= 1'b0;
else
out2 <= 1'b1;
else if(speed == 3'b010) //2档，占空比20%
if(cnt < 7'd80)//40)
out2 <= 1'b0;
else
out2 <= 1'b1;
else if(speed != 3'b000 ) //1档，占空比5%(实际上操作条件为“只要不等于000，就执行5%占空比”，挡位间能平滑过渡)
if(cnt < 7'd95)//70)
out2 <= 1'b0;
else
out2 <= 1'b1;
else //档位为0，输出0
out2 <= 1'b0;
else
out2 <= 1'b0;
end
endmodule
module direction(clk, //方向控制模块，用来决定正转还是反转
dir_in,
dir_out1,
dir_out2);
input clk;
input dir_in;
output dir_out1; //dir_out1=1，dir_out2=0时，正转；反之则反转
output dir_out2;
reg dir_out1;
reg dir_out2;
always@(posedge clk )
begin
if(dir_in) //控制信号为1时，正转begin
dir_out1 <= 1'b1;
dir_out2 <= 1'b0;
end
else
begin //控制信号为0时，反转dir_out1 <= 1'b0;
dir_out2 <= 1'b1;
end
end
endmodule