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MAX5936/MAX5937

-48V Hot-Swap Controllers with V IN

Step Immunity and No R SENSE

________________________________________________________________Maxim Integrated Products 1

19-3281; Rev 1; 1/05

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at https://www.wendangku.net/doc/cf15242305.html,.

General Description

The MAX5936/MAX5937 are hot-swap controllers for -10V to -80V rails. The MAX5936/MAX5937 allow circuit line cards to be safely hot-plugged into a live back-plane without causing a glitch on the power supply.These devices integrate a circuit-breaker function requiring no R SENSE .

The MAX5936/MAX5937 provide a controlled turn-on for circuit cards, limiting inrush, preventing glitches on the power-supply rail, and preventing damage to board connectors and components. Before startup, the devices perform a Load Probe? test to detect the presence of a short-circuit condition. If a short-circuit condition does not exist, the device limits the inrush current drawn by the load by gradually turning on the external MOSFET. Once the external MOSFET is fully enhanced, the MAX5936/MAX5937 provides overcur-rent and short-circuit protection by monitoring the volt-age drop across the R DS(ON)of the external power MOSFET. The MAX5936/MAX5937 integrate a 400mA fast G ATE pulldown to guarantee that the power MOSFET is rapidly turned off in the event of an overcur-rent or short-circuit condition.

The MAX5936/MAX5937 protect the system against input voltage (V IN ) steps by providing V IN step immuni-ty. The MAX5936/MAX5937 provide an accurate UVLO voltage. The MAX5936 has an open-drain, active-low PGOOD output and the MAX5937 has an open-drain,active-high PGOOD output.

The MAX5936/MAX5937 are offered with 100mV,200mV, and 400mV circuit-breaker thresholds, in addi-tion to a non-circuit-breaker option. These devices are offered in latched and autoretry fault management, are available in 8-pin SO packages, and specified for the extended (-40°C to +85°C) temperature range (see the Selector Guide ).

Applications

Servers

Telecom Line Cards Network Switches Solid-State Circuit Breaker Network Routers

Features

?-10V to -80V Operation ?No R SENSE Required

?Drives Large Power MOSFETS

?Programmable Inrush Current Limit During Hot Plug ?100mV, 200mV, 400mV, and No-Circuit-Breaker Threshold Options ?Circuit-Breaker Fault with Transient Rejection ?Shorted Load Detection (Load Probe) Before Power MOSFET Turn-On ?±2.4% Accurate Undervoltage Lockout (UVLO)?Autoretry and Latched Fault Management Available ?Low Quiescent Current

Pin Configuration

Load Probe is a trademark of Maxim Integrated Products, Inc.

Ordering Information

Note:The first “_” represents A for the autoretry and L for the latched fault management option.

The second “_” represents the circuit-breaker threshold. See the Selector Guide for additional information.

Selector Guide and Typical Operating Circuit appear at end of data sheet.

M A X 5936/M A X 5937

-48V Hot-Swap Controllers with V IN Step Immunity and No R SENSE 2_______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

V EE , V OUT , PGOOD (PGOOD ), LP,

STEP_MON to GND............................................+0.3V to -85V PGOOD (PGOOD ) to V OUT ....................................-0.3V to +85V PGOOD (PGOOD ), LP, STEP_MON to V EE ............-0.3V to +85V GATE to V EE ...........................................................-0.3V to +20V UVLO to V EE .............................................................-0.3V to +6V Input Current

LP (internally, duty-cycle limited).........................................1A PGOOD (PGOOD ) (continuous).....................................80mA

GATE (during 15V clamp, continuous)...........................30mA GATE (during 2V clamp, continuous).............................50mA GATE (during gate pulldown, continuous)......................50mA Continuous Power Dissipation (T A = +70°C)

8-Pin SO (derate 5.9mW/°C above +70°C)..................471mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature .....................................................+150°C Storage Temperature Range ............................-65°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C

ELECTRICAL CHARACTERISTICS

= -10V to -80V, V = GND - V , V =V , R = 200?, UVLO open, T = -40°C to +85°C, unless otherwise noted.

MAX5936/MAX5937

-48V Hot-Swap Controllers with V IN

Step Immunity and No R SENSE

ELECTRICAL CHARACTERISTICS (continued)

M A X 5936/M A X 5937

-48V Hot-Swap Controllers with V IN Step Immunity and No R SENSE 4_______________________________________________________________________________________

Note 2:All limits are 100% tested at +25°C and +85°C. Limits at -40°C and -10°C are guaranteed by characterization.Note 3:Delay time from a valid on-condition until the load probe test begins.

Note 4:V EE or UVLO voltages below V UVLO,F or V UVLO_REF,F , respectively, are ignored during this time.

Note 5:The time (V OUT - V EE ) > V SC + overdrive until (V GATE - V EE ) drops to approximately 90% of its initial high value.Note 6:The time when the PGOOD (PGOOD ) condition is met until the PGOOD (PGOOD ) signal is asserted.

ELECTRICAL CHARACTERISTICS (continued)

MAX5936/MAX5937

-48V Hot-Swap Controllers with V IN

Step Immunity and No R SENSE

_______________________________________________________________________________________5

SUPPLY CURRENT vs. INPUT VOLTAGE

M A Z 5936 t o c 01

INPUT VOLTAGE (V)S U P P L Y C U R R E N T (m A )

0.20.40.60.81.01.21.41.61.82.0010

SUPPLY CURRENT vs. TEMPERATURE

TEMPERATURE (°C)S U P P L Y C U R R E N T (m A )

603510-150.20.40.60.81.01.20

-4085GATE-DRIVE VOLTAGE vs. INPUT VOLTAGE

M A X 536 t o c 03

INPUT VOLTAGE (V)

G A T E -D R I V E V O L T A G E (V )

7060405030206.57.07.58.08.59.09.510.010.5

6.0

1080

GATE PULLDOWN CURRENT

vs. GATE VOLTAGE

M A X 5936 t o c 04

V GATE (V)

G A T E P U L L D O W N C U R R E N T (m A )

50100150200250300

35040045050000

RETRY TIME vs. TEMPERATURE

TEMPERATURE (°C)

R E T R Y T I M E (s )

-15

3.1

3.23.33.43.53.63.73.83.9

4.0

3.0-40

STARTUP WAVEFORM

MAX5936 toc06

40ms/div

V IN 50V/div V GATE 10V/div V OUT 50V/div I IN 2A/div

V PGOOD 50V/div MAX5936_A CIRCUIT-BREAKER EVENT

MAX5936 toc07

1ms/div

V GATE 10V/div

V OUT 50V/div

I IN 2A/div

V PGOOD 50V/div Typical Operating Characteristics

(V EE = -48V, GND = 0V, V IN = GND - V EE , all voltages are referenced to V EE , T A = +25°C, unless otherwise noted.)

M A X 5936/M A X 5937

-48V Hot-Swap Controllers with V IN Step Immunity and No R SENSE 6

_______________________________________________________________________________________

MAX5936_A SHORT-CIRCUIT EVENT

MAX5936 toc08

400ns/div

V GATE 10V/div

V OUT 50V/div I IN

10A/div

V PGOOD 50V/div

NORMALIZED CIRCUIT-BREAKER THRESHOLD vs. TEMPERATURE

M A X 5936 t o c 09

TEMPERATURE (°C)

N O R M A L I Z E D C I R C U I T -B R E A K E R T H R E S H O L D (%)

-15

0.60.81.01.21.41.60.4-40

V OUT SLEW RATE vs. TEMPERATURE

TEMPERATURE (°C)

S L E W R A T E (V /m s )

-15

5.5

6.0 6.5

7.07.5

8.08.5

9.09.510.0

5.0

-40

MAX5936_A INPUT VOLTAGE STEP EVENT (NO FAULT)

4ms/div

GATE OUT IN V PGOOD IN R LOAD = 75?

MAX5936_A INPUT VOLTAGE

STEP EVENT (FAULT)

4ms/div

GATE OUT IN V PGOOD

IN R LOAD = 75?

GATE TO V EE CLAMP VOLTAGE

AT POWER OFF

I SINK (mA)

G A T E C L A M P I N G V O L T A G E (V )

181614121086420.51.01.52.02.53.000

GATE TO V EE CLAMP VOLTAGE MOSFET FULLY ENHANCED

I SINK (mA)

G A T E C L A M P I N G V O L T A G E (V )

181612144681029101112131415161718

020

Typical Operating Characteristics (continued)

(V EE = -48V, GND = 0V, V IN = GND - V EE , all voltages are referenced to V EE , T A = +25°C, unless otherwise noted.)

MAX5936/MAX5937

-48V Hot-Swap Controllers with V IN

Step Immunity and No R SENSE

_______________________________________________________________________________________

Detailed Description

The MAX5936/MAX5937 hot-swap controllers incorpo-rate overcurrent fault management and are intended for negative-supply-rail applications. The MAX5936/MAX5937 eliminate the need for an external R SENSE and include V IN input-step protection and load probe,which prevents powering up into a shorted load. They are intended for negative 48V telecom power systems where low cost, flexibility, multifault management, and compact size are required. The MAX5936/MAX5937 are ideal for the widest range of systems from those requiring low current with small MOSFETs to high-current systems requiring large power MOSFETs and low on-resistance.

The MAX5936/MAX5937 control an external n-channel power MOSFET placed in the negative supply path of an external load. When no power is applied, the GATE output of the MAX5936/MAX5937 clamps the V GS of the MOSFET to 2V, keeping the MOSFET turned off. When power is applied to the MAX5936/MAX5937, the 2V

down device pulling G ATE to V EE and the V GS of the MOSFET to 0V. As shown in Figure 2, this transition enables the MAX5936/MAX5937 to keep the power MOSFET continually off during the board insertion phase when the circuit board first makes contact with the backplane. Without this clamp, the GATE output of a powered-down controller would be floating and the MOSFET reverse transfer capacitance (gate-to-drain)would pull up and turn on the MOSFET gate when the MOSFET drain is rapidly pulled up by the V IN step dur-ing backplane contact. The MAX5936/MAX5937 G ATE clamp can overcome the gate-to-drain capacitance of large power MOSFETs with added slew-rate control (C SLEW ) capacitors while eliminating the need for addi-tional gate-to-source capacitance. The MAX5936/MAX5937 will keep the MOSFET off indefinitely if the supply voltage is below the user-set UVLO threshold or if a short circuit is detected in the load connected to the drain of the power MOSFET.

M A X 5936/M A X 5937

-48V Hot-Swap Controllers with V IN Step Immunity and No R SENSE 8

_______________________________________________________________________________________

The MAX5936/MAX5937 conduct a load-probe test after contact transients from the hot plug-in have settled. This follows the MAX5936/MAX5937 power-up (when the UVLO condition has been met for 220ms (t LP )) and prior to the turn-on of the power MOSFET. This test pulls a user-programmable current through the load (1A, max)for up to 220ms and tests for a voltage of 200mV across the load at V OUT . This current is set by an external resis-tor, R LP , between V OUT and LP (Figure 14). When the voltage across the load exceeds 200mV, the test is trun-cated and the GATE turn-on sequence is started. If at the end of the 220ms test period the voltage across the load has not reached 200mV, the load is assumed to be short-ed and the current to the load from the LP pin is shut off.The MAX5936A_/MAX5937A_ will timeout for 16 x t LP then retry the load-probe test. The MAX5936L_/MAX5937L_ will latch the fault condition indefinitely until

the UVLO is brought below 1.125V for 1.5ms or the power is recycled. See the Applications Information section for recommendations on selecting R LP to set the current level.

Upon successful completion of the load-probe test, the MAX5936/MAX5937 enter the power-up GATE cycle and begin ramping the G ATE voltage with a 52μA current source. This current source is restricted if V OUT begins to ramp down faster than the default 9V/ms slew rate.Charging up G ATE enhances the power MOSFET in a controlled manner and ramping V OUT at a user-settable rate controls the inrush current from the backplane. The MAX5936/MAX5937 continue to charge up the G ATE until one of two events occurs: a normal power-up GATE cycle is completed or a power-up to fault management is detected (see the GATE Cycles section in Appendix A ).

Figure 1. Functional Block Diagram

MAX5936/MAX5937

-48V Hot-Swap Controllers with V IN

Step Immunity and No R SENSE

_______________________________________________________________________________________

In a normal power-up GATE cycle, the voltage at V OUT (referenced to V EE ) ramps to below 72% of the circuit-breaker threshold voltage, V CB . At this time, the remaining GATE voltage is rapidly pulled up to full enhancement.PGOOD is asserted 1.26ms after GATE is fully enhanced (see Figure 4). If the voltage at V OUT remains above 72%of the V CB (when GATE reaches 90% of full enhance-ment), then a power-up to fault management fault has occurred (see Figure 5). GATE is rapidly pulled to V EE ,turning off the power MOSFET and disconnecting the load. PGOOD remains deasserted and the MAX5936/MAX5937 enter the fault management mode.

When the power MOSFET is fully enhanced, the MAX5936/MAX5937 monitor the drain voltage (V OUT ) for circuit-breaker and short-circuit faults. The MAX5936/MAX5937 make use of the power MOSFET’s R DS(ON) as the current-sense resistance to detect excessive current through the load. The short-circuit threshold voltage,V SC , is twice V CB (V SC = 2 x V CB ) and is available in 100mV, 200mV, and 400mV thresholds. V CB and V SC are temperature-compensated (increasing with tempera-ture) to track the normalized temperature coefficient of R DS(ON) for typical power MOSFETs.

When the load current is increased during full enhance-ment, this causes V OUT to exceed V CB but remains less than V SC , and starts the 1.2ms circuit-breaker glitch rejection timer. At the end of the glitch rejection period,if V OUT still exceeds V CB , the G ATE is immediately pulled to V EE (330ns), PGOOD (PGOOD ) is deasserted,and the part enters fault management. Alternatively,during full enhancement when V OUT exceeds V SC ,there is no glitch rejection timer. G ATE is immediately pulled to V EE , PG OOD is deasserted, and the part enters fault management.

Figure 3. Load Probe Test During Initial Power-Up

40ms/div

V 20V/div

ALL VOLTAGES

REFERENCED TO GND Figure 2. GATE Voltage Clamp During Power-Up 4ms/div

C IN = 100μF

Figure 4. MAX5936 Normal Condition 40ms/div

Figure 5. MAX5936 Startup in Fault Condition

40ms/div

M A X 5936/M A X 5937

-48V Hot-Swap Controllers with V IN Step Immunity and No R SENSE

______________________________________________________________________________________

The V IN step immunity provides a means for transition-ing through a large step increase in V IN with minimal backplane inrush current and without shutting down the load. Without V IN step immunity (when the power MOSFET is fully enhanced), a step increase in V IN will result in a high inrush current and a large step in V OUT ,which can trip the circuit breaker. With V IN step immu-nity, the STEP_MON input detects the step before a short circuit is detected at V OUT and alters the MAX5936/MAX5937 response to V OUT exceeding V SC due to the step. The 1.25V voltage threshold at STEP_MON and a 10μA current source at STEP_MON allow the user to set the sensitivity of the step detection with an external resistor to V EE . A capacitor is placed between GND and the STEP_MON input, which, in con-junction with the resistor, sets the STEP_MON time con-stant. When a step is detected by the STEP_MON input to rise above its threshold (STEP TH ), the overcurrent fault management is blocked and remains blocked as long as STEP TH is exceeded. When STEP TH is exceed-ed, the MAX5936/MAX5937 take no action until V OUT rises above V SC or above V CB for the 1.2ms circuit-breaker glitch rejection period. When either of these conditions occurs, a step G ATE cycle begins and the GATE is immediately brought to V EE , which turns off the power MOSFET to minimize the resulting inrush current surge from the backplane and PGOOD remains assert-ed. GATE is held at V EE for 350μs, and after about 1ms,begins to ramp up thereby enhancing the power MOSFET in a controlled manner as in the power-up G ATE cycle. This provides a controlled inrush current to charge the load capacitance to the new supply volt-age (see the GATE Cycles section in Appendix A ).

As in the case of the power-up G ATE cycle, if V OUT drops to less than 72% of the programmed V CB , inde-pendent of the state of STEP_MON, the G ATE voltage

is rapidly pulled to full enhancement. PGOOD remains asserted throughout the step. Otherwise, if the STEP_MON input has decayed below its threshold but V OUT remains above 72% of the programmed V CB (when G ATE reaches 90% of full enhancement), (a step-to-fault management fault has occurred). GATE is rapidly pulled to V EE , turning off the power MOSFET and disconnecting the load, PG OOD (PGOOD ) is deasserted, and the MAX5936/MAX5937 enter the fault management mode.

Fault Management

Fault management can be triggered by the following conditions:

?V OUT exceeds 72% of V CB during G ATE ramp at 90% of full enhancement,

?V OUT exceeds the V CB for longer than 1.2ms during full enhancement,

?V OUT exceeds the V SC during full enhancement, and ?Load-probe test fails.

Once in the fault management mode, GATE will always be pulled to V EE to turn off the external MOSFET and PG OOD (PGOOD ) will always be deasserted. The MAX5936A_/MAX5937A_ have automatic retry following a fault while the MAX5936L_/MAX5937L remain latched in the fault condition.

Autoretry Fault Management

(MAX5936A_/MAX5937A_)

If the MAX5936A_/MAX5937A_entered fault management due to circuit-breaker and short-circuit faults, the autoretry timer starts immediately. The timer times out in 3.5s (typ) and at the end of the timeout, the sequencer initiates a load-probe test. If this is successful, it starts a normal power-up GATE cycle.

Figure 6. MAX5936 Response to a Step Input (V OUT < 0.74V CB )2ms/div

C LOA

D = 100μF R LOAD = 100?

Figure 7. MAX5936 Response to a Step Input (V OUT > 0.74V CB )

4ms/div

40V 20V

C LOA

D = 100μF R LOAD = 20?

MAX5936/MAX5937

-48V Hot-Swap Controllers with V IN

Step Immunity and No R SENSE

______________________________________________________________________________________

Latched Fault Management (MAX5936L_/MAX5937L_)

When the MAX5936L_/MAX5937L_ enter fault manage-ment, they remain in this condition indefinitely until the power is recycled or until UVLO is brought below 1.125V for 1.5ms (typ) (when the short-circuit or circuit-breaker fault has cleared, the sequencer initiates a load-probe test). If this is successful, it starts a normal power-up GATE cycle. A manual reset circuit (Figure 8)can be used to clear the latch.

Circuit-Breaker Thresholds

The MAX5936/MAX5937 are available with 100mV,200mV, and 400mV circuit-breaker thresholds. The short-circuit voltage threshold (V SC ) is twice the circuit-breaker threshold voltage (V CB ). In the MAX5936/MAX5937, V CB and V SC are temperature-compensated (increasing with temperature) to track the normalized temperature gradient of typical power MOSFETs.

The proper circuit-breaker threshold for an application depends on the R DS(ON) of the external power MOSFET and the maximum current the load is expected to draw.To avoid false fault indication and dropping of the load,the designer must take into account the load response to voltage ripples and noise from the backplane power supply, as well as switching currents in the downstream DC-DC converter that is loading the circuit. While the circuit-breaker threshold has glitch rejection that ignores ripples and noise lasting less than 1.2ms, the short-circuit detection is designed to respond very quickly (less than 330ns) to a short circuit. V SC and V CB must be selected from the three available ranges

with an adequate margin to cover all possible ripples,noise, and system current transients.

The short-circuit and circuit-breaker voltages are sensed at V OUT , which is the drain of the power MOSFET. The R DS(ON)of the MOSFET is the current-sense resis-tance, so the total current through the load and load capacitance is the drain current of the power MOSFET.Accordingly, the voltage at V OUT as a function of MOSFET drain current is:

V OUT = I D,MOSFET x R DS(ON)

The temperature compensation of the MAX5936/MAX5937 is designed to track the R DS(ON) of the typi-cal power MOSFET. Figure 9 shows the typical normal-ized tempco of the circuit-breaker threshold along with the normalized tempco of R DS(ON) for two typical power MOSFETS. When determining the circuit-breaker threshold in an application, go to the data sheet of the power MOSFET and locate the manufacturer’s maxi-mum R DS(ON)at +25°C with a V GS of 10V. Next, find the figure presenting the tempco of normalized R DS(ON)or on-resistance vs. temperature. Because this curve is in normalized units typically with a value of 1 at +25°C,it is possible to multiply the curve by the drain voltage at +25°C and convert the curve to drain voltage. Now compare this curve to that of the MAX5936/MAX5937 normalized tempco of the circuit-breaker threshold to make a determination of the tracking error in mV between the power MOSFET [I D,MOSFET x R DS(ON)]and the MAX5936/MAX5937 over the application’s operating temperature range. If the tempco of the power MOSFET is greater than that of the MAX5936/MAX5937, then additional margin will be required in selecting the circuit-breaker and short-circuit voltages at higher temperatures as compared to +25°C. When dissipation in the power MOSFET is expected to lead to local temperature elevation relative to ambient condi-tions, then it becomes imperative that the MAX5936/MAX5937 be located as close as possible to the power MOSFET. The marginal effect of temperature differ-ences on circuit-breaker and short-circuit voltages can be estimated from a comparative plot such as Figure 9.

MAX5936LN and MAX5937LN

The MAX5936LN and MAX5937LN do not have circuit-breaker and short-circuit thresholds and these faults are ignored. For these devices PG OOD (PGOOD )asserts 1.26ms after G ATE has ramped to 90% of full enhancement. The step detection function of the MAX5936LN and MAX5937LN responds to V IN and V OUT steps with the same voltage thresholds as the MAX5936_C and MAX5937_C.

Figure 8. Resetting MAX5936L/MAX5937L after a Fault Condition Using a Push-Button Switch

M A X 5936/M A X 5937

-48V Hot-Swap Controllers with V IN Step Immunity and No R SENSE

______________________________________________________________________________________

PGOOD (PGOOD ) Open-Drain Output

The power-good outputs, PG OOD (PGOOD ), are open drain and are referenced to V OUT . They assert and latch if V OUT ramps below 72% of V CB , and with the built-in delay this occurs 1.26ms after the external MOSFET becomes fully enhanced. PG OOD (PGOOD ) deasserts any time the part enters fault management. PG OOD (PGOOD ) has a delayed response to UVLO. The GATE goes to V EE when UVLO is brought below 1.125V for 1.5ms. This turns off the power MOSFET and allows V OUT to rise depending on the RC time constant of the load. PG OOD (PGOOD ), in this situation, deasserts when V OUT rises above V CB for more than 1.4ms or above V SC , whichever occurs first (see Figure 12b).

Due to the open-drain driver, PG OOD (PGOOD )requires an external pullup resistor to GND. Due to this external pullup, PG OOD will not follow positive V IN steps as well as if it were driven by an active pullup. As a result, when PG OOD (PGOOD

) is asserted high, an apparent negative glitch appears at PGOOD (PGOOD )during a positive V IN step. This negative glitch is a result of the RC time constant of the external resistor and the PGOOD pin capacitance lagging the V IN step.It is not due to switching of the internal logic. To mini-mize this negative transient, it may be necessary to increase the pullup current and/or to add a small amount of capacitance from PGOOD (PGOOD ) to GND to compensate for the pin capacitance.

WARNING:For the MAX5936_N/MAX5937_N, PGOOD (PGOOD ) asserts 1.26ms after the power MOSFET is fully enhanced, independent of V OUT . Once the MOSFET is fully enhanced and UVLO is pulled below its respective threshold, G ATE pulls to V EE to turn off the power MOSFET and disconnect the load. When UVLO is cycled low, PG OOD (PGOOD ) is deasserted. In sum-mary, once the MOSFET is fully enhanced, the MAX5936_N/ MAX5937_N ignore V OUT and deassert PG OOD (PGOOD ) when UVLO goes low or when the power to the MAX5936_N/ MAX5937_N is fully recy-cled.

Undervoltage Lockout (UVLO)

UVLO provides an accurate means to set the turn-on volt-age level for the MAX5936/MAX5937. Use a resistor-divider network from G ND to V EE to set the desired turn-on voltage (Figure 11). UVLO has hysteresis with a rising threshold of 1.25V and a falling threshold of 1.125V.A startup delay of 220ms allows contacts and voltages to settle prior to initiating the startup sequence (Figure 12a).

Figure 9. MAX5936/MAX5937 Normalized Circuit-Breaker Threshold (V CB )

Figure 10. Circuit-Breaker Voltage Margin for High and Low Tempco Power MOSFETS

MAX5936/MAX5937

-48V Hot-Swap Controllers with V IN

Step Immunity and No R SENSE

______________________________________________________________________________________

This startup delay is from a valid UVLO condition until the start of the load-probe test. There is glitch rejection on UVLO going low, which requires that V UVLO remains below its falling threshold for 1.5ms to turn off the part (Figure 12b). Use the following formula to calculate the MAX5936/MAX59337 turn-on voltage:

Where V ON is the desired turn-on voltage of the

MAX5936/MAX5937 and V UVLO_REF,R is the 1.25V UVLO rising threshold.

Output Voltage (V OUT )

Slew-Rate Control

The V OUT slew rate controls the inrush current required to charge the load capacitor. The MAX5936/MAX5937have a default internal slew rate set for 9V/ms. The inter-

nal circuit establishing this slew rate accommodates up to about 1000pF of reverse transfer capacitance (miller capacitance) in the external power MOSFET without effecting the default slew rate. Using the default slew rate, the inrush current required to charge the load capacitance is given by:

I INRUSH (mA) = C LOAD (μF) x SR (V/ms)where SR = 9V/ms (default, typ).

Applications Information

Selecting Resistor and Capacitor

for Step Monitor

When a positive V IN step or ramp occurs, the V IN increase results in a voltage rise at both STEP_MON and V OUT relative to V EE . When the voltage at STEP_MON is above STEP TH the MAX5936/MAX5937block short-circuit and circuit-breaker faults. During this STEP_MON high condition, if V OUT rises above V SC , the MAX5936/MAX5937 immediately and very rapidly pull GATE to V EE . This turns off the power MOSFET to avoid inrush current spiking. G ATE is held low for 350μs.About 1ms after the start of G ATE pulldown, the MAX5936/MAX5937 begin to ramp GATE up to turn on the MOSFET in a controlled manner, which results in ramping V OUT down to the new supply level (see the GATE Cycles section in Appendix A ).

Figure 11. Setting the MAX5936/MAX5937 Turn-On Voltage

Figure 12. UVLO Timing Diagram

M A X 5936/M A X 5937

-48V Hot-Swap Controllers with V IN Step Immunity and No R SENSE 14

______________________________________________________________________________________

This occurs with the least possible disturbance to V OUT ,although during the brief period that the MOSFET is off,the voltage across the load droops slightly depending on the load current and load storage capacitance.PG OOD remains asserted throughout the V IN step event.

The objective in selecting the resistor and capacitor for the step monitor function is to ensure that the V IN steps of all anticipated slopes and magnitudes will be proper-ly detected and blocked, which otherwise would result in a circuit-breaker or short-circuit fault. The following is a brief analysis for finding the resistor and capacitor.For a more complete analysis, see Appendix B .

Figure 13 is a functional diagram exhibiting the elements of the MAX5936/MAX5937 involved in the step immunity function. This block diagram shows the parallel relationship between V OUT and V STEP_MON .Each has an I*R component establishing the DC level prior to a step. While it is referred to as a V IN step, it is the dynamic response to a finite voltage ramp that is of interest.

Given a positive V IN ramp with a ramp rate of dV/dt, the approximate response of V OUT to V IN is:

V OUT (t) = (dV/dt) x τC x (1-e (-t / τL ,eqv) )

+ R DS(ON) x I LOAD

where τC = C LOAD x R DS(ON) and τL ,eqv is the equiva-lent time constant of the load that must be found empir-ically (see Appendix B ).

Similarly, the response of STEP_MON to a V IN ramp is:V STEP_MON (t) = (dV/dt) x τSTEP x (1-e (-t / τSTEP) ) + 10μA

x R STEP

where τSTEP = R STEP_MON x C STEP_MON .

For proper step detection, V STEP_MON must exceed STEP TH prior to V OUT reaching V SC or within 1.4ms of V OUT reaching V CB (overall V IN ramp rates anticipated in the application). V STEP_MON must be set below STEP TH with adequate margin, ?V STEP_MON , to accommodate the tolerance of both I STEP_OS (±8%) and R STEP_MON .R STEP_MON is typically set to 100k ?which gives a ?V STEP_MON for a worst-case high of 0.36V.

Figure 13. MAX5936/MAX5937 Step Immunity Functional Diagram

MAX5936/MAX5937

-48V Hot-Swap Controllers with V IN

Step Immunity and No R SENSE

______________________________________________________________________________________

The margin of V OUT with respect to V SC and V CB was set when V SC and V CB were selected from the three avail-able ranges. This margin may be lower at one of the tem-perature extremes and if so, that value should be used in the following discussion. These margins will be called ?V CB and ?V SC and they represent the minimum V OUT excursion required to trip the respective fault.

To set τSTEP to block all V CB and V SC faults for any ramp rate, find the ratio of ?V STEP_MON to ?V CB and choose τSTEP so:

τSTEP = 1.2 x τC x ?V STEP_MON / ?V CB

And since R STEP_MON = 100k ?. This results in C STEP_MON = τSTEP / 100k ?.

After the first-pass component selection, if sufficient timing margin exists (see Appendix B ), it is possible but not necessary to lower R STEP_MON below 100k ?to reduce the sensitivity of STEP_MON to V IN noise.

Appendix B gives a more complete analysis and dis-cussion of the step monitor function. It provides meth-ods for the characterization of the load response to a V IN ramp and graphical verification of the step monitor timing margins for a set of design parameters.

Selecting the PGOOD (PGOOD )

Pullup Resistor

Due to the open-drain driver, PGOOD (PGOOD ) requires an external pullup resistor to GND. This resistor should be selected to minimize the current load while PG OOD (PGOOD ) is low. The PGOOD output specification for V OL is 0.4V at 1mA. As described in the Detailed Description ,the external pullup interferes with the ability of PG OOD (PGOOD ) to follow positive V IN steps as well as if it were driven by an active pullup. When PG OOD (PGOOD ) is asserted high, an apparent negative glitch appears at PG OOD during a positive V IN step. To minimize this negative transient it may be necessary to increase the pullup current and/or to add a small amount of capaci-tance from PGOOD (PGOOD ) to GND to compensate for the pin capacitance.

Setting the Test Current Level for

Load-Probe Test

The load-probe test is a current test of the load that avoids turning on the power MOSFET. The MAX5936/MAX5937 have an internal switch (Q1 in Figure 14) that pulls current through the load and through an external current-limiting resistor, R LP . During the test, this switch is pulsed on for up to 220ms (typ). Current is pulled through the load, which should charge up the load capacitance unless there is a short. If the voltage across the load exceeds 200mV, the test is truncated and normal power-up is allowed to proceed. If the voltage across the load does not reach 200mV in the 220ms period that the

current is on, the load is assumed to be shorted and the current to the load from the LP pin is shut off. The MAX5936A_/MAX5937A_ time out for 16 x t LP then retry the load-probe test. The MAX5936L_/MAX5937L_ latch the fault condition indefinitely until the UVLO is brought below 1.125V for 1.5ms or the power is recycled.

In the application, the current-limiting resistor should be selected to minimize the current pulled through the load while guaranteeing that it charges the maximum expected load capacitance to 220mV in 80ms. These parameters are the maximum load-probe test voltage and the mini-mum load-probe current pulse period, respectively. The maximum current possible is 1A, which is adequate to test a load capacitance as large as 170,000μF over the typical telecom operating voltage range.

I TEST (A) = C LOAD,MAX (F) x 220mV / 80ms

Since the minimum intended V IN for the application results in the lowest I TEST , during the load-probe test,this V IN,MIN should be used to set the R LP . This voltage will likely be near V ON,FALLING or V OFF for the applica-tion.

R TEST (?) = V IN,MIN / I TEST = V IN,MIN x 80ms /

(C LOAD(MAX) x 220mV)

Example: V IN operating range = 36V to 72V, C LOAD =10,000μF. First, find the R TEST, which will guarantee a successful test of the load.

R LP = 36V x 80ms / (10,000μF x 220mV) = 1,309??

1.30k ?±1%

Next, evaluate the R LP at the maximum operating volt-age to verify that it will not exceed the 1A current limit for the load-probe test:

I TEST,MAX = V IN,MAX / R LP = 72V / 1.30k ?= 55.4mA If the C LOAD(MAX)is increased to 170,000μF, the test current will approach the limit. In this case, R TEST will be a much lower value and must include the internal switch resistance. To find the external series resistor value that will guarantee a successful test at the lowest supply voltage, the maximum value for the load-probe switch on-resistance of 11?should be used:

R LP,TOT = 36V x 80ms / (170,000μF x 220mV)

= 77?= 11?+ R LP

R LP = 77?- 11?= 66??66.5?±1%Again R LP must be evaluated at the maximum operat-ing voltage to verify that it will not exceed the 1A cur-rent limit for the load-probe test. In this case, the minimum value for the load-probe switch on-resistance of 6?should be used:

I TEST,MAX = V IN,MAX / R LP,TOT = 72V / (66.5?+ 6?)

= 993mA

M A X 5936/M A X 5937

-48V Hot-Swap Controllers with V IN Step Immunity and No R SENSE 16______________________________________________________________________________________

Adjusting the V OUT Slew Rate

The default slew rate is set internally for 9V/ms. The slew rate can be reduced by placing an external capacitor from the drain of the power MOSFET to the G ATE output of the MAX5936/MAX5937. Figure 15shows a graph of Slew Rate vs. C SLEW . This graph shows that for C SLEW < 4700pF there is very little effect to the addition of external slew-rate control capaci-tance. This is intended so the G ATE output can drive large MOSFETs with significant gate capacitance and still achieve the default slew rate. To select a slew-rate control capacitor, go into the graph with the desired slew rate and find the value of the miller capacitance.When C SLEW > 4700pF, SR and C SLEW are inversely related. G iven the desired slew rate, the required C SLEW is found as follows:

C SLEW (nF) = 23 / SR (V/ms)

From the data sheet of the power MOSFET find the reverse transfer capacitance (gate-to-drain capacitance)above 10V. If the reverse transfer capacitance of the external power MOSFET is 5% or more of C SLEW , then it should be subtracted from C SLEW in the equation above.Figure 16 gives an example of the external circuit for controlling slew rate. Depending on the parasitics asso-

ciated with the selected power MOSFET, the addition of C SLEW may lead to oscillation while the MOSFET and GATE control are in the linear range. If this is an issue, an external resistor, R GATE , in series with the gate of the MOSFET is recommended to prevent possible oscilla-tion. It should be as small as possible, e.g., 5?to 10?, to avoid impacting the MOSFET turn-off performance of the MAX5936/MAX5937.

Layout Guidelines

To benefit from the temperature compensation designed into the MAX5936/MAX5937, the part should be placed as close as possible to the power MOSFET that it is con-trolling. The V EE pin of the MAX5936/ MAX5937 should be placed close to the source pin of the power MOSFET and they should share a wide trace. A common top layer plane would service both the thermal and electrical requirements. The load-probe current must be taken into account. If this current is high, the layout traces and cur-rent-limiting resistor must be sized appropriately. Stray inductance must be minimized in the traces of the over-all layout of the hot-swap controller, the power MOSFET,and the load capacitor. Starting from the board con-tacts, all high-current traces should be short, wide, and direct. The potentially high pulse current pins of the MAX5936/MAX5937 are GATE (when pulling GATE low),

Figure 14. Load Probe Functional Diagram

MAX5936/MAX5937

-48V Hot-Swap Controllers with V IN

Step Immunity and No R SENSE

______________________________________________________________________________________17

load-probe, and V EE . Because of the nature of the hot-swap requirement, no decoupling capacitor is recom-mended for the MAX5936/MAX5937. Because there is no decoupling capacitor, stray inductance can result in excessive ringing at the G ND pin during power-up or during very rapid V IN steps. This should be examined in every application design since ringing at the G ND pin may exceed the absolute maximum supply rating for the part.

Input Transient Protection

During hot plug-in/unplug and fast V IN steps, stray inductance in the power path can cause voltage ring-ing above the normal input DC value, which may exceed the absolute maximum supply rating. An input transient such as that caused by lightning can also put a severe transient peak voltage on the input rail. The following techniques are recommended to reduce the effect of transients:

1)Minimize stray inductance in the power path using

wide traces and minimize loop area including the power traces and the return ground path.

2)Add a high-frequency (ceramic) bypass capacitor

on the backplane as close as possible to the plug-in connector (Figure 17).3)Add a 1k ?resistor in series with the MAX5936/

MAX5937’s G ND pin and a 0.1μF capacitor from GND to V EE to limit transient current going into this pin.

Appendix A

GATE Cycles

The power-up GATE cycle and the step GATE cycle are quite similar but have distinct differences. Understanding these differences may clarify application issues.

GATE Cycle During Power-Up

The power-up G ATE cycle occurs during the initial power-up of the MAX5936/MAX5937 and the associat-ed power MOSFET and load. The power-up G ATE cycle can result in full enhancement or in a fault (all voltages are relative to V EE ).

Power-Up to Full Enhancement:

1)At the beginning of the power-up sequence to the

start of the power-up GATE cycle, the GATE is held at V EE . Following a successful completion of the load-probe test, G ATE is held at V EE for an addi-tional 350μs and then is allowed to float for 650μs.At this point, the G ATE begins to ramp with 52μA charging the gate of the power MOSFET. [G ATE turn-on]2)When G ATE reaches the gate threshold voltage of

the power MOSFET, V OUT begins to ramp down toward V EE . [V OUT ramp]3)When V OUT ramps below 72% V CB , the G ATE is

rapidly pulled to full enhancement and the power-up G ATE cycle is complete. 1.26ms after G ATE is pulled to full enhancement, PGOOD will assert. [Full enhancement]

Figure 15. MAX5936/MAX5937 Slew Rate vs. C SLEW

Figure 16. Adjusting the MAX5936/MAX5937 Slew Rate

M A X 5936/M A X 5937

-48V Hot-Swap Controllers with V IN Step Immunity and No R SENSE 18______________________________________________________________________________________

Power-Up to Fault Management:

1)Same as step 1 above. [GATE turn-on]2)Same as step 2 above. [V OUT ramp]

3)G ATE ramps to 90% of full enhancement while

V OUT remains above 72% V CB , at which point the G ATE is rapidly pulled to V EE and fault manage-ment is initiated. [Fault management]GATE Cycle During V IN Step

A step G ATE cycle occurs only after a successful power-up GATE cycle to full enhancement occurs and as a result of a positive V IN step (all voltages are relative to V EE ).

Step to Full Enhancement:

1) A V IN step occurs resulting in STEP_MON rising

above STEP TH before V OUT rises above V SC . [Step detection]2)After a step is detected, V OUT rises above V SC in

response to the step. When V OUT rises above V SC ,GATE is immediately pulled to V EE , rapidly turning off the power MOSFET. GATE is held at V EE for 350μs to dampen any ringing. Once G ATE is pulled to V EE ,the gate cycle has begun and STEP_MON can safely drop below STEP TH and successfully complete a step GATE cycle to full enhancement without initiat-ing fault management. [GATE pulldown]3)Following the 350μs of G ATE pulldown, G ATE is

allowed to float for 650μs. At this point, the G ATE

begins to ramp with 52μA charging the gate of the power MOSFET. [GATE turn-on]

4)When G ATE reaches the gate threshold voltage of

the power MOSFET, V OUT begins to ramp down toward the new lower V EE . In the interval where GATE is below the MOSFET threshold, the MOSFET is off and V OUT will droop depending on the RC time constant of the load. [V OUT ramp]5)When V OUT ramps below 72% V CB , the GATE pulls

rapidly to full enhancement and the step G ATE cycle is complete. If STEP_MON remains above STEP TH when G ATE has ramped to 90% of full enhancement and V OUT remains above 72% of V CB , GATE remains at 90% and will not be pulled to full enhancement. In this condition, if V OUT drops below 72% of V CB before STEP_MON drops below STEP TH , GATE is rapidly pulled to full enhancement and the step G ATE cycle is complete. PG OOD remains asserted throughout the step GATE cycle.[Full enhancement]Step to Fault Management:

1)Same as step 1 above. [Step detection]2)Same as step 2 above. [GATE pulldown]3)Same as step 3 above. [GATE turn-on]4)Same as step 4 above. [VOUT ramp]

5)If STEP_MON is below STEP TH when GATE ramps

to 90% of full enhancement and V OUT remains above 72% V CB,G ATE is rapidly pulled to V EE .Fault management is initiated and PG OOD is de-asserted. If STEP_MON is above STEP TH when GATE ramps to 90% of full enhancement and V OUT remains above 72% of V CB , GATE remains at 90%.It will not be pulled to full enhancement nor will it be pulled to V EE . In this condition, if V OUT drops below 72% of V CB before STEP_MON drops below STEP TH , GATE is rapidly pulled to full enhancement and a fault is avoided. Conversely, if STEP_MON drops below STEP TH first, the G ATE is rapidly pulled to V EE , fault management is initiated, and PGOOD is deasserted. [Fault management]It should be emphasized that while STEP_MON remains above STEP TH the current fault management is blocked. During this time it is possible for there to be multiple events involving V OUT rising above V SC then those falling below 75% V CB . In each of these events,when V OUT rises above V SC , a full GATE cycle is initiat-ed where GATE is first pulled low then allowed to ramp up. Then finally, when V OUT conditions are met, it will be fully enhanced.

Figure 17. Protecting the MAX5936/MAX5937 Input from High-Voltage Transients

MAX5936/MAX5937

-48V Hot-Swap Controllers with V IN

Step Immunity and No R SENSE

______________________________________________________________________________________19

GATE Output

GATE is a complex output structure and its condition at any moment is dependent on various timing sequences in response to multiple inputs. A diode to V EE prevents neg-ative excursions. For positive excursions, the states are:1)Power-off with 2V clamp.2)10?pulldown to V EE.

a.Continuous during startup delay and during

fault conditions.b.Pulsed following detected step or OV

condition.3)Floating with 15V clamp. [Prior to GATE ramp]4)47μA current source with 15V clamp. [GATE ramp]5)Pullup to internal 10V supply with 15V clamp. [Full

enhancement]

Appendix B

Step Monitor Component

Selection Analysis

As mentioned previously in the Selecting Resistor and Capacitor for Step Monitor section, the AC response from V IN to V OUT is dependent on the parasitics of the load. This is especially true for the load capacitor in conjunction with the power MOSFET’s R DS(ON). The load capacitor (with parasitic ESR and LSR) and the power MOSFET’s R DS(ON)can be modeled as a heavily damped second-order system. As such, this system functions as a bandpass filter from V IN to V OUT limiting the ability of V OUT to follow the V IN ramp. STEP_MON lags the V IN ramp with a first-order RC response, while V OUT lags with an overdamped second-order response.

Given a positive V IN ramp with ramp rate of dV/dt, the approximate response of V OUT to V IN is:

V OUT (t) = (dV/dt) x τC x (1-e (-t / τL,eqv) )

+ R DS(ON) x I LOAD (Equation 1)

where τC = C LOAD x R DS(ON).

Equation 1 is a simplification for the overdamped sec-ond-order response of the load to a ramp input, τC =C LOAD x R DS(ON), and corresponds to the ability of the load capacitor to transfer dV/dt current to the fully enhanced power MOSFET’s R DS(ON). The equivalent time constant of the load (τL,eqv ) accounts for the para-sitic series inductance and resistance of the capacitor and board interconnect. Determine τL,eqv empirically with a few tests to characterize the load dynamic response to V IN ramps.

Similarly, the response of STEP_MON to a V IN ramp is:

V STEP_MON (t) = (dV/dt) x τSTEP x (1-e (-t / τSTEP) )

+ 10μA x R STEP_MON (Equation 2)

where τSTEP = R STEP_MON x C STEP_MON.

For proper step detection, V STEP_MON must exceed STEP TH prior to V OUT reaching V SC or within 1.4ms of V OUT reaching V CB (or overall V IN ramp rates anticipat-ed in the application). It is impossible to give a fixed set of design guidelines that rigidly apply over the wide array of applications that use the MAX5936/MAX5937. There are, however, limiting conditions and recommendations that should be observed.

One limiting condition that must be observed is to ensure that the STEP_MON time constant, τSTEP , is not so low that at the lowest ramp rate, the anticipated STEP TH can-not be obtained. The product (dV/dt) x τSTEP =τSTEP_MON,MAX , is the maximum differential voltage at STEP_MON if the V IN ramp were to continue indefinitely.A related condition is setting the STEP_MON voltage below STEP TH with adequate margin, ?V STEP_MON , to accommodate the tolerance of both I STEP_OS (±8%) and R STEP_MON . In determining τSTEP_MON , use the 9.2μA limit to ensure sufficient margin with worst-case I STEP_OS .The margin of V OUT (with respect to V SC and V CB ) is set when V SC and V CB were selected from the three available ranges. This margin may be lower at one of the temperature extremes and if so, that value should be used in the following discussion. These margins will be called ?V CB and ?V SC and they represent the mini-mum V OUT excursion required to trip the respective fault. R STEP_MON is typically set to 100k ?±1%. This gives a ?V STEP_MON of 0.25V, a worst-case low of 0.16V, and a worst-case high of 0.37V. In finding τSTEP in the equation below, use ?V STEP_MON = 0.37V to ensure sufficient margin with worst-case I STEP_OS .

To set τSTEP to block all V CB and V SC faults for any ramp rate, find the ratio of ?V STEP_MON to ?V CB and choose τSTEP so:

τSTEP = 1.2 x τC x ?V STEP_MON / ?V CB

and since R STEP_MON = 100k ?:

C STEP_MON = τSTEP / R STEP_MON = τSTEP / 100k ?After the first-pass component selection, if sufficient timing margin exists, it is possible but not necessary to lower R STEP below 100k ?to reduce the sensitivity of STEP_MON to V IN noise.

M A X 5936/M A X 5937

-48V Hot-Swap Controllers with V IN Step Immunity and No R SENSE 20

___________________________________________________

Verification of the Step

Monitor Timing

It is prudent to verify conclusively that all circuit-breaker and short-circuit faults will be blocked for all ramp rates. To do this, some form of graphical analysis is recommended but first, find the value of τL,eqv of the load by a series of ramp tests as indicated earlier.These tests include evaluating the load with a series of V IN ramps of increasing ramp rates and monitoring the rate of V OUT rise during the ramp. Each V IN ramp should have a constant slope. The V OUT response data must be taken only during the positive ramp. Data taken after V IN has leveled off at the new higher value must not be used.

Figure 18 shows the load in parallel with the load capacitor, C LOAD , and the parallel connection in series with the power MOSFET, which is fully enhanced with V

GS = 10V. The objective is to determine τL,eqv from the V OUT response.

Figure 19 shows the general response of V OUT to a V IN ramp over time t. Equation 1 gives the response of V OUT to a ramp of dV/dt. The product (dV/dt) x τC =?V OUT (max) or the maximum V OUT voltage differential if the V IN ramp were to continue indefinitely. The parame-ter of interest is ?V OUT due to the ramp dV/dt, thus it is necessary to subtract the DC shift in V OUT due to the load resistance. For some loads, which are relatively independent of supply voltage, this may be insignificant.

V OUT (t) = V OUT (t) - R DS(ON) x I LOAD

where I LOAD is a function of the V OUT level that should be determined separately with DC tests.

At any time (t) the ?V OUT fraction of ?V OUT (max) is:

?V OUT (t) / [(dV/dt) x τC ] = (1-e (-t / τL,eqv))

If V OUT (t) is measured at time t, then the equivalent time constant of the load is found from:

τL,eqv = -t / ln(1 - ?V OUT / [(dV/dt) x τC ])

As mentioned earlier, several measurements of ?V OUT at times t1, t2, t3, and t4 should be made during the ramp. Each of these may result in slightly different val-ues of τL,eqv and all values should then be averaged.In making the measurements, the V IN ramp duration should be such that ?V OUT reaches 2 or 3 times the selected ?V SC . The ramp tests should include three ramp rates: ?V SC / τC , 2 x ?V SC / τC and 4 x ?V SC / τC .The values of τL,eqv may vary over the range of slew rates due to measurement error, nonlinear dynamics in the load, and due to the fact that Equation 1 is a simpli-fication from a higher order dynamic system. The resulting range of τL,eqv values should be used to vali-date the performance of the final design.

Having τC , τL,eqv , R STEP , and C STEP in a graphical analysis using Equation 1 and Equation 2 can verify the step monitor function by displaying the relative timing of t CB , t STEP , and t SC , which are the times when V CB ,V STEP_MON ,and V SC voltage thresholds are exceeded.A simple spreadsheet for this purpose can be supplied by Maxim upon request. Figures 20, 21, and 22 graphi-cally verify a particular solution over 3 decades of V IN ramp rates. In addition, Figure 22 verifies that this solu-tion will block all circuit-breaker and short-circuit faults for even the lowest V IN ramp that will cause V OUT to exceed V CB .

Figure 18. V IN Ramp Test of Load Figure 19. General Response of V OUT to a V IN Ramp