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MSP430FR5738IRGET;MSP430FR5738IRGER;中文规格书,Datasheet资料

MSP430FR573x

MSP430FR572x

https://www.wendangku.net/doc/c215954868.html, SLAS639D–JULY2011–REVISED AUGUST2012

MIXED SIGNAL MICROCONTROLLER

FEATURES

?Embedded Microcontroller–eUSCI_A0and eUSCI_A1Support:–16-Bit RISC Architecture up to24-MHz–UART With Automatic Baud-Rate Clock Detection

–Wide Supply Voltage Range(2V to3.6V)–IrDA Encode and Decode

–-40°C to85°C Operation–SPI at Rates up to10Mbps

?Optimized Ultra-Low Power Modes–eUSCI_B0Supports:

–I2C With Multi-Slave Addressing

Consumption

Mode–SPI at Rates up to10Mbps

(Typical)

–Hardware UART or I2C Bootstrap Loader Active Mode81.4μA/MHz

(BSL)

Standby(LPM3With VLO) 6.3μA

?Power Management System

Real-Time Clock(LPM3.5With Crystal) 1.5μA

Shutdown(LPM4.5)0.32μA–Fully Integrated LDO

–Supply Voltage Supervisor for Core and ?Ultra-Low Power Ferroelectric RAM

Supply Voltages With Reset Capability –Up to16KB Nonvolatile Memory

–Always-On Zero-Power Brownout Detection –Ultra-Low Power Writes

–Serial On-Board Programming With No –Fast Write at125ns per Word(16KB in1

External Voltage Needed ms)

?Flexible Clock System

–Built in Error Coding and Correction(ECC)

–Fixed-Frequency DCO With Six Selectable and Memory Protection Unit(MPU)

Factory-Trimmed Frequencies(Device –Universal Memory=Program+Data+

Dependent)

Storage

–Low-Power Low-Frequency Internal Clock –1015Write Cycle Endurance

Source(VLO)

–Radiation Resistant and Nonmagnetic

–32-kHz Crystals(LFXT)

?Intelligent Digital Peripherals

–High-Frequency Crystals(HFXT)–32-Bit Hardware Multiplier(MPY)

?Development Tools and Software –Three-Channel Internal DMA

–Free Professional Development –Real-Time Clock With Calendar and Alarm Environments(IAR,CCS,GCC) Functions

–Low-Cost Full-Featured Kit(MSP-–Five16-Bit Timers With up to Three EXP430FR5739)

Capture/Compare

–Full Development Kit(MSP-FET430U40A)–16-Bit Cyclic Redundancy Checker(CRC)

–Target Board(MSP-TS430RHA40A)

?High-Performance Analog

?Family Members

–16-Channel Analog Comparator With

–20Different Variants and5Available Voltage Reference and Programmable

Packages Summarized in Table1and Hysteresis

Table2

–14-Channel10-Bit Analog-to-Digital

–For Complete Module Descriptions,See the Converter(ADC)With Internal Reference

MSP430FR57xx Family User's Guide and Sample-and-Hold

(SLAU272)

–200ksps at100-μA Consumption

?Enhanced Serial Communication

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

UNLESS OTHERWISE NOTED this document contains Copyright?2011–2012,Texas Instruments Incorporated PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

MSP430FR573x

MSP430FR572x

SLAS639D–JULY2011–REVISED https://www.wendangku.net/doc/c215954868.html,

CAUTION These products use FRAM nonvolatile memory technology.FRAM retention is sensitive to extreme temperatures,such as those experienced during reflow or hand soldering.See Absolute Maximum Ratings for more information.

CAUTION System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturb of data or code memory.See the application report MSP430?System-Level ESD Considerations

(SLAA530)for more information.

DESCRIPTION

The Texas Instruments MSP430FR57xx family of ultralow-power microcontrollers consists of multiple devices featuring embedded FRAM nonvolatile memory,ultralow power16-bit MSP430CPU,and different peripherals targeted for various applications.The architecture,FRAM,and peripherals,combined with seven low-power modes,are optimized to achieve extended battery life in portable and wireless sensing applications.FRAM is a new nonvolatile memory that combines the speed,flexibility,and endurance of SRAM with the stability and reliability of flash,all at lower total power consumption.Peripherals include10-bit A/D converter,16-channel comparator with voltage reference generation and hysteresis capabilities,three enhanced serial channels capable of I2C,SPI,or UART protocols,internal DMA,hardware multiplier,real-time clock,five16-bit timers,and more.The family members that are available are summarized in Table1.

Table1.Family Members

eUSCI

System Channel

FRAM SRAM Channel Device Clock ADC10_B Comp_D Timer_A(1)Timer_B(2)I/O Package

(KB)(KB)B:

(MHz)UART,

SPI,I2C

IrDA,SPI

32RHA

12ext,

MSP430FR57391612416ch.3,33,3,321

2int ch.30DA

6ext,2int

10ch.17RGE

ch.

8ext,2int

MSP430FR57381612412ch.3,331121PW

ch.

5ext,2int

9ch.16YFF(3)

ch.

32RHA MSP430FR57371612416ch.3,33,3,321

30DA

10ch.17RGE MSP430FR57361612412ch.3,331121PW

9ch.16YFF(3)

32RHA

12ext,

MSP430FR5735812416ch.3,33,3,321

2int ch.30DA

6ext,2int

10ch.17RGE

ch.

MSP430FR573481243,3311

8ext,2int

12ch.21PW

ch.

32RHA MSP430FR5733812416ch.3,33,3,321

30DA

10ch.17RGE MSP430FR573281243,3311

12ch.21PW

32RHA

12ext,

MSP430FR5731412416ch.3,33,3,321

2int ch.30DA

(1)Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM

output generators available.For example,a number sequence of3,5would represent two instantiations of Timer_A,the first

instantiation having3and the second instantiation having5capture/compare registers and PWM output generators,respectively.

(2)Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM

output generators available.For example,a number sequence of3,5would represent two instantiations of Timer_B,the first

instantiation having3and the second instantiation having5capture/compare registers and PWM output generators,respectively.

(3)Product Preview

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MSP430FR573x

MSP430FR572x https://www.wendangku.net/doc/c215954868.html, SLAS639D–JULY2011–REVISED AUGUST2012

Table1.Family Members(continued)

eUSCI

System Channel

FRAM SRAM Channel Device Clock ADC10_B Comp_D Timer_A(1)Timer_B(2)I/O Package

(KB)(KB)B:

(MHz)UART,

SPI,I2C

IrDA,SPI

6ext,2int

10ch.17RGE

ch.

8ext,2int

MSP430FR5730412412ch.3,331121PW

ch.

5ext,2int

9ch.16YFF(3)

ch.

32RHA

12ext,

MSP430FR5729161816ch.3,33,3,321

2int ch.30DA

6ext,2int

10ch.17RGE

ch.

MSP430FR572816183,3311

8ext,2int

12ch.21PW

ch.

32RHA MSP430FR5727161816ch.3,33,3,321

30DA

10ch.17RGE MSP430FR572616183,3311

12ch.21PW

32RHA

12ext,

MSP430FR572581816ch.3,33,3,321

2int ch.30DA

6ext,2int

10ch.17RGE

ch.

MSP430FR57248183,3311

8ext,2int

12ch.21PW

ch.

32RHA MSP430FR572381816ch.3,33,3,321

30DA

10ch.17RGE MSP430FR57228183,3311

12ch.21PW

32RHA

12ext,

MSP430FR572141816ch.3,33,3,321

2int ch.30DA

6ext,2int

10ch.17RGE

ch.

MSP430FR57204183,3311

8ext,2int

12ch.21PW

ch.

MSP430FR573x

MSP430FR572x

SLAS639D–JULY2011–REVISED https://www.wendangku.net/doc/c215954868.html,

Table2.Ordering Information(1)

PACKAGED DEVICES(2)

PLASTIC40-PIN PLASTIC24-PIN PLASTIC38-PIN PLASTIC28-PIN PLASTIC25-BALL T A

VQFN VQFN TSSOP TSSOP DSBGA

(RHA)(RGE)(DA)(PW)(YFF)(3) MSP430FR5721IRHA MSP430FR5720IRGE MSP430FR5721IDA MSP430FR5720IPW MSP430FR5730IYFF(3)

MSP430FR5723IRHA MSP430FR5722IRGE MSP430FR5723IDA MSP430FR5722IPW MSP430FR5736IYFF(3)

MSP430FR5725IRHA MSP430FR5724IRGE MSP430FR5725IDA MSP430FR5724IPW MSP430FR5738IYFF(3)

MSP430FR5727IRHA MSP430FR5726IRGE MSP430FR5727IDA MSP430FR5726IPW

MSP430FR5729IRHA MSP430FR5728IRGE MSP430FR5729IDA MSP430FR5728IPW

–40°C to

85°C MSP430FR5731IRHA MSP430FR5730IRGE MSP430FR5731IDA MSP430FR5730IPW

MSP430FR5733IRHA MSP430FR5732IRGE MSP430FR5733IDA MSP430FR5732IPW

MSP430FR5735IRHA MSP430FR5734IRGE MSP430FR5735IDA MSP430FR5734IPW

MSP430FR5737IRHA MSP430FR5736IRGE MSP430FR5737IDA MSP430FR5736IPW

MSP430FR5739IRHA MSP430FR5738IRGE MSP430FR5739IDA MSP430FR5738IPW

(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI

web site at https://www.wendangku.net/doc/c215954868.html,.

(2)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at

https://www.wendangku.net/doc/c215954868.html,/packaging.

(3)Product Preview

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RST/NMI/SBWTDIO PA PB

MSP430FR573x

MSP430FR572x

https://www.wendangku.net/doc/c215954868.html, SLAS639D–JULY2011–REVISED AUGUST2012 Functional Block Diagram–

MSP430FR5721IRHA,MSP430FR5725IRHA,MSP430FR5729IRHA,

MSP430FR5731IRHA,MSP430FR5735IRHA,MSP430FR5739IRHA

Functional Block Diagram–

MSP430FR5723IRHA,MSP430FR5727IRHA,

MSP430FR5733IRHA,MSP430FR5737IRHA

2223242526272829P2.2/TB2.2/UCB0CLK/TB1.0

P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK

TEST/SBWTCK

P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0

P3.4/TB1.1/TB2CLK/SMCLK P3.5/TB1.2/CDOUT

P3.6/TB2.1/TB1CLK RST/NMI/SBWTDIO PJ.0/TDO/TB0OUTH/SMCLK/CD631

P2.3/TA0.0/UCA1STE/A6*/CD10P2.4/TA1.0/UCA1CLK/A7*/CD11AVCC

PJ.5/XOUT

PJ.4/XIN

AVSS P2.7P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*

8765432P1.3/TA1.2/UCB0STE/A3*/CD3P3.3/A15*/CD15

P3.2/A14*/CD14P3.1/A13*/CD13P3.0/A12*/CD12P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2

P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*

VCORE

12P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0P2.6/TB1.0/UCA1RXD/UCA1SOMI P2.5/TB0.0/UCA1TXD/UCA1SIMO P4.1

P4.0/TB2.0

DVCC DVSS

RHA PACKAGE (TOP VIEW)

P1.4/TB0.1/UCA0STE/A4*/CD4P1.5/TB0.2/UCA0CLK/A5*/CD5

MSP430FR5721MSP430FR5723MSP430FR5725MSP430FR5727MSP430FR5729MSP430FR5731MSP430FR5733MSP430FR5735MSP430FR5737MSP430FR5739

PJ.3/TCK/CD9

PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7

PJ.2/TMS/TB2OUTH/ACLK/CD8

P3.7/TB2.2

AVSS *Not available on MSP430FR5737, MSP430FR5733, MSP430FR5727, MSP430FR5723

Note: Power Pad connection to V recommended.

SS MSP430FR573x MSP430FR572x

SLAS639D –JULY 2011–REVISED AUGUST 2012

https://www.wendangku.net/doc/c215954868.html,

Pin Designation –

MSP430FR5721IRHA,MSP430FR5723IRHA,MSP430FR5725IRHA,MSP430FR5727IRHA,MSP430FR5729IRHA,

MSP430FR5731IRHA,MSP430FR5733IRHA,MSP430FR5735IRHA,MSP430FR5737IRHA,MSP430FR5739IRHA

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RST/NMI/SBWTDIO PA PB

MSP430FR573x

MSP430FR572x

https://www.wendangku.net/doc/c215954868.html, SLAS639D–JULY2011–REVISED AUGUST2012 Functional Block Diagram–

MSP430FR5721IDA,MSP430FR5725IDA,MSP430FR5729IDA,

MSP430FR5731IDA,MSP430FR5735IDA,MSP430FR5739IDA

Functional Block Diagram–

MSP430FR5723IDA,MSP430FR5727IDA,

MSP430FR5733IDA,MSP430FR5737IDA

DA PACKAGE (TOP VIEW)

198765

43210

1119

181716141213153830

3334

35363729

2820

21222325

2624AVCC

AVSS PJ.5/XOUT

PJ.4/XIN P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*P1.3/TA1.2/UCB0STE/A3*/CD3P3.3/A15*/CD15

P3.2/A14*/CD14P3.1/A13*/CD13P3.0/A12*/CD12P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2

P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*

P1.4/TB0.1/UCA0STE/A4*/CD4P1.5/TB0.2/UCA0CLK/A5*/CD5PJ.0/TDO/TB0OUTH/SMCLK/CD6PJ.3/TCK/CD9

PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7

PJ.2/TMS/TB2OUTH/ACLK/CD8

P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0P2.6/TB1.0/UCA1RXD/UCA1SOMI

P2.5/TB0.0/UCA1TXD/UCA1SIMO

P2.2/TB2.2/UCB0CLK/TB1.0

P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK TEST/SBWTCK

P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0

P3.4/TB1.1/TB2CLK/SMCLK P3.5/TB1.2/CDOUT

P3.6/TB2.1/TB1CLK RST/NMI/SBWTDIO AVSS

P2.3/TA0.0/UCA1STE/A6*/CD10P2.7VCORE

DVCC DVSS P3.7/TB2.2

P2.4/TA1.0/UCA1CLK/A7*/CD11MSP430FR5721MSP430FR5723MSP430FR5725

MSP430FR5727MSP430FR5729MSP430FR5731MSP430FR5733MSP430FR5735MSP430FR5737MSP430FR5739*Not available on MSP430FR5737, MSP430FR5733, MSP430FR5727, MSP430FR5723

MSP430FR573x MSP430FR572x

SLAS639D –JULY 2011–REVISED AUGUST 2012

https://www.wendangku.net/doc/c215954868.html,

Pin Designation –

MSP430FR5721IDA,MSP430FR5723IDA,MSP430FR5725IDA,MSP430FR5727IDA,MSP430FR5729IDA,

MSP430FR5731IDA,MSP430FR5733IDA,MSP430FR5735IDA,MSP430FR5737IDA,MSP430FR5739IDA

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RST/NMI/SBWTDIO PA

MSP430FR573x

MSP430FR572x

https://www.wendangku.net/doc/c215954868.html, SLAS639D–JULY2011–REVISED AUGUST2012 Functional Block Diagram–

MSP430FR5720IRGE,MSP430FR5724IRGE,MSP430FR5728IRGE,

MSP430FR5730IRGE,MSP430FR5734IRGE,MSP430FR5738IRGE

Functional Block Diagram–

MSP430FR5722IRGE,MSP430FR5726IRGE,

MSP430FR5732IRGE,MSP430FR5736IRGE

1415161719

54327

18RGE PACKAGE (TOP VIEW)

MSP430FR5720MSP430FR5722MSP430FR5724MSP430FR5726MSP430FR5728MSP430FR5730MSP430FR5732MSP430FR5734MSP430FR5736MSP430FR5738

P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*P1.3/TA1.2/UCB0STE/A3*/CD3P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2

P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*

P1.4/TB0.1/UCA0STE/A4*/CD4P1.5/TB0.2/UCA0CLK/A5*/CD5

AVCC

PJ.5/XOUT

PJ.4/XIN AVSS PJ.0/TDO/TB0OUTH/SMCLK/CD6

PJ.1/TDI/TCLK/MCLK/CD7

PJ.2/TMS/ACLK/CD8

PJ.3/TCK/CD9

P2.2/UCB0CLK

P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK

P2.1/UCA0RXD/UCA0SOMI/TB0.0

P1.7/UCB0SOMI/UCB0SCL/TA1.0P1.6/UCB0SIMO/UCB0SDA/TA0.0VCORE

DVCC DVSS

TEST/SBWTCK RST/NMI/SBWTDIO *Not available on MSP430FR5736, MSP430FR5732, MSP430FR5726, MSP430FR5722

Note: Power Pad connection to V recommended.

SS MSP430FR573x MSP430FR572x

SLAS639D –JULY 2011–REVISED AUGUST 2012

https://www.wendangku.net/doc/c215954868.html,

Pin Designation –

MSP430FR5720IRGE,MSP430FR5722IRGE,MSP430FR5724IRGE,MSP430FR5726IRGE,MSP430FR5728IRGE,

MSP430FR5730IRGE,MSP430FR5732IRGE,MSP430FR5734IRGE,MSP430FR5736IRGE,MSP430FR5738IRGE

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分销商库存信息:

MSP430FR5738IRGET MSP430FR5738IRGER