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AD7983中文资料

16-Bit, 1.33 MSPS PulSAR ADC in

MSOP/QFN

AD7983 Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 https://www.wendangku.net/doc/ca16502096.html, Fax: 781.461.3113 ?2007 Analog Devices, Inc. All rights reserved.

FEATURES

16-bit resolution with no missing codes

Throughput: 1.33 MSPS

Low power dissipation: 10.5 mW typical @ 1.33 MSPS

INL: ±0.6 LSB typical, ±1.0 LSB maximum

SINAD: 91.6 dB @ 10 kHz

THD: ?115 dB @ 10 kHz

Pseudo differential analog input range

0 V to V REF with V REF between 2.9 V to 5.5 V

Any input range and easy to drive with the ADA4841

No pipeline delay

Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface

Serial interface SPI-/QSPI?-/MICROWIRE?-/DSP-compatible Daisy-chain multiple ADCs and busy indicator

10-lead MSOP (MSOP-8 size) and 10-lead 3 mm × 3 mm QFN1 (LFCSP), SOT-23 size

Wide operating temperature range: ?40°C to +85°C

APPLICATIONS

Battery-powered equipment

Communications

ATE

Data acquisitions

Medical instruments

APPLICATION DIAGRAM

TO 5V

3- OR 4-WIRE INTERFACE

Figure 1.

GENERAL DESCRIPTION

The AD7983 is a 16-bit, successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 16-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN?. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. Its power scales linearly with throughput.

The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single, 3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO.

The AD7983 is housed in a 10-lead MSOP or a 10-lead QFN1 (LFCSP) with operation specified from ?40°C to +85°C.

1 QFN package in development. Contact sales for samples and availability.

Table 1. MSOP, QFN1 (LFCSP) 14-/16-/18-Bit PulSAR? ADC

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver 14-Bit AD7940AD79422AD79462

16-Bit AD7680AD76852AD76862AD79802ADA4941 AD7683AD76872AD76882AD79832ADA4841

AD7684AD7694AD76932

18-Bit AD76912AD76902AD79822ADA4941

AD79842ADA4841

1 QFN package in development. Contact sales for samples and availability.

2 Pin-for-pin compatible.

AD7983

Rev. 0 | Page 2 of 24

TABLE OF CONTENTS

Features..............................................................................................1 Applications.......................................................................................1 Application Diagram........................................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Timing Specifications.......................................................................5 Absolute Maximum Ratings............................................................6 ESD Caution..................................................................................6 Pin Configurations and Function Descriptions...........................7 Typical Performance Characteristics.............................................8 Terminology....................................................................................11 Theory of Operation......................................................................12 Circuit Information....................................................................12 Converter Operation..................................................................12 Typical Connection Diagram...................................................13 Analog Inputs..............................................................................14 Driver Amplifier Choice...........................................................14 Voltage Reference Input............................................................15 Power Supply...............................................................................15 Digital Interface..........................................................................16 CS MODE, 3-Wire Without Busy Indicator...........................17 CS Mode, 3-Wire with Busy Indicator....................................18 CS Mode, 4-Wire Without Busy Indicator.............................19 CS Mode, 4-Wire with Busy Indicator....................................20 Chain Mode Without Busy Indicator......................................21 Chain Mode with Busy Indicator.............................................22 Application Hints...........................................................................23 Layout..........................................................................................23 Evaluating the Performance of the AD7983...............................23 Outline Dimensions.......................................................................24 Ordering Guide.. (24)

REVISION HISTORY

11/07—Revision 0: Initial Version

AD7983

Rev. 0 | Page 3 of 24

SPECIFICATIONS

VDD = 2.5 V , VIO = 2.3 V to 5.5 V , REF = 5 V , T A = –40°C to +85°C, unless otherwise noted. Table 2.

Parameter Conditions M in Typ M ax Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range IN+ ? IN? 0 V REF V Absolute Input Voltage IN+ ?0.1 V REF + 0.1 V IN? ?0.1 +0.1 V Analog Input CMRR f IN = 100 kHz 60 dB 1Leakage Current @ 25°C Acquisition phase 1 nA Input Impedance See the Analog Inputs section ACCURACY No Missing Codes 16 Bits Differential Linearity Error ?0.9 ±0.4 +0.9 LSB 2Integral Linearity Error ?1.0 ±0.6 +1.0 LSB 2Transition Noise 0.52 LSB 2Gain Error, T MIN to T MAX 3 ±2 LSB 2Gain Error Temperature Drift ±0.41 ppm/°C

Zero Error, T MIN to T MAX 3

?0.9 ±0.44 +0.9 mV Zero Temperature Drift 0.54 ppm/°C Power Supply Sensitivity VDD = 2.5 V ± 5%

±0.1 LSB 2T ROUG PUT Conversion Rate 0 1.33 MSPS Transient Response Full-scale step 290 ns AC ACCURACY Dynamic Range 93 dB 1Signal-to-Noise Ratio, SNR f IN = 1 kHz 90.5 92 dB 1Spurious-Free Dynamic Range, SFDR f IN = 10 kHz 114 dB 1Total Harmonic Distortion, THD f IN = 10 kHz ?115 dB 1Signal-to-(Noise + Distortion), SINAD f IN = 10 kHz 91.6 dB 1

1 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 2

LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 μV. 3

See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.

AD7983

Rev. 0 | Page 4 of 24

VDD = 2.5 V , VIO = 2.3 V to 5.5 V , REF = 5 V , T A = –40°C to +85°C, unless otherwise noted. Table 3.

Parameter Conditions M in Typ M ax Unit REFERENCE Voltage Range 2.9 5.1 V Load Current 1.33 MSPS 500 μA SAMPLING DYNAMICS ?3 dB Input Bandwidth 10 MHz Aperture Delay 2.0 ns DIGITAL INPUTS Logic Levels V IL VIO > 3V –0.3 0.3 × VIO V V IH VIO > 3V 0.7 × VIO VIO + 0.3 V V IL VIO ≤ 3V –0.3 0.1 × VIO V V IH VIO ≤ 3V 0.9 × VIO VIO + 0.3 V I IL ?1 +1 μA I IH ?1 +1 μA DIGITAL OUTPUTS Data Format Serial 16 bits straight binary Pipeline Delay Conversion results available immediately

after completed conversion

V OL I SINK = 500 μA 0.4 V V OH I SOURCE = ?500 μA VIO ? 0.3 V POWER SUPPLIES VDD 2.375 2.5 2.625 V VIO Specified performance 2.3 5.5 V VIO Range 1.8 5.5 V

Standby Current 1, 2

VDD and VIO = 2.5 V 0.35 nA Power Dissipation 1.33 MSPS throughput 10.5 12 mW

Energy per Conversion 7.9 nJ/sample

TEMPERATURE RANGE 3 Specified Performance T MIN to T MAX ?40 +85 °C

1 With all digital inputs forced to VIO or GND as required. 2

During the acquisition phase. 3

Contact sales for extended temperature range.

AD7983

Rev. 0 | Page 5 of 24

TIMING SPECIFICATIONS

T A = ?40°C to +85°C, VDD = 2.37 V to 2.63 V , VIO = 3.3 V to 5.5 V , unless otherwise noted. See Figure 2 and Figure 3 for load conditions.

1.4V

06974-002

Figure 2. Load Circuit for Digital Interface Timing

1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.2MINIMUM V IH AND MAXIMUM V IL

USED. SEE DIGITAL INPUTS

SPECIFICATIONS IN TABLE 3.

06974-003

Figure 3. Voltage Levels for Timing

AD7983

Rev. 0 | Page 6 of 24

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating Analog Inputs

IN+,1 IN?1

to GND ?0.3 V to V REF + 0.3 V or ±130 mA Supply Voltage REF, VIO to GND ?0.3 V to +6 V VDD to GND ?0.3 V to +3 V VDD to VIO ?0.3 V to +6 V Digital Inputs to GND ?0.3 V to VIO + 0.3 V Digital Outputs to GND ?0.3 V to VIO + 0.3 V Storage Temperature Range ?65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 10-Lead MSOP 200°C/W

10-Lead QFN 2

(LFCSP) 48.7°C/W θJC Thermal Impedance 10-Lead MSOP 44°C/W

10-Lead QFN 2

(LFCSP) 2.96°C/W Lead Temperature Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

1 See the Analog Inputs section.

QFN package in development. Contact sales for samples and availability.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

AD7983

Rev. 0 | Page 7 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF

VDD IN+IN–VIO

SDI SCK SDO GND CNV

0697

4-004

Figure 4. 10-Lead MSOP Pin Configuration

REF 1VDD 2IN+ 3

IN– 4

10 VIO

9 SDI 8 SCK 7 SDO GND 5

6 CNV

06974-005

Figure 5. 10-Lead QFN 1 (LFCSP) Pin Configuration

QFN package in development. Contact sales for samples and availability.

AI = analog input, DI = digital input, DO = digital output, and P = power.

AD7983

Rev. 0 | Page 8 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 2.5 V , REF = 5 V , VIO = 3.3 V , unless otherwise noted.

1.25–1.25

65536

06974-026

CODE

I N L (L S B )

1.000.75

0.50

0.25

0–0.25

–0.50

–0.75

–1.0016384

3276849152

Figure 6. Integral Nonlinearity vs. Code

120k

7FB6

06974-041

CODE IN HEX

C O U N T S

100k

80k

60k 40k

20k

7FB77FB87FB97FBA 7FBB 7FBC 7FBD 7FBE 7FBF 7FC07FC17FC2

Figure 7. Histogram of a DC Input at the Code Center

–180

006974-028

FREQUENCY (kHz)

A M P L I T U D E (d

B o f F u l l S c a l e )

–20

–40–60

–80–100–120–140–160100200300400500600

Figure 8. FFT Plot

1.00–1.00

065536

06974-029

CODE

D N L (L S B )

1638432768491520.75

0.50

0.25–0.25–0.50

–0.75

Figure 9. Differential Nonlinearity vs. Code

80k 0

7FF706974-042

CODE IN HEX

C O U N T S

7FF87FF97FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000800180028003

70k 60k

50k

40k 30k 20k

10k

Figure 10. Histogram of a DC Input at the Code Transition

9585–10

06974-032

INPUT LEVEL (dB of Full Scale)

S N R (d B )

–9

–8

–7

–6

–5

–4

–3

–2

–1

949392

919089888786

Figure 11. SNR vs. Input Level

AD7983

Rev. 0 | Page 9 of 24

–110

–120

–55

125

06974-038

TEMPERATURE (°C)

T H D (d B )

–35–15525456585105–112–114–116–118

Figure 12. THD vs. Temperature

–105

–130

2.5 5.5REFERENCE VOLTAGE (V)

T H D (d B )

S F D R (d B )

06974-033

–110–115–120

–125

130

105125

120

115

110

3.0 3.5

4.0 4.5

5.0

Figure 13. THD, SFDR vs. Reference Voltage

10065

100006974-034

FREQUENCY (kHz)

S I N A D (d B

)

110

1009590

85807570 Figure 14. SINAD vs. Frequency

85–55

125

06974-035

TEMPERATURE (°C)

S N R (d B )

–35–15525456585105

Figure 15. SNR vs. Temperature

100

802.5 5.5

REFERENCE VOLTAGE (V)

S N R , S I N A D (d B )

12E N O B (B i t s )

3.0 3.5

4.0 4.5

5.0

06974

-031

Figure 16. SNR, SINAD, and ENOB vs. Reference Voltage

–70–120

1000

06974-037

FREQUENCY (kHz)

T H D (d B )

100

–75–80–85

–90–95–100–105–110–115

Figure 17. THD vs. Frequency

AD7983

Rev. 0 | Page 10 of 24

2.5

02.375

2.62506974-036

V DD VOLTAGE (V)

O P E R A T I N G C U R R E N T S (m A )

2.0

1.5

1.0

0.5

2.425 2.475 2.525 2.575I VDD

I REF

I VIO

Figure 18. Operating Currents vs. Supply

2.5

0–55

125

06974-039

TEMPERATURE (°C)

O P E R A T I N G C U R R E N T S (m A )

–35–155254565851052.0

1.5

1.0

0.5

Figure 19. Operating Currents vs. Temperature

1.50.5–55

125

06974-040

TEMPERATURE (°C)

S T A N D B Y C U R R E N T S (m A )

1.41.3

1.21.11.00.90.80.7

0.6–35

–15

105

Figure 20. Standby Currents vs. Temperature

AD7983

Rev. 0 | Page 11 of 24

TERMINOLOGY

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ? LSB before the first code transition. Positive full scale is defined as a level 1? LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22). Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error

The first transition should occur at a level ? LSB above analog ground (38.1 μV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error

The last transition (from 111 … 10 to 111 … 11) should occur for an analog voltage 1? LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows:

ENOB = (SINAD dB ? 1.76)/6.02 and is expressed in bits.

Noise-Free Code Resolution

Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as

Noise-Free Code Resolution = log 2(2N /Peak-to-Peak Noise ) and is expressed in bits. Effective Resolution

Effective resolution is calculated as

Effective Resolution = log 2(2N /RMS Input Noise ) and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in dB. It is measured with a signal at ?60 dBFS to include all noise sources and DNL artifacts.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB.

Aperture Delay

Aperture delay is the measurement of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion.

Transient Response

Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.

AD7983

Rev. 0 | Page 12 of 24

THEORY OF OPERATION

REF

GND

06974-006

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7983 is a fast, low power, single-supply, precise 16-bit ADC that uses a successive approximation architecture. The AD7983 is capable of converting 1,000,000 samples per second (1 MSPS) and powers down between conversions. When operating at 10 kSPS, for example, it consumes 70 μW typically, making it ideal for battery-powered applications.

The AD7983 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications.

The AD7983 can be interfaced to any 1.8 V to 5 V digital logic family. It is available in a 10-lead MSOP or a tiny 10-lead QFN 1 (LFCSP) that allows space savings and flexible configurations. It is pin-for-pin compatible with the 18-bit AD7982.

CONVERTER OPERATION

The AD7983 is a successive approximation ADC based on a charge redistribution DAC. Figure 21 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via SW+ and SW?. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN? inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the

conversion phase begins, SW+ and SW? are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN? captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps

(V REF /2, V REF /4 … V REF /65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code and a busy signal indicator. Because the AD7983 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.

QFN package in development. Contact sales for samples and availability.

AD7983

Rev. 0 | Page 13 of 24

Transfer Functions

The ideal transfer characteristic for the AD7983 is shown in Figure 22 and Table 7.

000 (000)

000 ... 001000 (010)

111 ...110111 (111)

ANALOG INPUT

A D C C O D E (S T R A I G H T

B I N A R Y )

06974-007

Figure 22. ADC Ideal Transfer Function

Table 7. Output Codes and Ideal Input Voltages

Analog Input Description V REF = 5 V Digital Output Code (Hex) FSR ? 1 LSB 4.999924 V FFFF 1 Midscale + 1 LSB 2.500076 V 8001 Midscale 2.5 V 8000 Midscale ? 1 LSB 2.499924 V 7FFF ?FSR + 1 LSB 76.3 μV 0001 ?FSR 0 V 00002

1 This is also the code for an overranged analog input (V IN+ ? V IN? above V REF ? V GND ). 2

This is also the code for an underranged analog input (V IN+ ? V IN? below V GND ).

TYPICAL CONNECTION DIAGRAM

Figure 23 shows an example of the recommended connection diagram for the AD7983 when multiple supplies are available.

3- OR 4-WIRE INTERFACE

2.5V

0 TO VREF

1.8V TO 5V 1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.2C REF IS USUALLY A 10μF CERAMIC CAPACITOR (X5R).3SEE THE DRIVER AMPLIFIER CHOICE SECTION.

4OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION.

5SEE THE DIGITAL INTERFACE SECTION FOR THE MOST CONVENIENT INTERFACE MODE.

06974-008

Figure 23. Typical Application Diagram with Multiple Supplies

AD7983

Rev. 0 | Page 14 of 24

ANALOG INPUTS

Figure 24 shows an equivalent circuit of the input structure of the AD7983.

The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN?. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V , because this causes these diodes to become forward-biased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the supplies of the input buffer (U1) are different from VDD. In such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the part.

06974-009

Figure 24. Equivalent Analog Input Circuit

The analog input structure allows the sampling of the true differential signal between IN+ and IN?. By using these

differential inputs, signals common to both inputs are rejected. During the acquisition phase, the impedance of the analog inputs (IN+ and IN?) can be modeled as a parallel combination of capacitor, C PIN , and the network formed by the series connection of R IN and C IN . C PIN is primarily the pin capacitance. R IN is typically 400 Ω and is a lumped component made up of some serial resistors and the on resistance of the switches. C IN is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to C PIN . R IN and C IN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. When the source impedance of the driving circuit is low, the AD7983 can be driven directly. Large source impedances

significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.

DRIVER AMPLIFIER CHOICE

Although the AD7983 is easy to drive, the driver amplifier needs to meet the following requirements: ?

The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7983. The noise coming from the driver is filtered by the AD7983 analog input circuit’s 1-pole, low-pass filter made by R IN and C IN or by the external filter, if one is used. Because the typical noise of the AD7983 is 39.7 μV rms, the SNR degradation due to the amplifier is

?????

???

??+=?23dB 2)

(2π7.9339.7

log 20N LOSS

Ne f SNR where:

f –3dB is the input bandwidth in MHz of the AD7983 (10 MHz) or the cutoff frequency of the input filter, if one is used.

N is the noise gain of the amplifier (for example, 1 in buffer configuration).

e N is the equivalent input noise voltage o

f the op amp, in nV/√Hz. ? For ac applications, the driver should have a THD performance commensurate with the AD7983.

For multichannel multiplexed applications, the driver amplifier and the AD7983 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). In the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.

Table 8. Recommended Driver Amplifiers

Amplifier Typical Application

ADA4841-x Very low noise, small and low power AD8021Very low noise and high frequency AD8022Low noise and high frequency

OP184Low power, low noise, and low frequency AD8655

5 V single-supply, low noise AD8605, AD8615

5 V single-supply, low power

AD7983

Rev. 0 | Page 15 of 24

VOLTAGE REFERENCE INPUT

The AD7983 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section.

When REF is driven by a very low impedance source, for example, a reference buffer using the AD8031 or the AD8605, a ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, a reference-decoupling capacitor value as small as 2.2 μF can be used with a minimal impact on performance, especially DNL.

Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins.

POWER SUPPLY

The AD7983 uses two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.0 V . To reduce the number of supplies needed, VIO and VDD can be tied together. The AD7983 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 25.

11000

FREQUENCY (kHz)

P S R R (d B

)

1010075

06974-010

Figure 25. PSRR vs. Frequency

To ensure optimum performance, VDD should be roughly half of REF, the voltage reference input. For example, if REF is 5.0 V , VDD should be set to 2.5 V (±5%).

AD7983

Rev. 0 | Page 16 of 24

DIGITAL INTERFACE

Though the AD7983 has a reduced number of pins, it offers flexibility in its serial interface modes.

When in CS mode, the AD7983 is compatible with SPI, QSPI, and digital hosts. This interface can use either a 3-wire or a 4-wire interface. A 3-wire interface using the CNV , SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV , SCK, and SDO signals allows CNV , which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. The AD7983, when in chain mode, provides a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register.

The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high, and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected, the chain mode is always selected.

In either mode, the AD7983 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback.

The busy indicator feature is enabled

? In CS mode if CNV or SDI is low when the ADC conversion ends (see Figure 29 and Figure 33).

? In chain mode if SCK is high during the CNV rising edge (see Figure 37).

AD7983

Rev. 0 | Page 17 of 24

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7983 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 26, and the corresponding timing is given in Figure 27.

With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. When a conversion is initiated, it continues until completion irrespective of the state of CNV . This can be useful, for example, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7983 enters the acquisition phase and goes into standby mode.

When CNV goes low, the MSB is output onto SDO. The

remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided that it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance.

06974-012

Connection Diagram (SDI High)

SDI = 1

CNV

SCK

SDO

06974-013

Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)

AD7983

Rev. 0 | Page 18 of 24

CS MODE, 3-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7983 is connected to an SPI-compatible digital host that has an interrupt input. The connection diagram is shown in Figure 28, and the corresponding timing is given in Figure 29.

With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV . Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data read back controlled by the digital host. The AD7983 then enters the acquisition phase and goes into standby mode. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance. If multiple AD7983s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended that this contention be kept as short as possible to limit extra power dissipation.

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Figure 28. CS Mode, 3-Wire with Busy Indicator

Connection Diagram (SDI High)

SCK

CNV

06974-015

Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)

AD7983

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CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7983s are connected to an SPI-compatible digital host.

A connection diagram example using two AD7983s is shown in Figure 30, and the corresponding timing is given in Figure 31. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7983 enters the

acquisition phase and goes into standby mode. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7983 can be read.

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Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram

SCK

CNV

t t SDO

06974-017

Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing

AD7983

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CS MODE, 4-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7983 is connected to an SPI-compatible digital host that has an interrupt input, and when it is desired to keep CNV , which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 32, and the corresponding timing is given in Figure 33.

With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low.

With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7983 then enters the acquisition phase and goes into standby mode. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge or SDI going high, whichever is earlier, the SDO returns to high impedance.

06974-018

Figure 32. CS Mode, 4-Wire with Busy Indicator Connection Diagram

ACQUISITION

t SDI

t SCK

CNV

SDO

06974-019

Figure 33. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing