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tps40211

FEATURES

CONTENTS

DESCRIPTION

APPLICATIONS

V UDG-07110

TPS40210,TPS40211

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4.5-V TO 52-V INPUT CURRENT MODE BOOST CONTROLLER

?For Boost,Flyback,SEPIC,LED Drive Apps Device Ratings

2?Wide Input Operating Voltage:4.5V to 52V Electrical Characteristics 3?Adjustable Oscillator Frequency

Typical Characteristics 5?Fixed Frequency Current Mode Control ?Internal Slope Compensation Terminal Information 10?Integrated Low-Side Driver

Application Information 12?Programmable Closed Loop Soft Start Additional References 25?Overcurrent Protection

Design Examples

?External Synchronization Capable

?Reference700-mV (TPS40210),260-mV (TPS40211)

The TPS40210and TPS40211are wide-input voltage ?

Low Current Disable Function

(4.5V to 52V),non-synchronous boost controllers.They are suitable for topologies which require a grounded source N-channel FET including boost,?LED Lighting

flyback,SEPIC and various LED Driver applications.?Industrial Control Systems The device features include programmable soft start,overcurrent protection with automatic retry and ?

Battery Powered Systems

programmable oscillator frequency.Current mode control provides improved transient response and simplified loop compensation.The main difference between the two parts is the reference voltage to which the error amplifier regulates the FB pin.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.Copyright ?2008,Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.

DEVICE RATINGS

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

PACKAGE DISSIPATION RATINGS

ELECTROSTATIC DISCHARGE (ESD)PROTECTION

TPS40210,TPS40211

SLUS772C–MARCH 2008–REVISED OCTOBER https://www.wendangku.net/doc/c717193730.html,

These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGE TAPE AND REEL T J

PACKAGE PART NUMBER LEAD QUANTITY

2500TPS40210DGQR 10-Pin MSOP DGQ

PowerPAD

80TPS40210DGQ -40°C to 125°C

3000TPS40210DRCR 10-Pin SON DRC 250TPS40210DRCT 2500TPS40211DGQR 10-Pin MSOP DGQ PowerPAD

80TPS40211DGQ -40°C to 125°C

3000TPS40211DRCR 10-Pin SON

DRC 250

TPS40211DRCT

over operating free-air temperature range unless otherwise noted (1)

TPS40210UNIT

TPS40211

VDD

–0.3to 52Input voltage range RC,SS,FB,DIS/EN –0.3to 10V ISNS

–0.3to 8Output voltage range

COMP,BP,GDRV

–0.3to 9T J Operating junction temperature range

–40to 150°C T stg Storage temperature

–55to 150

(1)

Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

MIN

NOM

MAX UNIT V VDD Input voltage

4.552V T J

Operating Junction temperature

-40

125

°C

R θJA High-K Board (1)

Power Rating (W)

PACKAGE

AIRFLOW (LFM)(°C/W)

T A =25°C

T A =85°C

10-Pin MSOP PowerPAD

0(Natural Convection)57.7 1.730.693(DGQ)10-Pin SON (DRC)0(Natural Convection)

47.9

2.08

0.835

(1)

Ratings based on JEDEC High Thermal Conductivity (High K)Board.For more information on the test method,see TI Technical Brief SZZA017.

MIN

TYP MAX

UNIT Human Body Model (HBM)1500V

Charged Device Model (CDM)

1500

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ELECTRICAL CHARACTERISTICS TPS40210,TPS40211

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T J=–40°C to125°C,V VDD=12V dc,all parameters at zero power dissipation(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE REFERENCE

TPS40210COMP=FB,4.5≤V VDD≤52V,T J=25°C693700707 Feedback voltage range

TPS40211COMP=FB,4.5≤V VDD≤52V,T J=25°C254260266

COMP=FB,4.5≤V VDD≤52V,-40°C≤T J≤

V FB mV

TPS40210686700714

125°C

COMP=FB,4.5≤V VDD≤52V,-40°C≤T J≤

TPS40211250260270

125°C

INPUT SUPPLY

V VDD Input voltage range 4.552V

4.5≤V VDD≤52V,no switching,V DIS<0.8 1.5 2.5mA

I VDD Operating current 2.5≤V DIS≤7V1020μA

V VDD

V UVLO(on)Turn on threshold voltage 4.00 4.25 4.50V

V UVLO(hyst)UVLO hysteresis140195240mV OSCILLATOR

Oscillator frequency range(1)351000

f OSC kHz

Oscillator frequency R RC=182k?,C RC=330pF260300340

Frequency line regulation 4.5≤V DD≤52V-20%7%

V SLP Slope compensation ramp520620720mV PWM

V VDD=12V(1)275400

t ON(min)Minimum pulse width

V VDD=30V90200ns

t OFF(min)Minimum off time170200

V VLY Valley voltage 1.2V SOFT-START

Offset voltage from SS pin to error

V SS(ofst)700mV amplifier input

R SS(chg)Soft-start charge resistance320430600

R SS(dchg)Soft-start discharge resistance84012001600

ERROR AMPLIFIER

GBWP Unity gain bandwidth product(1) 1.5 3.0MHz

A OL Open loop gain(1)6080dB

Input bias current(current out of FB

I IB(FB)100300nA

pin)

I COMP(src)Output source current V FB=0.6V,V COMP=1V100250μA

I COMP(snk)Output sink current V FB=1.2V,V COMP=1V 1.2 2.5mA OVERCURRENT PROTECTION

Overcurrent detection threshold(at

V ISNS(oc) 4.5≤V DD<52V,-40°C≤T J≤125°C120150180mV ISNS pin)

D OC Overcurrent duty cycle(1)2%

Overcurrent reset threshold voltage(at

V SS(rst)100150350mV SS pin)

T BLNK Leading edge blanking(1)75ns (1)Ensured by design.Not production tested.

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TPS40210,TPS40211

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ELECTRICAL CHARACTERISTICS(continued)

T J=–40°C to125°C,V VDD=12V dc,all parameters at zero power dissipation(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT SENSE AMPLIFIER

A CS Current sense amplifier gain 4..2 5.67.2V/V

I B(ISNS)Input bias current13μA DRIVER

I GDRV(src)Gate driver source current V GDRV=4V,T J=25°C375400

I GDRV(snk)Gate driver sink current V GDRV=4V,T J=25°C330400

LINEAR REGULATOR

V BP Bypass voltage output0mA

V DIS(en)Turn on voltage0.7 1.3V

V DIS(hys)Hysteresis voltage25130220mV

R DIS DIS pin pulldown resistance0.7 1.1 1.5M?

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TYPICAL CHARACTERISTICS

0400

800

1200

100

200

600100

f S W -F r e q u e n c y -k H z

R T -Timing Resistance -k W

300

200

40060050080010009007000

400

800

1200

0200

600

1000

f S W -F r e q u e n c y -k H z

D -Duty Cycle 0.20.4

0.8 1.2

0.6 1.00

0.41.4

-400.2

1.2

I V D D –Q u i e s c e n t C u r r e n t –m A

T J –Junction Temperature –°C

-10-255502080125

9565351100.8

0.6

1.0

-401

I V D D –S h u t d o w n C u r r e n t –m A

T J –Junction Temperature –°C

-10-25

5502080125

9565351103

TPS40210,TPS40211

FREQUENCY

SWITCHING FREQUENCY

TIMING RESISTANCE

DUTY CYCLE

Figure 1.

Figure 2.

QUIESCENT CURRENT

SHUTDOWN CURRENT

JUNCTION TEMPERATURE

Figure 3.

Figure 4.

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-0.8

-0.4

0.4

-40-0.60.2

V F B –R e f e r e n c e V o l t a g e C h a n g e –%

T J –Junction Temperature –°C

-10-255502080125

9565351100.0

-0.2

-0.5

-0.30.50

-0.40.4V F B –R e f e r e n c e V o l t a g e C h a n g e –%

V VDD

–Input Voltage –V

302060

50400.10.00.2-0.1-0.20.34.00

4.30-404.05

4.25

V U V L O –U n d e r v o l t a g e L o c k o u t T h r e s h o l d –V

T J –Junction Temperature –°C

-10-255502080125

9565351104.154.10

4.20

147

150155

-40148

154V I S N S (O C )–O v e r c u r r e n t T h r e s h o l d –m V

T J –Junction Temperature –°C

-10-255502080125

956535110152

151

153149TPS40210,TPS40211

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TYPICAL CHARACTERISTICS (continued)

REFERENCE VOLTAGE CHANGE

JUNCTION TEMPERATURE

INPUT VOLTAGE

Figure 5.

Figure 6.

UNDERVOLTAGE LOCKOUT THRESHOLD

OVERCURRENT THRESHOLD

JUNCTION TEMPERATURE

Figure 7.

Figure 8.

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V I S N S (O C )–O v e r c u r r e n t T h r e s h o l d –m V

V VDD –Input Voltage –V

1510

20145

148155

14615315114915215415014735

3040-5

-25-40-4

3f O S C –S w i t c h i n g F r e q u e n c y C h a n g e –%

T J –Junction Temperature –°C

-10-255502080125

9565351101-12

40-315

29-4017

S l o p e C o m p e n s a t i o n R a t i o (V V D D /V S L P )

T J –Junction Temperature –°C

-10-255502080125

9565351102319

4001400

-40200

1200R S S –S o f t S t a r t C h a r g e /D i s c h a r g e R e s i s t a

n c e -k W

T J –Junction Temperature –°C

-10-255502080125

9565351101000800

600

TPS40210,TPS40211

TYPICAL CHARACTERISTICS (continued)

OVERCURRENT THRESHOLD

SWITCHING FREQUENCY CHANGE

INPUT VOLTAGE

JUNCTION TEMPERATURE

Figure 9.

Figure 10.

OSCILLATOR AMPLITUDE

SOFT-START CHARGE/DISCHARGE RESISTANCE

JUNCTION TEMPERATURE

Figure 11.

Figure 12.

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40180-4020

160I I B (F B )–F e e d b a c k B i a s C u r r e n t –n A

T J –Junction Temperature –°C

-10-255502080125

9565351101008012060

1400

100

300-4050

250

I C O M P (S R C )–C o m p e n s a t i o n S o u r c e C u r r e n t –m A

T J –Junction Temperature –°C

-10-255502080125

956535110200

150

-40I C O M P (S N K )–C o m p e n s a t i o n S i n k C u r r e n t –m A

T J –Junction Temperature –°C -10-255502080125

9565351100

100

30050

250

200

150

-40V V L Y –V a l l e y V o l t a g e C h a n g e –%

T J –Junction Temperature –°C

-10-255502080125

956535110-5

-25-4

31-124

0-3TPS40210,TPS40211

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TYPICAL CHARACTERISTICS (continued)

FB BIAS CURRENT

COMPENSATION SOURCE CURRENT

JUNCTION TEMPERATURE

Figure 13.

Figure 14.

COMPENSATION SINK CURRENT

VALLEY VOLTAGE CHANGE

JUNCTION TEMPERATURE

Figure 15.

Figure 16.

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7.4

7.88.8-407.6

8.6

V B P –R e g u l a t o r V o l t a g e –V

T J –Junction Temperature –°C

-10-255502080125

9565351108.48.2

8.0

1.00

1.021.10

-401.01

1.09V D I S

(E N )–D I S /E N T u r n -O n T h r e s h o l d –m V

T J –Junction Temperature –°C

-10-255502080125

9565351101.061.05

1.071.03

1.081.06A C

S –C u r r e n t S e n s e A m p l i f i e r G a i n –V /V

-40T J –Junction Temperature –°C

-10-255502080125

956535110TPS40210,TPS40211

TYPICAL CHARACTERISTICS (continued)

REGULATOR VOLTAGE

TURN-ON THRESHOLD

JUNCTION TEMPERATURE

Figure 17.

Figure 18.

CURRENT SENSE AMPLIFIER GAIN

JUNCTION TEMPERATURE

Figure 19.

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DEVICE INFORMATION

10237489FB

RC COMP

DIS/EN SS GND

VDD ISNS GDRV BP DGQ PowerPAD PACKAGE

(Top View)

RC COMP

DIS/EN SS 5

432116

78910

GND

VDD ISNS GDRV BP DRC SURFACE MOUNT PACKAGE

(Top View)

TPS40210,TPS40211

SLUS772C–MARCH 2008–REVISED OCTOBER https://www.wendangku.net/doc/c717193730.html,

TERMINAL FUNCTIONS

TERMINAL I/O DESCRIPTION

NAME https://www.wendangku.net/doc/c717193730.html,P 4O Error amplifier output.Connect control loop compensation network between COMP pin and FB pin.

Disable pin.Pulling this pin high,places the part into a shutdown mode.Shutdown mode is characterized by a very low quiescent current.While in shutdown mode,the functionality of all blocks is disabled and the BP DIS/EN

regulator is shut down.This pin has an internal 1-M ?pull-down resistor to GND.Leaving this pin unconnected enables the device.

Error amplifier inverting input.Connect a voltage divider from the output to this pin to set output voltage.FB 5I Compensation network is connected between this pin and COMP.GDRV 8O Connect the gate of the power N channel MOSFET to this pin.GND 6-Device ground.

Current sense pin.Connect an external current sensing resistor between this pin and GND.The voltage on this pin is used to provide current feedback in the control loop and detect an overcurrent condition.An

ISNS

overcurrent condition is declared when ISNS pin voltage exceeds the overcurrent threshold voltage,150mV typical.

Switching frequency setting pin.Connect capacitor from RC pin to GND.Connect a resistor from RC pin RC 1I toVDD of the IC power supply and a capacitor from RC to GND.

Soft-start time programming pin.Connect capacitor from SS pin to GND to program converter soft-start time.SS 2I This pin also functions as a timeout timer when the power supply is in an overcurrent condition.BP 9O Regulator output pin.Connect a 1.0-μF bypass capacitor from this pin to GND.

System input voltage.Connect a local bypass capacitor from this pin to GND.Depending on the amount of VDD

required slope compensation,this pin can be connected to the converter output.See Application Information section for additional details.

DGQ PowerPAD PACKAGE

DRC PACKAGE (TOP VIEW)

(TOP VIEW)

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COMP

DIS/EN SS

RC BP

VDD

GDRV GND

ISNS

UDG-07107

TPS40210,TPS40211

FUNCTIONAL BLOCK DIAGRAM

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APPLICATION INFORMATION

Minimum On-Time and Off Time Considerations

OUT D IN V V 1

V 1D

-(1)

IN OUT D V D 1V V ????=-?÷?

÷?

÷+è?è?

(2)

()()f OUT D OUT SW

IN 2V V I L D V ′+′′′=

(3)

()()()f 2

OUT D IN IN OUT(crit)2

OUT D SW V V V V I 2V V L

+-′=

′+′′(4)

TPS40210,TPS40211

SLUS772C–MARCH 2008–REVISED OCTOBER https://www.wendangku.net/doc/c717193730.html,

The TPS40210has a minimum off time of approximately 200ns and a minimum on time of 300ns.These two constraints place limitations on the operating frequency that can be used for a given input to output conversion ratio.See Figure 2for the maximum frequency that can be used for a given duty cycle.

The duty cycle at which the converter operates is dependent on the mode in which the converter is running.If the converter is running in discontinuous conduction mode,the duty cycle varies with changes to the load much more than it does when running in continuous conduction mode.

In continuous conduction mode,the duty cycle is related primarily to the input and output voltages.

In discontinuous mode the duty cycle is a function of the load,input and output voltages,inductance and switching frequency.

All converters using a diode as the freewheeling or catch component have a load current level at which they transition from discontinuous conduction to continuous conduction.This is the point where the inductor current just falls to zero.At higher load currents,the inductor current does not fall to zero but remains flowing in a positive direction and assumes a trapezoidal wave shape as opposed to a triangular wave shape.This load boundary between discontinuous conduction and continuous conduction can be found for a set of converter parameters as follows.

For loads higher than the result of Equation 4,the duty cycle is given by Equation 2and for loads less that the results of Equation 4,the duty cycle is given Equation 3.For Equations 1the variable definitions are as ?V OUT is the output voltage of the converter in V

?V D is the forward conduction voltage drop across the rectifier or catch diode in V ?V IN is the input voltage to the converter in V ?I OUT is the output current of the converter in A ?L is the inductor value in H

?f SW is the switching frequency in Hz

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Setting the Oscillator Frequency

T 810274692

SW T SW SW T T 1

R 5.810f C 810f 1.410f 1.510 1.710C 410C ------=

′′′+′′+′′-′+′′-′′(5)

Synchronizing the Oscillator

UDG-08063

TPS40210,TPS40211

The oscillator frequency is determined by a resistor and capacitor connected to the RC pin of the TPS40210.The capacitor is charged to a level of approximately V VDD /20by current flowing through the resistor and is then discharged by a transistor internal to the TPS40210.The required resistor for a given oscillator frequency is found from either Figure 1or Equation 5.

where

?R T is the timing resistance in k ??f SW is the switching frequency in kHz ?

C T is the timing capacitance in pF

For most applications a capacitor in the range of 68pF to 120pF gives the best results.Resistor values should be limited to between 100k ?and 1M ?as well.If the resistor value falls below 100k ?,decrease the capacitor size and recalculate the resistor value for the desired frequency.As the capacitor size decreases below 47pF,the accuracy of Equation 5degrades and empirical means may be needed to fine tune the timing component values to switching frequency.

The TPS40210and TPS40211can be synchronized to an external clock source.Figure 20shows the functional diagram of the oscillator.When synchronizing the oscillator to an external clock,be pulled below 150mV for 20ns or more.The external clock frequency must be higher than the free running frequency of the converter as well.When synchronizing the controller,if the RC pin is held low for an excessive amount of time,erratic operation may occur.The maximum amount of time that the RC pin should be held low is 50%of a nominal output pulse,or 10%of the period of the synchronization frequency.

Under circumstances where the duty cycle is less than 50%,a Schottky diode connected from the RC pin to an external clock may be used to synchronize the oscillator.The cathode of the diode is connected to the RC pin.The trip point of the oscillator is set by an internal voltage divider to be 1/20of the input voltage.The clock signal must have an amplitude higher than this trip point.When the clock goes low,it allows the reset current to restart the RC ramp,synchronizing the oscillator to the external clock.This provides a simple,single-component method for clock synchronization.

Figure 20.Oscillator Functional Diagram

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Frequency >Frequency

Amplitude >

V IN Duty Cycle <50%

UDG-08064

Current Sense and Overcurrent

UDG-07119

UDG-07120

TPS40210,TPS40211

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Figure 21.Diode Connected Synchronization

The tps40210and TPS40211are current mode controllers and use a resistor in series with the source terminal power FET to sense current for both the current mode control and overcurrent protection.The device enters a current limit state if the voltage on the ISNS pin exceeds the current limit threshold voltage V ISNS(oc)from the electrical specifications table.When this happens the controller discharges the SS capacitor through a relatively high impedance and then attempt to restart.The amount of output current that causes this to happen is dependent on several variables in the converter.

Figure 22.Oscillator Components Figure 23.Current Sense Components

The load current overcurrent threshold is set by proper choice of R ISNS .If the converter is operating in discontinuous mode the current sense resistor is found in Equation 6.

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ISNS L V R ′′=

(6)

()f ISNS ISNS

ISNS OUT RIPPLE OUT IN SW V V R I I I D V 1D 21D 2L =

????????

′++?÷?÷?÷?÷?÷-è?-′′è?è

?è?(7)

Current Sense and Sub-Harmonic Instability

f VDD e SW V s 20??

=′?÷

è?

(8)

()

CS ISNS OUT D IN A R V V V m2L

′′+-=

(9)

TPS40210,TPS40211

If the converter is operating in continuous conduction mode R ISNS can be found in Equation 7.

where

R ISNS is the value of the current sense resistor in ?.

?V ISNS(oc)is the overcurrent threshold voltage at the ISNS pin (from electrical specifications)?D is the duty cycle (from Equation 2)?f SW is the switching frequency in Hz

?V IN is the input voltage to the power stage in V (see text)?L is the value of the inductor in H

?I OUT (oc)is the desired overcurrent trip point in A ?

V D is the drop across the diode in Figure 23

The TPS40210/11has a fixed undervoltage lockout (UVLO)that allows the controller to start at a typical input voltage of 4.25V.If the input voltage is slowly rising,the converter might have less than its designed nominal input voltage available when it has reached regulation.As a result,this may decreases the apparent current limit load current value and must be taken into consideration when selecting R ISNS .The value of V IN used to calculate R ISNS must be the value at which the converter finishes startup.The total converter output current at startup is the sum of the external load current and the current required to charge the output capacitor(s).See the Soft Start section of this datasheet for information on calculating the required output capacitor charging current.

The topology of the standard boost converter has no method to limit current from the input to the output in the event of a short circuit fault on the output of the converter.If protection from this type of event is desired,it is necessary to use some secondary protection scheme such a fuse or rely on the current limit of the upstream power source.

A characteristic of peak current mode control results in a condition where the current control loop can exhibit instability.This results in alternating long and short pulses from the pulse width modulator.The voltage loop maintains regulation and dioes not oscillate,but the output ripple voltage increases.The condition occurs only when the converter is operating in continuous conduction mode and the duty cycle is 50%or greater.The cause of this condition is described in Texas Instruments literature number SLUA101,available at https://www.wendangku.net/doc/c717193730.html,.The remedy for this condition is to apply a compensating ramp from the oscillator to the signal going to the pulse width modulator.In the TPS40210/11the oscillator ramp is applied in a fixed amount to the pulse width modulator.The slope of the ramp is given in Equation 8.

To ensure that the converter does not enter into sub-harmonic instability,the slope of the compensating ramp signal must be at least half of the down slope of the current ramp signal.Since the compensating ramp is fixed in the TPS40210/11,this places a constraint on the selection of the current sense resistor.

The down slope of the current sense wave form at the pulse width modulator is described in Equation 9.

Since the slope compensation ramp must be at least half,and preferably equal to the down slope of the current sense waveform seen at the pulse width modulator,a maximum value is placed on the current sense resistor

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()

f VDD SW

ISNS(max)OUT D IN V L R 60V V V ′′=

′+-(10)

Current Sense Filtering

f ON SW

D t =

(11)

IFLT IFLT ON

R C 0.1t ′=′(12)

Soft Start

TPS40210,TPS40211

SLUS772C–MARCH 2008–REVISED OCTOBER https://www.wendangku.net/doc/c717193730.html,

when operating in continuous mode at 50%duty cycle or greater.For design purposes,some margin should be applied to the actual value of the current sense resistor.As a starting point,the actual resistor chosen should be 80%or less that the value calculated in Equation 10.This equation calculates the resistor value that makes the slope compensation ramp equal to one ramp downslope.Values no more than 80%of this result would be acceptable.

where

?S e is the slope of the voltage compensating ramp applied to the pulse width modulator in V/s ?f SW is the switching frequency in Hz ?V VDD is the voltage at the VDD pin in V

?m2is the down slope of the current sense waveform seen at the pulse width modulator in V/s ?R ISNS is the value of the current sense resistor in ?

?V OUT is the converter output voltage V IN is the converter power stage input voltage ?

V D is the drop across the diode in Figure 23

It is possible to increase the voltage compensation ramp slope by connecting the VDD pin to the output voltage of the converter instead of the input voltage as shown in Figure 23.This can help in situations where the converter design calls for a large ripple current value in output current limit setting.

NOTE:

Connecting the VDD pin to the output voltage of the converter affects the startup voltage of the converter since the controller undervoltage lockout (UVLO)circuit monitors the VDD pin and senses the input voltage less the diode drop before startup.The effect is to increase the startup voltage by the value of the diode voltage drop.

If an acceptable R ISNS value is not available,the next higher value can be used and the signal from the resistor divided down to an acceptable level by placing another resistor in parallel with C ISNS .

In most cases,a small filter placed on the ISNS pin improves performance of the converter.These are the components R IFLT and C IFLT in Figure 23.The time constant of this filter should be approximately 10%of the nominal pulse width of the width can be found using Equation 11.

The suggested time constant is then

The range of R IFLT should be from about 1k ?to 5k ?for best results.Higher values can be used but this raises the impedance of the ISNS pin connection more than necessary and can lead to noise pickup issues in some layouts.C ISNS should be located as close as possible to the ISNS pin as well to provide noise immunity.

The soft-start feature of the TPS40210/11is a closed loop soft start,meaning that the output voltage follows a linear ramp that is proportional to the ramp generated at the SS pin.This ramp is generated by an internal resistor connected from the BP pin to the SS pin and an external capacitor connected from the SS pin to GND.The SS pin voltage (V SS )is level shifted down by approximately V SS(ofst)(approximately 700mV)and sent to one of the “+”(the “+”input with the lowest voltage dominates)inputs of the error amplifier.When this level shifted voltage (V SSE )starts to rise at time t 1(see Figure 24),the output voltage the controller expects,rises as well.Since V SSE starts at near 0V,the controller regulate the output voltage from a starting point of zero volts.It cannot do this due to the converter architecture.The output voltage starts from the input voltage less the

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UDG-07121

()

SS BP SS(ofst)

SS BP

SS(ofst)FB t C V V R ln V V

V =

÷′?÷-+è?

(13)

TPS40210,TPS40211

drop across the diode (V IN -V D )and rise from there.The point at which the output voltage starts to rise (t 2)is the point where the V SSE ramp passes the point where it is commanding more output voltage than (V IN -V D ).This voltage level is labeled V SSE(1).The time required for the output voltage to ramp from a theoretical zero to the final regulated value (from t 1to t 3)is determined by the time it takes for the capacitor connected to the SS pin (C SS )to rise through a 700mV range,beginning at V SS(ofst)above GND.

Figure 24.SS Pin Voltage adn Output Voltage Figure 25.SS Pin Functional Circuit

The required capacitance for a given soft start time t 3–t 1in Figure 24is calculated in Equation 13.

where

?t SS is the soft-start time

?R SS(chg)is the SS charging resistance in ?,typically 500k ??C SS is the value of the capacitor on the SS pin,in F ?V BP is the value of the voltage on the BP pin in V

?V SS(ofst)is the approximate level shift from the SS pin to the error amplifier (~700mV)?

V FB is the error amplifier reference voltage,700m V typical

Note that t SS is the time it takes for the output voltage to rise from 0V to the final output voltage.Also note the tolerance on R SS(chg)given in the electrical specifications table.This contributes to some variability in the output voltage rise time and margin must be applied to account for it in design.

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I= C(chg)C V

OUT OUT

′

(14)

t> SS

C V

(I I)

OUT OUT

OUT(oc)EXT

′

(15)

TPS40210,TPS40211

SLUS772C–MARCH2008–REVISED https://www.wendangku.net/doc/c717193730.html, Also take note of V BP.Its value varies depending on input conditions.For example,a converter operating from a slowly rising input initializes V BP at a fairly low value and increases during the entire startup sequence.If the controller has a voltage above8V at the input and the DIS pin is used to stop and then restart the converter,V BP is approximately8V for the entire startup sequence.The higher the voltage on BP,the shorter the startup time is and conversely,the lower the voltage on BP,the longer the startup time is.

The soft-start time(t SS)must be chosen long enough so that the converter can start up without going into an overcurrent state.Since the over current state is triggered by sensing the peak voltage on the ISNS pin,that voltage must be kept below the overcurrent threshold voltage V ISNS(oc).The voltage on the ISNS pin is a function of the load current of the converter,the rate of rise of the output voltage and the output capacitance,and the current sensing resistor.The total output current that must be supported by the converter is the sum of the charging current required by the output capacitor and any external load that must be supplied during startup.This current must be less than the I OUT(oc)value used in Equation6or Equation7(depending on the operating mode of the converter)to determine the current sense In the actual input voltage at the time that the controller reaches the final output voltage is the important input voltage to use in the calculations.If the input voltage is slowly rising and is at less than the nominal input voltage when the startup time ends,the output current limit is less than I OUT(oc)at the nominal input voltage.The output capacitor charging current must be reduced(decrease C OUT or increase the t SS)or I OUT(oc)must be increased and a new value for R ISNS calculated.

where

?I C(chg)is the output capacitor charging current in A

?C OUT is the total output capacitance in F

?V OUT is the output voltage in V

?t SS is the soft start time from Equation13

?I OUT(oc)is the desired over current trip point in A

?I EXT is any external load current in A

The capacitor on the SS pin(C SS)also plays a role in overcurrent functionality.It is used as the timer between restart attempts.The SS pin is connected to GND through a resistor,R SS(dchg),whenever the controller senses an overcurrent condition.Switching stops and nothing else happens until the SS pin discharges to the soft-start reset threshold,V SS(rst).At this point,the SS pin capacitor is allowed to charge again through the charging resistor R SS(chg),and the controller restarts from that point.The shortest time between restart attempts occurs when the SS pin discharges from V SS(ofst)(approximately700mV)to V SS(rst)(150mV)and then back to V SS(ofst) and switching resumes.In actuality,this is a conservative estimate since switching does not resume until the V SSE ramp rises to a point where it is commanding more output voltage than exists at the output of the controller. This occurs at some SS pin voltage greater than V SS(ofst)and depends on the voltage that remains on the output overvoltage the converter while switching has been halted.The fastest restart time can be calculated by using Equation16,Equation17and Equation18.

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SS(ofst)

DCHG SS(dchg)SS SS(rst)V t R C ln V ???

÷=′′?÷è?

(16)

()(

)BP SS(rst)

CHG

SS(chg)SS BP

SS(ofst)V V

t R C ln V V

??-?

÷=′′?÷-è?

(17)()CHG DCHG

RSTRT min t t t =+(18)

T -Time

TPS40210,TPS40211

Figure 26.Soft Start During Overcurrent

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BP Regulator

Q VDD VDD(en)P V I =′(19)f G VDD g SW

P V Q =′′(20)E VDD EXT

P V I =′(21)

Shutdown (DIS/EN Pin)

TPS40210,TPS40211

SLUS772C–MARCH 2008–REVISED OCTOBER https://www.wendangku.net/doc/c717193730.html,

The TPS40210/11has an on board linear regulator the supplies power for the internal circuitry of the controller,including the gate driver.This regulator has a nominal output voltage of 8V and must be bypassed with a 1-μF capacitor.If the voltage at the VDD pin is less than 8V,the voltage on the BP pin ia also be less and the gate drive voltage to the external FET ia reduced from the nominal 8V.This should be considered when choosing a FET for the converter.

Connecting external loads to this regulator can be done,but care must be taken to ensure that the thermal rating of the device is observed since is no thermal shutdown feature in this controller.Exceeding the thermal ratings cause out of specification behavior and can lead to reduced reliability.The controller dissipates more power when there is an external load on the BP pin and is tested for dropout voltage for up to 5-mA load.When the controller is in the disabled state,the BP pin regulator also shuts off so loads connected there power down as well.When the controller is disabled with the DIS/EN pin,this regulator is turned off.

The total power dissipation in the controller can be calculated as follows.The total power is the sum of P Q ,P G and P E .

where

?P Q is the quiescent power of the device in W ?V VDD is the VDD pin voltage in V

?I VDD(en)is the quiescent current of the controller when enabled but not switching in A ?P G is the power dissipated by driving the gate of the FET in W

?Q g is the total gate charge of the FET at the voltage on the BP pin in C ?f SW is the switching frequency in Hz

?P E is the dissipation caused be external loading of the BP pin in W ?

I EXT is the external load current in A

The DIS/EN pin is an active high shutdown command for the controller.Pulling this pin above 1.2V causes the controller to completely shut down and enter a low current consumption state.In this state,the regulator connected to the BP pin is turned off.There is an internal 1.1-M ?pull-down resistor connected to this pin that keeps the pin at GND level when left floating.If this function is not used in an application,it is best to connect this pin to GND

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