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74LCX541

74LCX541 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Features

■ 5V tolerant input and outputs

■ 2.3V–3.6V V CC specifications provided ■ 6.5ns t PD max (V CC = 3.3V), 10μA I CC max ■ Power-down high impedance inputs and outputs ■ Supports live insertion/withdrawal (1) ■ ±24 mA output drive (V CC = 3.0V)

■ Implements patented noise/ EMI reduction circuitry ■ Latch-up performance exceeds JEDEC 78 conditions ■ ESD performance

– Human body model >

2000V – Machine model > 200V ■ Leadless DQFN package

Note:

1.To ensure the high impedance state during power up or down, OE should be tied to V CC through a pull-up resistor: the minimum value of the resistor is

determined by the current-sourcing capability of the driver.

General Description

The LCX541 is an octal buffer/line driver designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. The LCX541 is a non inverting option of the LCX540.

This device is similar in function to the LCX244 while providing flow-through architecture (inputs on opposite side from outputs). This pinout arrangement makes this device especially useful as an output port for micropro-cessors, allowing ease of layout and greater PC board density.

The LCX541 is designed for low voltage applications with capability of interfacing to a 5V signal environment.The LCX541 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.

Ordering Information

Note:

2.DQFN package available in Tape and Reel only.

Order Number

Package Number

Package Description

74LCX541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LCX541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX541BQX (2)

MLP20B 20-T erminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm

74LCX541MSA MSA2020-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX541MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LCX541 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Pad Assignment for DQFN

(Top View)

Pin Descriptions

Truth Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

Pin Names

Description

OE 1 , OE 2 3-ST A TE Output Enable Inputs

I 0 –I 7 Inputs O 0 –O 7

Outputs

I 1I 2I 3I 4I 5I 6I 7GND

O 0O 1O 2O 3O 4O 5O 6O 7

345678910

1817161514131211

I 1I 2I 3I 4I 5I 6I 7GND I 0O 0O 1O 2O 3O 4O 5O 6

O 7

OE 2V CC

23456789

1918171615141312OE 1 Inputs

Outputs

OE 1

OE 2

O n

L L H H H X X Z X H X Z L

O 0I 0O 1I 1O 2I 2O 3I 3O 4I 4O 5I 5O 6I 6O 7

I 7

74LCX541 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Recommended Operating Conditions (4)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Notes:

3.I O Absolute Maximum Rating must be observed.

4.Unused inputs must be held HIGH or LOW. They may not float.

V CC Supply Voltage –0.5 to +7.0V V I DC Input Voltage –0.5 to +7.0

V V O DC Output Voltage Output in 3-ST A TE

–0.5 to +7.0V Output in HIGH or LOW State (3) –0.5 to V CC + 0.5

I IK DC Input Diode Current V I < GND –50mA I OK DC Output Diode Current V O < GND –50mA V O > V CC

+50I O DC Output Source/Sink Current ±50mA I CC DC Supply Current per Supply Pin ±100mA I GND DC Ground Current per Ground Pin ±100mA T STG

Storage T emperature

–65 to +150

°C

Symbol

Parameter

Conditions

Min.

Max.

Units

V CC Supply Voltage Operating 2.0 3.6V Data Retention 1.5 3.6V I Input Voltage 0 5.5V V O Output Voltage HIGH or LOW State 0V CC V 3-ST A TE 0

5.5I OH /

I OL

Output Current

V CC = 3.0V–3.6V ±24mA

V CC = 2.7V–3.0V ±12V CC = 2.3V–2.7V

±8

T A Free-Air Operating T emperature –4085°C ? t /

? V

Input Edge Rate

V IN = 0.8V–2.0V , V CC = 3.0V

74LCX541 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs

AC Electrical Characteristics

Notes

5.Outputs disabled or 3-STATE only.

6.Skew is defined as the absolute value of the difference between the actual propagation delay for any two

separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).

V IL LOW Level Input Voltage 2.3–2.70.7V 2.7–3.60.8

V OH

HIGH Level Output Voltage

2.3–

3.6I OH = –100μA V CC – 0.2V

2.3I OH = –8mA 1.82.7I OH = –12mA 2.2

3.0

I OH = –18mA 2.4I OH = –24mA 2.2

V OL

LOW Level Output Voltage 2.3–3.6I OL = 100μA 0.2V

2.3I OL = 8mA 0.62.7I OL = 12mA 0.4

3.0

I OL = 16mA 0.4I OL = 24mA 0.55I I Input Leakage Current 2.3–3.60 ≤ V I ≤ 5.5V ±5.0μA I OFF Power-Off Leakage Current 0V I or V O = 5.5V 10μA I CC Quiescent Supply Current 2.3–3.6V I

= V CC or GND 10μA 3.6V ≤ V I , V O ≤ 5.5V (5)±10?I CC

Increase in I CC per Input

2.3–

3.6

V IH = V CC = 0.6V

500

μA

Symbol

Parameter

T A = –40°C to +85°C, R L = 500?

Units

V CC = 3.3V ± 0.3V ,

C L = 50pF

V CC = 2.7V ,C L = 50pF V CC = 2.5V ± 0.2V ,

C L = 30pF Min.

Max.

Min.

Max.

Min.

Max.

t PHL , t PLH Propagation Delay 1.5 6.5 1.57.5 1.57.8ns t PZL , t PZH Output Enable Time 1.58.5 1.59.5 1.510.5ns t PLZ , t PHZ Output Disable Time 1.5

7.5 1.5

8.5

1.5

9.0

ns t OSHL , t OSLH

Output to Output Skew (6)

1.0

74LCX541 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs

Capacitance

V OLV

Quiet Output Dynamic Valley V OL

3.3C L = 50 pF , V IH = 3.3V , V IL = 0V –0.8V

2.5

C L = 30 pF , V IH = 2.5V , V IL = 0V

–0.6

Symbol

Parameter

Conditions

Typical

Units

C IN Input Capacitance V CC = Open, V I = 0V or V CC 7pF C OUT Output Capacitance

V CC = 3.3V , V I = 0V or V CC

8pF C PD

Power Dissipation Capacitance

V CC = 3.3V , V I = 0V or V CC , f = 10 MHz

3-STATE Output Low Enable and

Disable Times for Logic

t rise and t fall

Figure 2. Waveforms (Input Characteristics; f = 1MHz, t r = t f = 3ns)

OUT

V mo

V OL

Symbol

V CC 3.3V ± 0.3V

2.7V

2.5V ± 0.2V

Tape Size A B C D N W1W2 12mm13.0 (330.0)0.059 (1.50)0.512 (13.00)0.795 (20.20) 2.165 (55.00)0.488 (12.4)0.724 (18.4)

Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speci?cations do not expand the terms of Fairchild’s worldwide terms and conditions, speci?cally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

https://www.wendangku.net/doc/c918078725.html,/packaging/

Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

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DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY,FUNCTION,OR DESIGN.FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS,NOR THE RIGHTS OF OTHERS.THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS,SPECIFICALLY THE WARRANTY THEREIN,WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1.Life support devices or systems are devices or systems

which,(a)are intended for surgical implant into the body or

(b)support or sustain life,and(c)whose failure to perform

when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury of the user.2.A critical component in any component of a life support,

device,or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design This datasheet contains the design specifications for product development.Specifications may change in any manner without notice.

Preliminary First Production This datasheet contains preliminary data;supplementary data will be

published at a later date.Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design. 74LCX541 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs