外文翻译--AT89C52单片机的介绍
中文4800字
附录3：外文翻译
AT89C52 monolithic integrated circuit introduction AT89C52 is the low voltage which American ATMEL Corporation produces, the high performance CMOS 8 monolithic integrated circuits, internal may repeatedly scratch read-only program memory (PEROM) and 256bytes random access data-carrier storage (RAM) including 8k bytes which writes, the component uses ATMEL Corporation the high density, the non-volatility memory technology production, is compatible with the standard MCS-51 command system and 8052 product pins, internal sets at general 8 central processor (CPU) and the Flash memory cell, the function formidable AT89C52 monolithic integrated circuit suits in many comparatively plurality of controls application situation.
Main performance parameter:
Are completely compatible with the MCS-51 product instruction and the pin
The 8k byte may again scratch writes Flash to dodge the fast memory
1000 times scratches the write cycle
Entire static operation: 0Hz—24MHz
Three level of encryption program memory
256×8 In byte RAM
32 programmable I/O mouth line
3 16 fixed time/counters
8 interrupt sources
Programmable serial UART channel
The low power loss idle and falls the electricity pattern
Function characteristic outline:
Below AT89C52 provides the standard function: 8k byte Flash dodges the fast memory, 256 byte internal RAM,32 I/O mouth line, 3 16 fixed time/counters, 6 vector two level of interrupt structures, A full-duplex serial passes unguardedly, internal oscillator and clock electric circuit.At the same time, AT89C52 may fall to the 0HZ static state logical operation, and supports the electricity saving working pattern which two kind of softwares may elect.The idle way stops CPU the work, but permits RAM, fixed time/the counter, serial passes unguardedly and the interruption system continues to work.Falls the electricity way to preserve in RAM the content, but the oscillator knock off and forbids other all part work to reposition until the next hardware.
The pin function shows
Vcc: Supply voltage
GND: Grounding
P0 mouth: The P0 mouth is one group of 8 leaks leads the way extremely the bidirectional I/O mouth, also is the address/data bus multiplying mouth.As outlet with when, each potential energy absorption current way actuates 8 TTL logic gate, when writes “1” to port P0, may take the high impedance input end uses.
When visits exterior data-carrier storage or the program memory, when this group of mouth line segment transforms the address (low 8) and the data bus multiplying, pulls the resistance in the visit activation interior.
When Flash programming, P0 mouth receive instruction byte, but when program check, when output order byte, verification, outside the request joins pulls the resistance
P1 mouth: P1 is in a belt interior pulls the resistance 8 bidirectional I/O mouth, the P1 output buffer may actuate (absorption or output current) 4 TTL logic gate.Writes “1” to the port, pulls the resistance through internal on to pull the port to
the high level, this time may make the input port.When makes the input port use, because in internal existence pulls the resistance, some pin is pulled lowly by exterior signal when can output electric current (IIL).
With at89C51 similarity is, P1.0 and P1.1 also may take separately fixed time/the counter 2 exterior countings inputs (P1.0/T2) and inputs (P1.1/T2EX), see also table 1.
Flash programming and program check period, P1 receives the low 8 bit address.
P2 mouth: P2 is one has in the interior to pull the resistance 8 bidirectional I/O mouth, the P2 output buffer may actuate (absorption or output current) 4 TTL logic gate.Writes “1” to port P2, pulls the resistance through internal on to pull the port to the high level, this time may make the input port, when makes the input port use, because in internal existence pulls the resistance, some pin is pulled lowly by exterior signal when can output electric current (IIL).
When visits exterior program memory or 16 bit address exterior data-carrier storage (e.g. carries out the MOVX@DPTR instruction), the P2 mouth sends out the high 8 bit address data.When visits 8 bit addresses exterior data-carrier storage (for example carries out the MOVX@RI instruction), the P2 mouth outputs the P2 latch the content
When Flash programming or verification, P2 also receives the top digit address and some control signal.
P3 mouth: The P3 mouth is a group has in the interior to pull the resistance 8 bidirectional I/O mouth.The P3 mouth output buffer may actuate (absorption or output current) 4 TTL logic gate.Read s in “1” when to the P3 mouth, they the position resistance are pulled by the interior in Gao Bingke the achievement to input the port.This time, will be pulled by the outside the low P3 mouth to use to pull resistance output current (IIL).
The P3 mouth besides took the general I/O mouth line, a more important use is
In addition, the P3 mouth also receives some to use in Flash dodging the fast memory programming and the program check control signal.
RST: Replacement input.When the oscillator works, the RST pin will appear above two machine cycles the high level to cause the monolithic replacement.
ALE/PROG: When visits exterior program memory or the data-carrier storage, ALE (address lock saves permission) to output the pulse to use in the lock saving the address the low 8 bytes.In ordinary circumstances, ALE still by clock oscilation frequency 1/6 output fixed pulse signal, therefore it may the foreign output clock or uses in fixed time the goal.Must pay attention: When visits exterior data-carrier storage will jump over a ALE pulse.
To Flash memory programming period, this pin also uses in inputting programming pulse (PROG).
If has the necessity, may through to in special function register (SFR) area 8EH the unit D0 position position, be possible to forbid the ALE operation.After this position position, only then MOVX and the MOVC instruction can activate ALE.In addition, this pin can pull weakly high, when the monolithic integrated circuit carries out exterior procedure, should establish the ALE prohibition position to be invalid PSEN: The procedure storage permits the (PSEN) output is exterior program memory reads the gating signal, when AT89C52 takes the instruction by exterior program memory (or data), each machine cycle two PSEN is effective, namely outputs two pulses.When visits exterior data-carrier storage, will jump over two RSEN signals.
EA/VPP: Exterior visit permission.Wants to cause CPU only to visit exterior program memory (address is 0000H-FFFFH), the EA end must maintain the low level (earth).Must pay attention: If adds mil LB1 to program, when replacement the interior
can lock saves the EA end condition.
If the EA end (meets the Vcc end) for the high level, CPU carries out in the internal procedure memory instruction.
When the Flash memory programs, this pin adds on 12V programming permission power source VPP, certainly this must be this component is uses 12V to program voltage VPP.
XTAL1: Oscillator inverting amplifier and internal clock generator input end.
XTAL2: Oscillator inverting amplifier out-port. Special function register:
In at89C52 internal memory, the 80H-FFH altogether 128 units for special function register (SFE), SFR address basement reflection as shown in Table 2.
All addresses all are defined by no means, only then a part is defined from the 80H-FFH altogether 128 bytes, but also has quite a part not to define.To the definition unit read-write will not have been Yuan Xiao, the read-out value will be indefinite, but will read in the data will also lose.
Should not “1” not read in the data the definition unit, then will possibly entrust with the new function in these units in the future product, in this case, after replacement these unit value always “0”.
AT89C52 besides with A T89C51 all fixed time/counters 0 and fixed time/counter 1, but also increased a fixed time/counter 2.Fixed time/the counter 2 control status
byte is located T2CON、T2MOD (to see Table 4), the register to (RCA02H, RCAP2L) is the timer 2/automatic loads the register again under 16 capture ways or 16 automatic heavy loading way capture.
Interrupt register:
AT89C52 has 6 interrupt sources, 2 interrupt priorities, the IE register controls each interrupt position, in the IP register 6 interrupt source each may decide as 2 superior
data-carrier storages:
AT89C52 has 256 byte internal RAM,80H-FFH high 128 bytes and the special function register (SFR) address is overlap, also is high 128 byte RAM and the special function register address is same, but in physics they are separated.
When an instruction visits the 7FH above dummy home address unit, in the instruction uses the addressing way is different, also is the addressing way decision is visits high 128 byte RAM to visit the special function register.If the instruction is the direct addressing way for the visit special function register.
For example, following direct addressing instruction visit special function register 0A0H (i.e. P2 mouth) address unit.
MOV 0A0H,#data
The indirect addressing instruction visits high 128 byte RAM, for example, in following indirect addressing instruction, the R0 content is 0A0H, then the visit data byte address is 0A0H, but is not the P2 mouth (0A0H).
MOV the @R0,#data
storehouse operation also is the indirect addressing way, therefore, high 128 bit data RAM also may take the storehouse area use.
Timer 0 and timer 1:
The AT89C52 timer 0 and the timer 1 working and AT89C51 are same.
Timer 2:
The timer 2 is 16 fixed time/counters.It already may when timer use, also may take the external event counter use, its working chooses by the special function register T2CON C/T2 position.The timer 2 has three workings: The capture way, the automatic heavy loading (upward or downward counting) the way and the baudrate generator way, the working chooses by the T2CON control position, see also table 4.
The timer 2 is composed by two 8 register TH2 and TL2, in the timer working, each machine cycle TL2 register value adds 1, because a machine cycle vibrates the clock constitution by 12, therefore, counting speed for oscilation frequency 1/12.
When counting working, when on the T2 pin exterior input signal produces by 1 to 0 drops along, the register value adds 1, under this working, each machine cycle 5SP2 period, carries on the sampling to exterior input. If picks in the first machine cycle the value is 1, but the value which picks in the next machine cycle is 0, then is following close on the next cyclical S3P1 period register adds 1.Because distinguishes 1 to need 2 machine cycles to 0 jumps (24 durations of oscillation), therefore, highest counting speed for oscilation frequency 1/24. In order to guarantee the sampling the accuracy, the request input level maintains at least before the change for a complete cyclical the time, guarantees the input signal at least by sampling one time.
Capture way:
Under the capture way, chooses two ways through T2CON control position EXEN2.If EXEN2=0, the timer 2 is 16 timers or the counter, when counting overflow, to the T2CON overflow symbolized TF2 sets at the position, simultaneously activates the interrupt.If looks up EXEN2=1, the timer 2 completes the same operation, But when the T2EX pin exterior input signal has 1 to 0 negative jumps, also appears in TH2 and the TL2 value is caught separately to in RCAP2H and RCAP2L.Moreover, the T2EX pin signal jump causes in T2CON EXF2 to set at the position, is similar with TF2, EXF2 also can interrupt exactly.Capture way as shown in Figure 4.
Automatic heavy loading (upward or downward counter) way:
When timer 2 work in 16 automatic heavy loading ways, can to its programming for upward or the downward counting way, this function may (see Table 5) through special function register T2CON the DCEN position (permission downward counting) choose.When replacement, the DCEN position “0”, the timer 2 defaults establishes as the upward counting. When DCEN sets at the position, the timer 2 already may count upwardly also may the downward counting, this is decided by the T2EX pin value,
see also Figure 5, when DCEN=0, the timer 2 automatic setups for the upward counting, under this way, in the T2CON EXEN2 control position have two kind of choices, if EXEN2=0, the timer 2 for the upward counting to the 0FFFFH overflow, sets at the position TF2 activation interrupt, simultaneously 16 counter register RCAP2H and the RCAP2L heavy loading, RCAP2H and the RCAP2L value may by the software initialization.
When DCEN sets at the position, the timer 2 already may count upwardly also may the downward counting, this is decided by the T2EX pin value, see also Figure 5, when DCEN=0, the timer 2 automatic setups for the upward counting, under this way, in the T2CON EXEN2 control position have two kind of choices, if EXEN2=0, the timer 2 for the upward counting to the 0FFFFH overflow, sets at the position TF2 activation interrupt, simultaneously 16 counter register RCAP2H and the RCAP2L heavy loading, RCAP2H and the RCAP2L value may by the software initialization.
Baudrate generator:
When T2CON (Table 3) TCLK and RCLK set at the position, fixed time/the counter 2 takes the baudrate generator use.If fixed time/the counter 2 took the
transmitter or the receiver, its transmission and the receive baudrate may be different, the timer 1 uses in other functions, as shown in Figure 7.If RCLK and TCLK set at the position, then timer 2 work in baudrate generator way.
The baudrate generator way and the automatic heavy loading way are similar, under this way, the TH2 turn over causes the timer 2 registers is important the new loading with in RCAP2H and the RCAP2L 16 figures, this value establishes by the software.
In the way 1 and the way in 3, the baudrate determined by the timer 2 overflow speeds according to the equation below that,Way 1 and 3 baudrate = timer overflow rate /16
The timer already can work in fixed time the way also can work in the counting way, in the majority applications, is the work in fixed time the way (C/T2=0).The timer 2 took when baudrate generator, with as the timer operation is different, when usual achievement timer, (1/12 oscilation frequency) checks the value in each machine cycle to add 1, but took when baudrate generator use, (1/2 oscilation frequency) the register value adds 1 in each condition time. The baudrate formula is as follows:
The way 1 and 3 baudrate = oscilation frequency/{32×[65536-(RCAP2H, RCAP2L)]}
in the formula (RCAP2H, RCAP2L) is in RCAP2H and RCAP2L 16 does not have the sign digit.
The timer 2 took the baudrate generator use electric circuit as shown in Figure 7.In when T2CON RCLK or TCLK=1, the baudrate working only then is effective. In the baudrate generator working, the TH2 turn over cannot cause TF2 to set at the
position, therefore does not have the interrupt.But if EXEN2 sets at the position, also the T2EX end produces by 1 to 0 negative jumps, then can cause EXF2 to set at the position, this time cannot load (RCAP2H, RCAP2L) content in TH2 and TL2.Therefore, when the timer 2 takes the baudrate generator use, T2EX may use as the additional exterior interrupt source.Needs to pay attention, when timer 2 work in baudrate, when moves (TR2=1) as the timer, cannot visit TH2 and TL2.Because this time each condition time timer can add 1, to its read-write will obtain a indefinite value.
But however, may read to RCAP2 cannot write, because the write operation will be the reload, the write operation possibly command writes with/or the heavy loading makes a mistake.In visits timer 2 or in front of the RCAP2 register, should (eliminate the timer closure TR2).
The programmable clock outputs:
The timer 2 may output a dutyfactor through the programming from P1.0 is 50% clock signal, as shown in Figure 8.The P1.0 pin besides is a standard I/O mouth, but also may cause it through the programming to take fixed time/the counter 2 exterior clock inputs and the output dutyfactor 50% clock pulse.When the clock oscilation frequency is 16MHz, outputs the clock frequency range is 61Hz-4MHz.
When establishes fixed time/the counter 2 as the clock generator, C/T2(T2CON.1)=0, T2OE(T2MOD.1)=1, must or stops the timer by TR2(T2CON.2) start.The clock output frequency is decided in the oscilation frequency and the timer 2 catches the register (RCAP2H, RCAP2L) reload value, the formula is as follows:
The output clock frequency = oscillator frequency/{4×[65536-(RCAP2H, RCAP2L)]}
under the clock output way, the timer 2 turn over cannot have the interrupt, this characteristic with took when baudrate generator use is similar.When the timer 2 takes the baudrate generator use, Also may take the clock generator use, but needs to pay attention is the baudrate and the clock output frequency cannot separate the determination, this is because they with use RCAP2H and RCAP2L.
AT89C52单片机的介绍
AT89C52是美国ATMEL公司生产的低电压，高性能CMOS 8位单片机，片内含8k bytes的可反复擦写的只读程序存储器（PEROM）和256bytes的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，与标准MCS－51指令系统及8052产品引脚兼容，片内置通用8位中央处理器（CPU）和Flash存储单元，功能强大AT89C52单片机适合于许多较为复杂控制应用场合。
主要性能参数：
与MCS－51产品指令和引脚完全兼容
8k字节可重擦写Flash闪速存储器
1000次擦写周期
全静态操作：0Hz—24MHz
三级加密程序存储器
256×8字节内部RAM
32个可编程I/O口线
3个16位定时/计数器
8个中断源
可编程串行UART通道
低功耗空闲和掉电模式
功能特性概述：
AT89C52提供以下标准功能：8k字节Flash闪速存储器，256字节内部RAM，32个I/O口线，3个16位定时/计数器，一个6向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C52可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许
RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。
引脚功能说明
Vcc：电源电压
GND：地线
P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口P0写“1”时，可作为高阻抗输入端用。
在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。
在Flash编程时，P0口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻
P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电
阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。
与AT89C51不同之处是，P1.0和P1.1还可分别作为定时/计数器2的外部计数输入（P1.0/T2）和输入（P1.1/T2EX），参见表1。
Flash编程和程序校验期间，P1接收低8位地址。
表1 P1.0和P1.1的第二功能
P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口P2写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。
在访问外部程序存储器或16位地址的外部数据存储器（例如执行MOVX＠DPTR指令）时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器（如执行MOVX＠RI指令）时，P2口输出P2锁存器的内容
Flash编程或校验时，P2亦接收高位地址和一些控制信号。
P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对P3口写入“1”时，它们被内部上位电阻拉高并可作为输入端口。此时，被外部拉低的P3口将用上拉电阻输出电流（IIL）。
P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能，如下表所示：
此外，P3口还接收一些用于Flash闪速存储器编程和程序校验的控制信号。
RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片复位。
ALE/PROG：当访问外部程序存储器或数据存储器时，ALE（地址锁存允许）输出脉冲用于锁存地址的低8位字节。一般情况下，ALE仍以时钟振荡频率的1/6输出固定的脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。
对Flash存储器编程期间，该引脚还用于输入编程脉冲（PROG）。
如有必要，可通过对特殊功能寄存器（SFR）区中的8EH单元的D0位置位，可禁止ALE操作。该位置位后，只有一条MOVX和MOVC指令才能将ALE激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE禁止位无效PSEN：程序储存允许（PSEN）输出是外部程序存储器的读选通信号，当AT89C52由外部程序存储器取指令（或数据）时，每个机器周期两次PSEN有效，即输出两个脉冲。在此期间，当访问外部数据存储器，将跳过两次RSEN信号。
EA/VPP：外部访问允许。欲使CPU仅访问外部程序存储器（地址为0000H－FFFFH），EA端必须保持低电平（接地）。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。
如EA端为高电平（接Vcc端），CPU则执行内部程序存储器中的指令。
Flash存储器编程时，该引脚加上+12V的编程允许电源VPP，当然这必须是该器件是使用12V编程电压VPP。
XTAL1：振荡器反相放大器的及内部时钟发生器的输入端。
XTAL2：振荡器反相放大器的输出端。
特殊功能寄存器：
AT89C52片内存储器中，80H－FFH共128个单元为特殊功能寄存器（SFE），SFR的地址窨映象如表2所示。
并非所有的地址都被定义，从80H－FFH共128个字节只有一部分被定义，还有相当一部分没有定义。对没有定义的单元读写将是元效的，读出的数值将不确定，而写入的数据也将丢失。
不应将数据“1”写入未定义的单元，则于这些单元在将来的产品中可能赋予新的功能，在这种情况下，复位后这些单元数值总是“0”。
AT89C52除了与AT89C51所有的定时/计数器0和定时/计数器1外，还增加了一个定时/计数器2。定时/计数器2的控制状态位位于T2CON、T2MOD（见表4），寄存器对（RCA02H、RCAP2L）是定时器2在16位捕获方式或16位自动重装载方式下的捕获/自动重装载寄存器。
中断寄存器：
AT89C52有6个中断源，2个中断优先级，IE寄存器控制各中断位，IP寄存器中6个中断源的每一个可定为2个优
数据存储器：
AT89C52有256个字节的内部RAM，80H－FFH高128个字节与特殊功能寄存器（SFR）地址是重叠的，也就是高128字节的RAM和特殊功能寄存器的地址是相同的，但物理上它们是分开的。
当一条指令访问7FH以上的内部地址单元时，指令中使用的寻址方式是不同的，也即寻址方式决定是访问高128字节RAM还是访问特殊功能寄存器。如果指令是直接寻址方式则为访问特殊功能寄存器。
例如，下面的直接寻址指令访问特殊功能寄存器0A0H（即P2口）地址单元。
MOV 0A0H，＃data
间接寻址指令访问高128字节RAM，例如，下面的间接寻址指令中，R0的内
容为0A0H，则访问数据字节地址为0A0H，而不是P2口（0A0H）。
MOV ＠R0，＃data
堆栈操作也是间接寻址方式，所以，高128位数据RAM亦可作为堆栈区使用。
定时器0和定时器1：
AT89C52的定时器0和定时器1的工作方式与AT89C51相同。
定时器2：
定时器2是一个16位定时/计数器。它既可当定时器使用，也可作为外部事件计数器使用，其工作方式由特殊功能寄存器T2CON的C/T2位选择。定时器2有三种工作方式：捕获方式，自动重装载（向上或向下计数）方式和波特率发生器方式，工作方式由T2CON的控制位来选择，参见表4。
表4 定时器2工作方式
定时器2由两个8位寄存器TH2和TL2组成，在定时器工作方式中，每个机器周期TL2寄存器的值加1，由于一个机器周期由12个振荡时钟构成，因此，计数速率为振荡频率的1/12。
在计数工作方式时，当T2引脚上外部输入信号产生由1至0的下降沿时，寄存器的值加1，在这种工作方式下，每个机器周期的5SP2期间，对外部输入进行采样。若在第一个机器周期中采到的值为1，而在下一个机器周期中采到的值为0，则在紧跟着的下一个周期的S3P1期间寄存器加1。由于识别1至0的跳变需要2个机器周期（24个振荡周期），因此，最高计数速率为振荡频率的1/24。为确保采样的正确性，要求输入的电平在变化前至少保持一个完整周期的时间，以保证输入信号至少被采样一次。
捕获方式：
在捕获方式下，通过T2CON控制位EXEN2来选择两种方式。如果EXEN2＝0，定时器2是一个16位定时器或计数器，计数溢出时，对T2CON的溢出标志TF2置位，同时激活中断。如查EXEN2＝1，定时器2完成相同的操作，而当T2EX引脚外部输入信号发生1至0负跳变时，也出现TH2和TL2中的值分别被捕获到RCAP2H和RCAP2L中。另外，T2EX引脚信号的跳变使得T2CON中的EXF2置位，与TF2相仿，EXF2也会活中断。捕获方式如图4所示。
自动重装载（向上或向下计数器）方式：
当定时器2工作于16位自动重装载方式时，能对其编程为向上或向下计数方式，这个功能可通过特殊功能寄存器T2CON（见表5）的DCEN位（允许向下计数）来选择的。复位时，DCEN位置“0”，定时器2默认设置为向上计数。当DCEN 置位时，定时器2既可向上计数也可向下计数，这取决于T2EX引脚的值，参见图5，当DCEN＝0时，定时器2自动设置为向上计数，在这种方式下，T2CON中的EXEN2控制位有两种选择，若EXEN2＝0，定时器2为向上计数至0FFFFH溢出，置位TF2激活中断，同时把16位计数寄存器RCAP2H和RCAP2L重装载，RCAP2H 和RCAP2L的值可由软件预置。若EXEN2＝1，定时器2的16位重装载由溢出或外部输入端T2EX从1至0的下降沿触发。这个脉冲使EXF2置位，如果中断允许，同样产生中断。
当DCEN＝1时，允许定时器2向上或向下计数，如图6所示。这种方式下，T2EX引脚控制计数器方向。T2EX引脚为逻辑“1”时，定时器向上计数，当计数0FFFFH向上溢出时，置位TF2，同时把16位计数寄存器RCAP2H和RCAP2L载到TH2和TL2中。T2EX引脚为逻辑“0”时，定时器2向下计数，当TH2和TL2中的数值等于RCAP2H和RCAP2L中的值时，计数溢出，置位TF2，同时将0FFFFH 数值重新装入定时寄存器中。
AT89C51单片机外文翻译
AT89C51外文翻译 Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51? instruction-set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. Features ? Compatible with MCS-51? Products ? 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to 24 MHz ? Three-Level Program Memory Lock ? 128 x 8-Bit Internal RAM ? 32 Programmable I/O Lines ? Two 16-Bit Timer/Counters ? Six Interrupt Sources ? Programmable Serial Channel ? Low Power Idle and Power Down Modes The AT89C51 provides the following standard features: 4K bytes of Flash,128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
步进电机及单片机英文文献及翻译
外文文献： Knowledge of the stepper motor What is a stepper motor： Stepper motor is a kind of electrical pulses into angular displacement of the implementing agency. Popular little lesson: When the driver receives a step pulse signal, it will drive a stepper motor to set the direction of rotation at a fixed angle (and the step angle). You can control the number of pulses to control the angular displacement, so as to achieve accurate positioning purposes; the same time you can control the pulse frequency to control the motor rotation speed and acceleration, to achieve speed control purposes. What kinds of stepper motor sub-： In three stepper motors: permanent magnet (PM), reactive (VR) and hybrid (HB) permanent magnet stepper usually two-phase, torque, and smaller, step angle of 7.5 degrees or the general 15 degrees; reaction step is generally three-phase, can achieve high torque output, step angle of 1.5 degrees is generally, but the noise and vibration are large. 80 countries in Europe and America have been eliminated; hybrid stepper is a mix of permanent magnet and reactive advantages. It consists of two phases and the five-phase: two-phase step angle of 1.8 degrees while the general five-phase step angle of 0.72 degrees generally. The most widely used Stepper Motor. What is to keep the torque (HOLDING TORQUE) How much precision stepper motor? Whether the cumulative： The general accuracy of the stepper motor step angle of 3-5%, and not cumulative.
会计内部控制中英文对照外文翻译文献
会计内部控制中英文对照外文翻译文献(文档含英文原文和中文翻译)
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单片机外文翻译
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外文翻译--如何监测内部控制
附录A
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51单片机外文文献
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单片机外文文献翻译
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中小企业内部控制_外文参考文献 安徽工业大学毕业设计外文翻译 Private Enterprises of the intenal control issues Pulin Chang Economic Review. 2008, (5) Third, the promotion of private SMEs in the internal control system strategy (A) change management and business owners the concept of development. The majority of private small and medium enterprises in the family business, the success of these enterprises depends largely on internal control or entrepreneur leadership attention and level of implementation. Over the years, by traditional Chinese culture, business owners believe in Sincerity, fraternal loyalty permeate many aspects of enterprise management, strengthen internal controls that will affect the organization the members of distrust, resulting in internal control. Many private business owners that rely on business to do business benefits out of, rather than out of the internal financial management control; that the market is the most important internal control will be bound himself and staff development. Understanding of the bias, so that these leaders neglected the internal control system on the production and operation activities. Internal control can really become the leader of the internal needs of enterprise internal control system is the key to whether a mere formality. The internal control to make the internal needs of the enterprise depends largely on two points: First, determine
单片机外文翻译--STC89C52处理芯片
外文资料翻译 STC89C52 processi ng chip Prime features: With MCS - 51 SCM product compatibility, 8K bytes in the system programmable Flash memory, 1000 times CaXie cycle, the static operation: 0Hz ~ 33Hz, triple encryption program memory, 32 programmed I/O port, three 16 timer/counter, the eight uninterrupted dual-career UART serial passage, low power consumption, leisure and fall after fall electric power mode can be awakened and continuous watchdog timer and double-number poin ter, power ide ntifier. Efficacy: characteristics STC89C52 is one kind of low power consumption, high CMOS8 bit micro-co ntroller, 8K in system programmable Flash memory. Use high-de nsity nonv olatile storage tech no logy, and in dustrial 80C51 product in structi on and pin fully compatible. The Flash memory chips allows programs in the system, also suitable for programmable conventional programming. In a single chip, have clever 8 bits CPU and on li ne system programmable Flash, in crease STC89C52 for many embedded control system to provide high vigorous application and useful solutions. STC89C52 has following standard efficacy: 8k byte Flash RAM, 256 bytes, 32 I/O port, the watchdog timer, two, three pointer numerical 16 timer/counter, a 6 vector level 2 continuous structure, the serial port, working within crystals and horological circuit. In addition, 0Hz AT89S52 can drop to the static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, and allows the RAM, timer/c oun ters, serial, continu ous to work. Protectio n asa na patter n, RAM content is survival, vibrators frozen, SCM, until all the work under a continuous or hardware reset. 8-bit microcontrollers 8K bytes in the system programmable Flash AT89S52 devices. Mouth: P0 P0 mouth is a two-way ope n drain I/O. As export, each can drive eight TTL logic level. For P0 port to write "1", foot as the high impeda nee in put. When access to exter nal programs and nu merical memory, also known as
单片机的外文文献及中文翻译
SCM is an integrated circuit chip, is the use of large scale integrated circuit technology to a data processing capability of CPU CPU random access memory RAM, read-only memory ROM, a variety of I / O port and interrupt system, timers / timer functions (which may also include display driver circuitry, pulse width modulation circuit, analog multiplexer, A / D converter circuit) integrated into a silicon constitute a small and complete computer systems. SCM is also known as micro-controller (Microcontroller), because it is the first to be used in industrial control. Only a single chip by the CPU chip developed from a dedicated processor. The first design is by a large number of peripherals and CPU on a chip in the computer system, smaller, more easily integrated into a complex and demanding on the volume control device which. The Z80 INTEL is the first designed in accordance with this idea processor, then on the development of microcontroller and dedicated processors will be parting ways. Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performance was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, but not ideal because the cost has not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been the rapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90s dedicated processor, while the average model prices fall to one U.S. dollar, the most high-end [1] model only 10 dollars. Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems. SCM is more suitable than the specific processor used in embedded systems, so it was up to the application. In fact the number of SCM is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will be integrated single chip. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse with a 1-2 in both the Department of SCM. Personal computer will have a large number of SCM in the work. General car with more than 40 microcontroller, a complex industrial control systems may even hundreds of single chip at the same time work! SCM is not only far exceeds the number of PC and other computing the sum, or even more than the number of human beings. Single chip, also known as single-chip microcontroller, it is not complete a certain logic chips, but to a computer system integrated into a chip. Equivalent to a
外文翻译---51系列单片机的结构和功能
外文翻译---51系列单片机的结构和功能
外文资料翻译 英文原文： Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers . An one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). (2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. (4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction, may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command center, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing devices temporarily of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a expresses in the order. The controller includes the procedure counter, the order is deposited, the