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AK5358A中文资料

GENERAL DESCRIPTION

The AK5358A is a stereo A/D Converter with wide sampling rate of 8kHz ～ 96kHz and is suitable for consumer to professional audio system. The AK5358A achieves high accuracy and low cost by using Enhanced dual bit ΔΣ techniques. The AK5358A requires no external components because the analog inputs are single-ended. The audio interface has two formats (MSB justified, I 2S) and can correspond to various systems like DTV, DVR and AV Receiver.

FEATURES

Linear Phase Digital Anti-Alias Filtering Single-ended Input

Digital HPF for DC-Offset cancel S/(N+D): 92dB DR: 102dB S/N: 102dB

Sampling Rate Ranging from 8kHz to 96kHz Master Clock:

256fs/384fs/512fs/768fs (8kHz ～ 48kHz) 256fs/384fs (48kHz ～ 96kHz)

Input level: TTL/CMOS Master / Slave Mode

Audio Interface: 24bit MSB justified / I 2S selectable Power Supply: 4.5 ～ 5.5V (Analog), 2.7 ～ 5.5V (Digital) Ta = ?20 ～ 85°C

Small 16pin TSSOP Package AK5357/58/59/81 Pin-compatible

AINL

LRCK SCLK

SDTO

VCOM

AINR

96kHz 24-Bit ΔΣADC

AK5358A

■ Ordering Guide

AK5358AET ?20 ～ +85°C 16pin TSSOP (0.65mm pitch)

AKD5358A Evaluation Board for AK5358A

■ Pin Layout

CKS1VCOM VD DGND

AINR AINL AGND VA Top View

76543219

10111213141516DIF PDN LRCK MCLK SCLK CKS2CKS0SDTO

■ Compatibility with AK5357, AK5358, AK5359 and AK5381

AK5357 AK5358 AK5358A AK5381 AK5359 fs 4kHz to 96kHz 8kHz to 96kHz 8kHz to 96kHz 4kHz to 96kHz 8kHz to 216kHz S/(N+D) 88dB 92dB 92dB 96dB 94dB DR 102dB 102dB 102dB 106dB 102dB VIH@TTL Level

Mode

2.2V 2.2V 2.2V 2.4V Not Available

VA (Analog

Supply)

2.7 to 5.5V 4.5 to 5.5V 4.5 to 5.5V 4.5 to 5.5V 4.5 to 5.5V

2.7 to 5.5V

VD (Digital Supply) 2.7 to 5.5V 2.7 to 3.6V 2.7 to 5.5V 3.0 to 5.5V

@96kHz

3.0 to 5.5V HPF Disable Available Not Available Not Available Available Available Operating Temperature ET: ?20 ～ +85°C VT: ?40 ～ +85°C ET: ?20 ～ +85°C ET: ?20 ～ +85°C ET: ?20 ～ +85°C VT: ?40 ～ +85°C XT: ?40 ～ +85°C

ET: ?20 ～ +85°C

VT: ?40 ～ +85°C

PIN / FUNCTION

No. Pin Name I/O Function

1 AINR I Rch Analog Input Pin

2 AINL I Lch Analog Input Pin

3 CKS1 I Mode Select 1 Pin

4 VCOM O Common Voltage Output Pin, VA/2 Bias voltage of ADC input.

5 AGND - Analog Ground Pin

6 VA - Analog Power Supply Pin, 4.5 ～ 5.5V

7 VD - Digital Power Supply Pin, 2.7 ～ 5.5V

8 DGND - Digital Ground Pin

9 SDTO O Audio Serial Data Output Pin

“L” Output at Power-down mode.

10 LRCK I/O Output Channel Clock Pin

“L” Output in Master Mode at Power-down mode.

11 MCLK I Master Clock Input Pin

12 SCLK I/O Audio Serial Data Clock Pin

“L” Output in Master Mode at Power-down mode.

13 PDN I Power Down Mode & Reset Pin

“H”: Power up, “L”: Power down & Reset

The AK5358A must be reset once upon power-up.

14 DIF I Audio Interface Format Pin

“H”: 24bit I2S Compatible, “L”: 24bit MSB justified

15 CKS2 I Mode Select 2 Pin

16 CKS0 I Mode Select 0 Pin

Note: All input pins except analog input pins (AINR, AINL) should not be left floating.

■ Handling of Unused Pin

The unused input pins should be processed appropriately as below.

Classification Pin

Name Setting

AINL This pin should be open.

Analog

AINR This pin should be open.

ABSOLUTE MAXIMUM RATINGS

(AGND, DGND=0V; Note 1)

Parameter Symbol

min

max

Units

Power Supplies: Analog

Digital

|AGND – DGND| (Note 2)

ΔGND

?0.3

6.0

0.3

Input Current, Any Pin Except Supplies IIN - ±10 mA

Analog Input Voltage (AINL, AINR, CKS1 pins)VINA ?0.3 VA+0.3 V

Digital Input Voltage (Note 3) VIND ?0.3 VD+0.3 V

Ambient Temperature (powered applied) Ta ?20 85 °C

Storage Temperature Tstg ?65 150 °C

Note 1. All voltages with respect to ground.

Note 2. AGND and DGND must be connected to the same analog ground plane.

Note 3. PDN, DIF, MCLK, SCLK, LRCK, CKS0, CKS2 pins

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(AGND, DGND=0V; Note 1)

Parameter Symbol min

typ

max

Units

Power Supplies (Note 4) Analog

Digital

4.5

2.7

5.0

5.5

Note 4. The power up sequence between VA and VD is not critical.

WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.

ANALOG CHARACTERISTICS

(Ta=25°C; VA=5.0V, VD=5.0V; AGND=DGND=0V; fs=48kHz, 96kHz; SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ～ 20kHz at fs=48kHz, 40Hz ～ 40kHz at fs=96kHz; unless otherwise specified)

Parameter min typ max Units ADC Analog Input Characteristics:

Resolution 24 Bits Input Voltage (Note 5) 2.7 3.0 3.3 Vpp ?1dBFS 82 92 dB fs=48kHz BW=20kHz ?60dBFS - 39 dB

?1dBFS - 90 dB S/(N+D) fs=96kHz

BW=40kHz ?60dBFS - 38 dB

DR (?60dBFS, A-weighted) 94 102 dB S/N (A-weighted) 94 102 dB fs =

48kHz 13 20 k Ω Input Resistance fs =96kHz 9 14 k Ω Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0.1 0.5 dB Gain Drift 100 - ppm/°C Power Supply Rejection (Note 6) - 50 dB Power Supplies

Power Supply Current Normal Operation (PDN pin = “H”) VA VD (fs=48kHz) (Note 7) VD (fs=96kHz) (Note 8)

Power down mode (PDN pin = “L”) (Note 9)

VA+VD

12 3 6 10 18 5 9 100 mA mA mA μA Note 5. This value is the full scale (0dB) of the input voltage. Input voltage is proportional to VA voltage. Vin = 0.6 x VA (Vpp).

Note 6. PSR is applied to VA and VD with 1kHz, 50mVpp. Note 7. VD=2mA@3V Note 8. VD=4mA@3V

Note 9. All digital input pins and CKS1 pin are held VD or DGND.

FILTER CHARACTERISTICS (fs=48kHz)

(Ta=-20°C ～ 85°C; VA=4.5 ～ 5.5V; VD=2.7 ～ 5.5V)

Parameter Symbol

min

typ

max

Units ADC Digital Filter (Decimation LPF):

Passband (Note 10)±0.1dB

?0.2dB

?3.0dB PB 0

20.0

23.0

18.9

kHz

Stopband SB

28 kHz Passband Ripple PR ±0.04 dB

Stopband Attenuation SA 68 dB

Group Delay Distortion ΔGD 0 μs

Group Delay (Note 11) GD 16 1/fs

ADC Digital Filter (HPF):

Frequency Response (Note 10) ?3dB

?0.1dB FR 1.0

6.5

FILTER CHARACTERISTICS (fs=96kHz)

(Ta=-20°C ～ 85°C; VA=4.5 ～ 5.5V; VD=2.7 ～ 5.5V)

Parameter Symbol

min

typ

max

Units ADC Digital Filter (Decimation LPF):

Passband (Note 10) ±0.1dB

?0.2dB

?3.0dB PB 0

40.0

46.0

37.8

kHz

Stopband SB

56 kHz Passband Ripple PR ±0.04 dB

Stopband Attenuation SA 68 dB

Group Delay Distortion ΔGD 0 μs

Group Delay (Note 11) GD 16 1/fs

ADC Digital Filter (HPF):

Frequency Response (Note 10) ?3dB

?0.1dB FR 2.0

13.0

Note 10. The passband and stopband frequencies scale with fs.

For example, PB=18.9kHz@±0.1dB is 0.39375 × fs.

Note 11. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC.

DC CHARACTERISTICS (CMOS Level Mode)

(Ta=-20°C ～ 85°C; VA=4.5 ～ 5.5V; VD=2.7 ～ 5.5V)

Parameter Symbol

min

typ

max

Units

High-Level Input Voltage Low-Level Input Voltage VIH

VIL

70%VD

30%VD

High-Level Output Voltage (Iout=?1mA) Low-Level Output Voltage (Iout=1mA)VOH

VOL

VD?0.5

0.5

Input Leakage Current Iin - - ±10 μA

DC CHARACTERISTICS (TTL Level Mode)

(Ta=-20°C ～ 85°C; VA=4.5 ～ 5.5V; VD=4.5 ～ 5.5V)

Parameter Symbol

min

typ

max

Units

High-Level Input Voltage (CKS2-0 pins) (All pins except CKS2-0 pins) Low-Level Input Voltage (CKS2-0 pins) (All pins except CKS2-0 pins)VIH

VIH

VIL

70%VD

2.2

30%VD

0.8

High-Level Output Voltage (Iout=?1mA) Low-Level Output Voltage (Iout=1mA)VOH

VOL

VD?0.5

0.5

Input Leakage Current Iin - - ±10 μA

SWITCHING CHARACTERISTICS

(Ta=-20°C ～ 85°C; VA=4.5 ～ 5.5V; VD=2.7 ～ 5.5V; C L=20pF)

Parameter Symbol min

typ

max

Units

Master Clock Timing

512fs, 256fs Frequency Pulse Width Low Pulse Width High 768fs, 384fs Frequency Pulse Width Low Pulse Width High

fCLK

tCLKL

tCLKH

fCLK

tCLKL

tCLKH

2.048

3.072

10.5

24.576

36.864

MHz

LRCK Frequency fs

kHz

Duty Cycle Slave mode

Master mode 45

55 %

Audio Interface Timing Slave mode

SCLK Period

SCLK Pulse Width Low

Pulse Width High

LRCK Edge to SCLK “↑” (Note 12) SCLK “↑” to LRCK Edge (Note 12) LRCK to SDTO (MSB) (Except I2S mode) SCLK “↓” to SDTO

tSCK

tSCKL

tSCKH

tLRSH

tSHLR

tLRS

tSSD

160

Master mode

SCLK Frequency SCLK Duty

SCLK “↓” to LRCK SCLK “↓” to SDTO

fSCK

dSCK

tMSLR

tSSD

?20

64fs

Reset Timing

PDN Pulse Width (Note 13) PDN “↑” to SDTO valid at Slave Mode (Note 14) PDN “↑” to SDTO valid at Master Mode (Note 14)

tPD

tPDV

150

4132

4129

1/fs

Note 12. SCLK rising edge must not occur at the same time as LRCK edge. Note 13. The AK5358A can be reset by bringing the PDN pin = “L”.

Note 14. This cycle is the number of LRCK rising edges from the PDN pin = “H”.

■ Timing Diagram

MCLK

LRCK

SCLK

Clock Timing

LRCK VIH VIL

SCLK VIH VIL

SDTO50%VD

Audio Interface Timing (Slave mode)

LRCK SCLK

50%VD

SDTO

50%VD

Audio Interface Timing (Master mode)

PDN

VIL

PDN

VIH

VIL

SDTO

50%VD

Power Down & Reset Timing

OPERATION OVERVIEW

■ System Clock

MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. MCLK frequency, SCLK frequency and master/slave are selected by CKS2-0 pins as shown in Table 2. All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided, the AK5358A may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK5358A in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be provided unless PDN pin = “L”.

MCLK

256fs 384fs 512fs 768fs

32kHz 8.192MHz 12.288MHz 16.384MHz 24.576MHz

44.1kHz 11.2896MHz16.9344MHz22.5792MHz33.8688MHz

48kHz 12.288MHz 18.432MHz 24.576MHz 36.864MHz

96kHz 24.576MHz 36.864MHz N/A N/A

Table 1. System Clock Example

Mode CKS2 CKS1 CKS0 Input

Level Master/Slave MCLK SCLK

0 L L L CMOS Slave 256/384fs (8k≤fs≤96k)

512/768fs (8k≤fs≤48k)

≥ 48fs or 32fs

(Note 15)

1 L L H Reserved

2 L H L CMOS Master 256fs (8k≤fs≤96k) 64fs

3 L H H CMOS Master 512fs (8k≤fs≤48k) 64fs

4 H L L TTL Slave 256/385fs(～ 96kHz)

512/768fs(～ 48kHz)

≥ 48fs or 32fs

(Note 15)

5 H L H Reserved

6 H H L CMOS Master 384fs (8k≤fs≤96k) 64fs

7 H H H CMOS Master 768fs (8k≤fs≤48k) 64fs

Table 2. Operation Mode Select

Note 15. SDTO outputs 16bit data at SCLK=32fs.

■ Audio Interface Format

Two kinds of data formats can be chosen with the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK frequency fixed to 1fs.

pin SDTO LRCK SCLK Figure

Mode DIF

0 L 24bit, MSB justified H/L ≥ 48fs or 32fs Figure 1

I2S Compatible L/H ≥ 48fs or 32fs Figure 2

24bit,

1 H

Table 3. Audio Interface Format

BICK(64fs)

SDTO(o)

Figure 1. Mode 0 Timing

LRCK

BICK(64fs)

SDTO(o)

Figure 2. Mode 1 Timing

■ Digital High Pass Filter

The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz (@fs=48kHz) and scales with sampling rate (fs).

■ Power down

The AK5358A is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same time. This reset should always be done after power-up. In the power-down mode, the VCOM are AGND level. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after 4129 cycles of LRCK clock in master mode or 4132 cycles of LRCK clock in slave mode. During initialization, the ADC digital data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle in the data corresponding to the input signals after the end of initialization (Settling approximately takes the group delay time).

PDN

Internal

State

A/D In

(Analog)

A/D Out

(Digital)

Clock In

MCLK,LRCK,SCLK

Notes:

(1) 4132/fs in slave mode and 4129/fs in master mode.

(2) Digital output corresponding to analog input has the group delay (GD).

(3) A/D outputs “0” data at the power-down state.

(4) When the external clocks (MCLK, SCLK and LRCK) are stopped, the AK5358A should be in the power-down state.

Figure 3. Power-down/up sequence example

■ System Reset

The AK5358A should be reset once by bringing PDN pin “L” after power-up. In slave mode, the internal timing starts clocking by the rising edge (falling edge at mode 1) of LRCK after exiting from reset and power down state by MCLK. The AK5358A is power down state until LRCK is input. In master mode, the internal timing starts when MCLK is input.

SYSTEM DESIGN

Figure 4 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.

Lch In

Rch In

Note:

- AGND and DGND of the AK5358A should be distributed separately from the ground of external digital devices (MPU, DSP etc.).

- All digital input pins should not be left floating.

- The CKS1 pin should be connected to VA or AGND.

Figure 4. Typical Connection Diagram

Figure 5. Ground Layout

Note:

- AGND and DGND must be connected to the same analog ground plane.

1. Grounding and Power Supply Decoupling

The AK5358A requires careful attention to power supply and grounding arrangements. Alternatively if VA and VD are supplied separately, the power up sequence is not critical. AGND and DGND of the AK5358A must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5358A as possible, with the small value ceramic capacitor being the nearest.

2. Voltage Reference

The voltage input to VA sets the analog input range. VCOM are 50%VA and normally connected to AGND with a 0.1μF ceramic capacitor. A capacitor 2.2μF is attached to VCOM pin. No load current may be drawn from these pins. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the

AK5358A.

3. Analog Inputs

The ADC inputs are single-ended and internally biased to the common voltage (50%VA) with 20kΩ (typ@fs=48kHz) resistance. The input signal range scales with the supply voltage and nominally 0.6xVA Vpp (typ). The ADC output data format is 2’s complement. The internal HPF removes the DC offset.

The AK5358A samples the analog inputs at 64fs (@fs=48kHz). The digital filter rejects noise above the stop band except for multiples of 64fs. The AK5358A includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.

16pin TSSOP (Unit: mm)

■ Material & Lead finish

Package molding compound: Epoxy

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

1) Pin #1 indication

2) Date Code: XXYYY (5 digits)

XX: Lot#

YYY: Date Code

3) Marketing Code: 5358AET

REVISION HISTORY

Date (YY/MM/DD) Revision Reason Page Contents

First

Edition

06/06/02 00

07/04/13 01 Error Correction 4 Absolute Maximum Ratings

Power Supplies: Digital 4.6 → 6.0