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V436632S04VTG-10PC中文资料

MOSEL VITELIC

V436632S04VTG-10PC

3.3 VOLT 32M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE

PRELIMINARY

Features

s 168 Pin Unbuffered 33,554,432 x 64 bit Oganization SDRAM Modules

s Utilizes High Performance 32M x 8 SDRAM in TSOPII-54 Packages

s Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification

s Single +3.3V (± 0.3V) Power Supply

s Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) s Auto Refresh (CBR) and Self Refresh s All Inputs, Outputs are LVTTL Compatible s 8192 Refresh Cycles every 64 ms s Serial Present Detect (SPD) Description

The V436632S04VTG-10PC memory module is organized 33,554,432 x 64 bits in a 168 pin dual in line memory module (DIMM). The 32M x 64 unbuf-fered DIMM uses 8 Mosel-Vitelic 32M x 8 SDRAM.The x64 modules are ideal for use in high perfor-mance computer systems where increased memory density and fast access times are required.

s SDRAM Performance

s Module Frequency vs AC Parameter

Key Component Timing Parameters

-8PC

Units

t CK Clock Frequency (max.)125MHz t AC Clock Access Time CAS Latency = 36ns t AC

Latency = 2

Frequency

(CAS Latency)

t RCD

t RP

Unit

V436632S04VTG-10PC

100 MHz (PC)

3227CLK 2

CLK

MOSEL VITELIC

V436632S04VTG-10PC

Pin Configurations (Front Side/Back Side)

Notes:

* These pins are not used in this module.

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 12345678910111213141516171819202122232425262728

VSS I/O1I/O2I/O3I/O4VCC I/O5I/O6I/O7I/O8I/O9VSS I/O10I/O11I/O12I/O13I/O14VCC I/O15I/O16CBO*CB1*VSS NC NC VCC WE DQM0

29303132333435363738394041424344454647484950515253545556

DQM1CS0DU VSS A0A2A4A6A8A10(AP)BA1VCC VCC CLK0VSS DU CS2DQM2DQM3DU VCC NC NC CB2*CB3*VSS I/O17I/O18

57585960616263646566676869707172737475767778798081828384

I/O19I/O20VCC I/O21NC DU CKE1VSS I/O22I/O23I/O24VSS I/O25I/O26I/O27I/O28VCC I/O29I/O30I/O31I/O32VSS CLK2NC WP SDA SCL VCC

858687888990919293949596979899100101102103104105106107108109110111112

VSS I/O33I/O34I/O35I/O36VCC I/O37I/O38I/O39I/O40I/O41VSS I/O42I/O43I/O44I/O45I/O46VCC I/O47I/O48CB4*CB5*VSS NC NC VCC CAS DQM4

113114115116117118119120121122123124125126127128129130131132133134135136137138139140

DQM5CS1RAS VSS A1A3A5A7A9BA0A11VCC CLK1A12VSS CKE0CS3DQM6DQM7DU VCC NC NC CB6*CB7*VSS I/O49I/O50

141142143144145146147148149150151152153154155156157158159160161162163164165166167168

I/O51I/O52VCC I/O53NC DU NC VSS I/O54I/O55I/O56VSS I/O57I/O58I/O59I/O60VCC I/O61I/O62I/O63I/O64VSS CLK3NC SA0SA1SA2VCC

Pin Names

A0–A12Address Inputs I/O1–I/O64Data Inputs/Outputs RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input BA0, BA1Bank Selects CKE0, CKE1Clock Enable CS0–CS3Chip Select CLK0–CLK3Clock Input DQM0–DQM7Data Mask VCC Power (+3.3 Volts)VSS Ground

SCL

Clock for Presence Detect

SDA

Serial Data OUT for Presence Detect

SA0–A2Serial Data IN for Presence Detect

CB0–CB7Check Bits (x72 Organization)NC No Connection DU Don’t Use

MOSEL VITELIC V436632S04VTG-10PC Module Part Number Information

Block Diagram

MOSEL VITELIC V436632S04VTG-10PC Serial Presence Detect Information

A serial presence detect storage device -E2PROM - is assembled onto the module. Informa-tion about the module configuration, speed, etc. is written into the E2PROM device during module pro-duction using a serial presence detect protocol (I2C synchronous 2-wire bus)

SPD-Table:

Byte

Number Function Described SPD Entry Value Hex Value 100 MHz -10PC

0Number of SPD bytes12880

1Total bytes in Serial PD25608 2Memory Type SDRAM04 3Number of Row Addresses (without BS bits)130D 4Number of Column Addresses (for x8 SDRAM)100A 5Number of DIMM Banks101 6Module Data Width6440 7Module Data Width (continued)000 8Module Interface Levels LVTTL01 9SDRAM Cycle Time at CL=310.0 ns A0 10SDRAM Access Time from Clock at CL=3 6.0 ns60 11Dimm Config (Error Det/Corr.)none00 12Refresh Rate/Type Self-Refresh, 15.6μs80 13SDRAM width, Primary x808 14Error Checking SDRAM Data Width n/a / x800

15Minimum Clock Delay from Back to Back

Random Column Address

t ccd = 1 CLK01 16Burst Length Supported1, 2, 4, 8, full page8F 17Number of SDRAM Banks404 18Supported CAS Latencies CL = 2 & 306 19CS Latencies CS Latency = 001 20WE Latencies WL = 001 21SDRAM DIMM Module Attributes Non Buffered/Non Reg.00 22SDRAM Device Attributes: General Vcc tol ± 10%0E 23Minimum Clock Cycle Time at CAS Latency = 210.0 ns A0 24Maximum Data Access Time from Clock for CL = 2 6.0 ns60 25Minimum Clock Cycle Time at CL = 1Not Supported00 26Maximum Data Access Time from Clock at CL = 1Not Supported00 27Minimum Row Precharge Time t RP20 ns14 28Minimum Row Active to Row Active Delay t RRD16 ns10 29Minimum RAS to CAS Delay t RCD20 ns14

MOSEL VITELIC

V436632S04VTG-10PC

DC Characteristics

T A = 0 ° C to 70 ° C; V SS = 0 V; V DD , V DDQ = 3.3V ± 0.3V

30Minimum RAS Pulse Width t RAS 45 ns 2D 31Module Bank Density (Per Bank)256 MByte 4032SDRAM Input Setup Time 2 ns 2033SDRAM Input Hold Time 1 ns 1034SDRAM Data Input Setup Time 2 ns 2035SDRAM Data Input Hold Time

1 ns

1036-61Superset Information (May be used in Future)00

62SPD Revision

Revision 1.21263Checksum for Bytes 0 - 62

7C 64-125Manufacturers’s Information (Optional)00

126Max. Frequency Specification 100 MHz 64127100 MHz Support Details AF 128+

Unused Storage Location

Symbol

Parameter

Limit Values

Unit

Min.

Max.

V IH Input High Voltage 2.0V CC +0.3V V IL Input Low Voltage

–0.50.8V V OH Output High Voltage (I OUT = –4.0 mA) 2.4—V V OL Output Low Voltage (I OUT = 4.0 mA)—0.4V I I(L) Input Leakage Current, any input

(0 V < V IN < 3.6 V, all other inputs = 0V)–4040 μ A I O(L)

Output leakage current

(DQ is disabled, 0V < V OUT < V CC )

–40

μ A

SPD-Table: (Continued)

Byte Number

Function Described

SPD Entry Value

Hex Value

100 MHz -10PC

MOSEL VITELIC V436632S04VTG-10PC Capacitance

T A = 0°C to 70°C; V DD = 3.3V ± 0.3V, f = 1 MHz

Symbol Parameter Limit Values Unit

C I1Input Capacitance (A0 to A11, RAS, CAS, WE)85pF

C I2Input Capacitance (CS0-CS3)30pF

C ICL Input Capacitance (CLK0-CLK3)22pF

C I3Input Capacitance (CKE0, CKE1)50pF

C I4Input Capacitance (DQM0-DQM7)20pF

C IO Input/Output Capacitance (I/O1-I/064)20pF

C SC Input Capacitance (SCL, SA0-2)8pF

C S

D Input/Output Capacitance18pF

Absolute Maximum Ratings

Parameter Max.Units Voltage on VDD Supply Relative to V SS-1 to 4.6V Voltage on Input Relative to V SS-1 to 4.6V Operating Temperature0 to +70°C Storage Temperature-55 to 125°C Power Dissipation6W

MOSEL VITELIC V436632S04VTG-10PC Standby and Refresh Currents1

T A = 0°C to 70°C, V CC = 3.3V ± 0.3V

Symbol Parameter Test Conditions32M x 64Unit Note

I CC1Operating Current Burst length = 4, CL = 3

t RC> = t RC(min),

t CK> = t CK(min), IO = 0 mA

2 Bank Interleave Operation

1360mA1,2

I CC2P Precharged Standby Current in Power

Down Mode

CKE< = V IL(max), t CK> = t CK(min)16mA

I CC2N Precharged Standby Current in

Non-Power Down Mode CKE> = V IH(min), t CK> = t CK(min), Input

changed once in 3 cycles

240mA CS =

High

I CC3P Active Standby Current in Power

Down Mode

CKE< = V IL(max), t CK> = t CK(min)80mA

I CC3N Active Standby Current in Non-Power

Down Mode CKE> = V IH(min), t CK> = t CK(min), Input

changed one time

228mA CS =

High

I CC4Burst Operating Current Burst length = Full Page,

t RC = Infinite, CL = 3,

t CK> = t CK(min), IO = 0 mA

2 Banks Activated

960mA1, 2

I CC5Auto Refresh Current t RC>= t RC(min)1760mA1,2 I CC6Self Refresh Current CKE = <0,2 V Standard24mA1,2

L version12mA1,2

AC Characteristics3,4

T A = 0° to 70°C; V SS = 0V; V CC = 3.3V ± 0.3V, t T = 1 ns

#Symbol Parameter

Limit Values

Unit Note -10PC

Min.Max.

Clock and Clock Enable

1t CK Clock Cycle Time

CAS Latency = 3 CAS Latency = 210

2f CK System frequency

CAS Latency = 3 CAS Latency = 2–

–

100

MHz

3t AC Clock Access Time

CAS Latency = 3 CAS Latency = 2–

–

4,5

4t CH Clock High Pulse Width3–ns6 5t CL Clock Low Pulse Width3–ns6 6t CS Input Setup time2–ns7 7t CH Input Hold Time1–ns7 8t CKSP CKE Setup Time (Power down mode) 2.5–ns8 9t CKSR CKE Setup Time (Self Refresh Exit)8–ns9 10t T Transition time (rise and fall)1–ns Common Parameters

11t RCD RAS to CAS delay20–ns

12t RC Cycle Time70120k ns

13t RAS Active Command Period45–ns

14t RP Precharge Time20–ns

15t RRD Bank to Bank Delay Time16–ns

16t CCD CAS to CAS delay time (same bank)1–CLK Refresh Cycle

17t SREX Self Refresh Exit Time10–ns9 18t REF Refresh Period (8192 cycles)64–ms8 Read Cycle

19t OH Data Out Hold Time3–ns4 20t LZ Data Out to Low Impedance Time0–ns

21t HZ Data Out to High Impedance Time39ns10 22t DQZ DQM Data Out Disable Latency2–CLK

Write Cycle

23t DPL Data input to Precharge (write recovery)2–CLK

24t DAL Data In to Active/refresh5–CLK11 25t DQW DQM Write Mask Latency0–CLK

Notes:

1.The specified values are valid when addresses are changed no more than once during t CK (min.) and when No

Operation commands are registered on every rising clock edge during t RC (min). Values are shown per module bank.2.The specified values are valid when data inputs (DQ’s) are stable during t RC (min.).

3.All AC characteristics are shown for device level.

An initial pause of 100 μs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.4.AC timing tests have V IL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition

time is measured between V IH and V IL . All AC measurements assume t T = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V.

5.If clock rising time is longer than 1 ns, a time (t T /2 -0.5) ns has to be added to this parameter.

6.Rated at 1.5V

7.If t T is longer than 1 ns, a time (t T -1) ns has to be added to this parameter.

8.Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be

given to “wake-up” the device.9.Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.

Self Refresh Exit is not complete until a time period equal to t RC is satisfied once the Self Refresh Exit command is registered.10.

Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.

11.t DAL is equivalent to t DPL + t RP .

1.4V

CLOCK

INPUT OUTPUT

50 pF

I/O

50 Ohm

I/O

Measurement conditions for

tac and toh

50 pF

Package Diagram

L-DIM-168-30

SDRAM DIMM Module Package

Label Information

MOSEL VITELIC

WORLDWIDE OFFICES

V436632S04VTG-10PC

8/00

Printed in U.S.A.

The information in this document is subject to change without notice.

MOSEL VITELIC makes no commitment to update or keep cur-rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.

MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica-tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil-ity for consequential or incidental arising from any use of its prod-ucts. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.

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