IDT74FCT273C中文资料

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MAY 1992

?1992 Integrated Device Technology, Inc.

7.10

DSC-4609/2

?IDT54/74FCT273 equivalent to FAST ? speed;?IDT54/74FCT273A 45% faster than FAST ?IDT54/74FCT273C 55% faster than FAST

?Equivalent to FAST output drive over full temperature and voltage supply extremes

?I OL = 48mA (commercial) and 32mA (military)?CMOS power levels (1mW typ. static)?TTL input and output level compatible ?CMOS output level compatible

?Substantially lower input current levels than FAST (5μA max.)

?Octal D flip-flop with Master Reset

?JEDEC standard pinout for DIP and LCC

?Product available in Radiation Tolerant and Radiation Enhanced versions

?

Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT273/A/C are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/74FCT273/A/C have eight edge-triggered D-type flip-flops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR ) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s O output.

All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

FUNCTIONAL BLOCK DIAGRAM

2558 drw 01

7

6543

210

PIN CONFIGURATIONS

D 0D 1O 1Vcc D 7O 2D 2D 3O 3CP

D 6O 6O 5D 5D 4GND

O 4O 0O 72558 drw 02

D 7O 3

C P

D 6O 6O 5D 5

D 4

G N D O 4

The IDT logo is a registered trademark of Integrated Device Technology, Inc.FAST is a registered trademark of National Semiconductor Co.

DIP/SOIC/CERPACK

TOP VIEW

LCC TOP VIEW

1

7.102

NOTES:2558 tbl 06H =HIGH voltage level steady-state

h =HIGH voltage level one set-up time prior to the LOW-to-HIGH clock

transition

L =LOW voltage level steady state

l =LOW voltage level one set-up time prior to the LOW-to-HIGH clock

transition X =Don’t care

↑ =LOW-to-HIGH clock transition

2558 tbl 05

(1)

NOTES:2558 tbl 011.Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed V CC by +0.5V unless otherwise noted.2.Input and V CC terminals only.3.Outputs and I/O terminals only.

NOTE:2558 tbl 021.This parameter is guaranteed by characterization data and not tested.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:V LC = 0.2V; V HC = V CC – 0.2V

NOTES:2558 tbl 03

1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2.Typical values are at V CC = 5.0V, +25°C ambient and maximum loading.

3.Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4.This parameter is guaranteed but not tested.

7.103

POWER SUPPLY CHARACTERISTICS

NOTES:2558 tbl 04

1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2.Typical values are at V CC = 5.0V, +25°C ambient.

3.Per TTL driven input (V IN = 3.4V); all other inputs at V CC or GND.

4.This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

5.Values for these conditions are examples of the I CC formula. These limits are guaranteed but not tested.

6.I C = I QUIESCENT + I INPUTS + I DYNAMIC

I C = I CC + ?I CC D H N T + I CCD (f CP/2 + f i N i)

I CC = Quiescent Current

?I CC = Power Supply Current for a TTL High Input (V IN = 3.4V)

D H = Duty Cycle for TTL Inputs High

N T = Number of TTL Inputs at D H

I CCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)

f CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f i = Input Frequency

N i = Number of Inputs at f i

All currents are in milliamps and all frequencies are in megahertz.

7.104

2558 tbl 07

1.See test circuit and waveforms.

2.Minimum limits are guaranteed but not tested on Propagation Delays.

7.105

7.106

TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS

ENABLE AND DISABLE TIMES

PROPAGATION DELAY

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

DATA INPUT

TIMING INPUT

PRESET CLEAR ETC.

PRESET CLEAR

CLOCK ENABLE

ETC.

3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V

7.0V

SAME PHASE INPUT TRANSITION

3V 1.5V

0V 1.5V V OH V OL OUTPUT

OPPOSITE PHASE INPUT TRANSITION

3V 1.5V 0V 3.5V 0V

V OL V OH 3V 1.5V 0V

ENABLE

DISABLE

1.5V

1.5V

NOTES 2558 drw 041.Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

2.Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; Z O ≤ 50?; t F ≤ 2.5ns;

t R ≤ 2.5ns.

SWITCH POSITION

Test Switch Open Drain Disable Low Closed Enable Low All Other Tests

Open

DEFINITIONS:2558 tbl 08C L =Load capacitance: includes jig and probe capacitance.

R T =Termination resistance: should be equal to Z OUT of the Pulse

Generator.

7.107

ORDERING INFORMATION

XX

X Package

X Process

Blank B Commercial

MIL-STD-883, Class B P D SO L E Plastic DIP CERDIP

Small Outline IC

Leadless Chip Carrier CERPACK

273273A 273C Octal D Flip-Flop w/Clear

Fast Octal D Flip-Flop w/Clear

Super Fast Octal D Flip-Flop w/Clear X Device

2558 drw 03

–55°C to +125°C 0°C to +70°C

5474

Temperature FCT

IDT