FPD750DFN中文资料

?PERFORMANCE (1850 MHz)

?24 dBm Output Power (P1dB)

?20 dB Small-Signal Gain (SSG)

?0.3 dB Noise Figure at 25% Bias

?39 dBm Output IP3 at 50% Bias

?45% Power-Added Efficiency

?Evaluation Boards Available

?Featuring Lead Free Finish Package

?DESCRIPTION AND APPLICATIONS

The FPD750DFN is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 μm x 750 μm Schottky barrier Gate, defined by high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a range of bias conditions and input power levels. The FPD750DFN is available in die form and in other packages.

Typical applications include drivers or output stages in PCS/Cellular base station high-intercept-point LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems. ?ELECTRICAL SPECIFICATIONS AT 22°C

Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL Power at 1dB Gain Compression P1dB V DS = 5 V; I DS = 50% I DSS22.5 24 dBm Small-Signal Gain SSG V DS = 5 V; I DS = 50% I DSS19 20 dB Power-Added Efficiency PAE V DS = 5 V; I DS = 50% I DSS;

P OUT = P1dB

45 %

Noise Figure NF V DS = 5 V; I DS = 50% I DSS

V DS = 5 V; I DS = 25% I DSS 0.7

0.3

1.1

0.9

dB

Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) IP3 V DS = 5V; I DS = 50% I DSS

Matched for optimal power

Matched for best IP3

37

39

dBm

Saturated Drain-Source Current I DSS V DS = 1.3 V; V GS = 0 V 180 230 280 mA Maximum Drain-Source Current I MAX V DS = 1.3 V; V GS? +1 V 375 mA Transconductance G M V DS = 1.3 V; V GS = 0 V 200 mS Gate-Source Leakage Current I GSO V GS = -5 V 1 15 μA Pinch-Off Voltage |V P| V DS = 1.3 V; I DS = 0.75 mA 0.7 1.0 1.3 V

Gate-Source Breakdown Voltage |V BDGS| I GS = 0.75 mA 12 16 V

Gate-Drain Breakdown Voltage |V BDGD| I GD = 0.75 mA 12 16 V

?ABSOLUTE MAXIMUM RATINGS1

Parameter Symbol Test Conditions Min Max Units Drain-Source Voltage V DS-3V < V GS < +0V 8 V

Gate-Source Voltage V GS0V < V DS < +8V -3 V

Drain-Source Current I DS For V DS > 2V I DSS mA Gate Current I G Forward or reverse current 7.5 mA

RF Input Power2P IN Under any acceptable bias state 175 mW Channel Operating Temperature T CH Under any acceptable bias state 175 oC Storage Temperature T STG Non-Operating Storage -40 150 oC

Total Power Dissipation P TOT See De-Rating Note below 1.50 W Gain Compression Comp. Under any bias conditions 5 dB Simultaneous Combination of Limits3 2 or more Max. Limits 80 %

T Ambient = 22°C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1

3Users should avoid exceeding 80% of 2 or more Limits simultaneously

Notes:

?Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device.

?Total Power Dissipation defined as: P TOT≡ (P DC + P IN) – P OUT, where:

P DC: DC Bias Power

P IN: RF Input Power

P OUT: RF Output Power

?Total Power Dissipation to be de-rated as follows above 22°C:

P TOT= 1.50W – (0.011W/°C) x T PACK

where T PACK = source tab lead temperature above 22°C

(coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65°C source lead temperature: P TOT = 1.50W – (0.011 x (65 – 22)) = 1.03W

?The use of a filled via-hole directly beneath the exposed heatsink tab on the bottom of the package is strongly recommended to provide for adequate thermal management. Ideally the bottom of the circuit board is affixed to a heatsink or thermal radiator

?HANDLING PRECAUTIONS

To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model.

Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.

?APPLICATIONS NOTES & DESIGN DATA

Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. Evaluation Boards available upon request.

?BIASING GUIDELINES

?Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased.

Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information.

?Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD750DFN.

?For standard Class A operation, a 50% of I DSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at 50% of I DSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of I DSS range is suggested. Such Class AB operation will not degrade the IP3 performance.

?(dimensions in mm)

All information and specifications subject to change without notice.

0.00

0.05

0.10

0.15

0.20

0.250.30

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Drain-Source Voltage (V)

D r a i n -S o u r c e C u r r e n t (A )

Note: The recommended method for measuring I DSS, or any particular I DS, is to set the Drain-Source voltage (V DS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which would normally distort the current measurement (this effect has been filtered from the I-V curves presented above). Setting the V DS > 1.3V will generally cause errors in the current measurements, even in stabilized circuits.

Recommendation: Traditionally a device’s I DSS rating (I DS at V GS = 0V) was used as a predictor of RF power, and for MESFETs there is a correlation between I DSS and P1dB (power at 1dB gain compression). For pHEMTs it can be shown that there is no meaningful statistical correlation between I DSS and P1dB; specifically a linear regression analysis shows r2 < 0.7, and the regression fails the F-statistic test. I DSS is sometimes useful as a guide to circuit tuning, since the S22 does vary with the quiescent operating point I DS.