Xilinx官方verilog指南
Verilog Language Support
Introduction
Introduction
Complex circuits are commonly designed using a top down methodology. Various specification levels are required at each stage of the design process. As an example, at the architectural level, a specification may correspond to
a block diagram or an Algorithmic State Machine (ASM) chart. A block or ASM stage corresponds to a register
transfer block (for example register, adder, counter, multiplexer, glue logic, finite state machine.) where the
connections are N-bit wires. Use of an HDL language like Verilog allows expressing notations such as ASM charts and circuit diagrams in a computer language. Verilog provides both behavioral and structural language structures which allow expressing design objects at high and low levels of abstraction. Designing hardware with a language like Verilog allows usage of software concepts such as parallel processing and object-oriented programming.
Verilog has a syntax similar to C and Pascal, and is supported by XST as IEEE 1364.
The Verilog support in XST provides an efficient way to describe both the global circuit and each block according to the most efficient "style". Synthesis is then performed with the best synthesis flow for each block. Synthesis in this context is the compilation of high-level behavioral and structural Verilog HDL statements into a flattened
gate-level netlist which can then be used to custom program programmable logic device such as the Virtex FPGA family from Xilinx. Different synthesis methods will be used for arithmetic blocks, glue logic, and finite state
machines.
This manual assumes that you are familiar with the basic notions of Verilog. Please refer to the IEEE Verilog HDL Reference Manual for a complete specification.
Behavioral Verilog Features
This section contains descriptions of the behavioral features of Verilog.
Variable Declaration
Variables in Verilog may be declared as integers or real. These declarations are intended only for use in test code. Verilog provides data types such as reg and wire for actual hardware description.
The difference between reg and wire is whether the variable is given its value by behavioral (reg) or structural (wire) Verilog code. Both reg and wire have a default width being one bit wide (scalar). To specify an N-bit width (vectors) for a declared reg or wire, the left and right bit positions are defined in square brackets separated by a colon.
Example:
reg [3:0] arb_priority;
wire [31:0] arb_request;
where arb_request[31] is the MSB and arb_request[0] is the LSB.
Verilog allows arrays of reg and wires to be defined as following two examples:
reg [3:0] mem_array [31:0];
The above describes an array of 32 Elements each, 4 bits wide which can be assigned via behavioral verilog code.
wire [7:0] mem_array [63:0];
The above describes an array of 64 elements each 8 bits wide which can only be assigned via structural Verilog code.
Data Types
The Verilog representation of the bit data type contains the following four values:
0: logic zero
1: logic one
x: unknown logic value
z: high impedance
XST includes support for the following Verilog data types:
Net: wire, tri, triand/wand, trior/wor
Registers: reg, integer
Supply nets: supply0, supply1
Constants: parameter
Memories
Net and registers can be either single bit (scalar) or multiple bit (vectors).
The following example gives some examples of Verilog data types (as found in the declaration section of a Verilog module).
Example 7-1 Basic Data Types
wire net1; // single bit net
reg r1; // single bit register
tri [7:0] bus1; // 8 bit tristate bus
reg [15:0] bus1; // 15 bit register
reg [7:0] mem[0:127]; // 8x128 memory register
parameter state1 = 3'b001; // 3 bit constant
Legal Statements
The following are statements that are legal in behavioral Verilog.
Variable and signal assignment:
Variable = expression
if (condition) statement
if (condition) else statement
case (expression)
constant: statement
...
default: statement
endcase
for (variable = expression; condition; variable = variable + expression) statement
while (condition) statement
forever statement
functions and tasks
Note All variables are declared as integer or reg. A variable cannot be declared as a wire. Expressions
An expression involves constants and variables with arithmetic (+, -, *, /, %), logical (&, &&, |, ||, ^, ~, <<, >>), relational (<, ==, ===, <=, >=, !=, !==, >), and conditional (?) operators. The logical operators are further divided as bit-wise versus logical depending on whether it is applied to an expression involving several bits or a single bit. The following table lists the expressions supported by XST.
Table 7-1 Expressions
Concatenation{}Supported
Replication{{}}Supported
Arithmetic
+, -, *Supported
/Supported only if second operand is a power of 2
Modulus%Supported only if second operand is a power of 2
Addition+Supported
Subtraction-Supported
Multiplication*Supported
Division/Supported
XST generates incorrect logic for the division operator between signed and unsigned constants. Example: -1235/3'b111
Remainder%Supported
Relational>, <,
>=, <=Supported
Logical
Negation!Supported Logical AND&&Supported
Logical OR||Supported
Logical
Equality==Supported
Logical
Inequality!=Supported Case Equality===Unsupported
Case
Inequality!==Unsupported
Bitwise
Negation~Supported Bitwise AND&Supported
Bitwise
Inclusive OR|Supported
Bitwise
Exclusive OR^Supported
Bitwise
Equivalence~^, ^~Supported
Reduction
AND&Supported
Reduction
NAND~&Supported Reduction OR|Supported
Reduction
NOR~|Supported
Reduction
XOR^Supported
Reduction
XNOR~^, ^~Supported Left Shift<
The following table lists the results of evaluating expressions using the more
frequently used operators supported by XST.
Note The (===) and (!==) are special comparison operators useful in simulations to check if a variable is assigned a value of (x) or (z). They have no meaning in hardware.
Table 7-2 Results of Evaluating Expressions
a b a==b a===b a!=b a!==b a&b a&&b a|b a||b a^b
0 0110000000
0 1001100111
0 x x0x100x x x
0 z x0x100x x x
1 000 1 100111
1 1110011110
1 x x0x1x x11x
1 z x0x1x x11x
x 0x0x100x x x
x 1x0x1x x11x
x x x1x0x x x x x
x z x0x1x x x x x
z 0x0x100x x x
z 1x0x1x x11x
z x x0x1x x x x x
z z x1x0x x x x x
Blocks
Block statements are used to group statements together. XST only supports sequential blocks. Within these blocks, the statements are executed in the order listed. Parallel blocks are not supported by XST. Block statements are designated by begin and end keywords, and are discussed within examples later in this chapter. Modules
In Verilog a design component is represented by a module. The connections between components are specified within module instantiation statements. Such a statement specifies an instance of a module. Each module instantiation statement must be given a name (instance name). In addition to the name, a module instantiation statement contains an association list that specifies which actual nets or ports are associated with which local ports (formals) of the module declaration.
All procedural statements occur in blocks that are defined inside modules. There are two kinds of procedural blocks: the initial block and the always block. Within each block, Verilog uses a begin and end to enclose the statements. Since initial blocks are ignored during synthesis, only always blocks are discussed. Always blocks usually take the following format:
always
begin
statement
.....
end
where each statement is a procedural assignment line terminated by a semicolon.
Module Declaration
In the module declaration, the I/O ports of the circuit are declared. Each port has a name and a mode (in, out, and inout) as shown in the example below.
module EXAMPLE (A, B, C, D, E);
input A, B, C;
output D;
inout E;
wire D, E;
...
assign E = oe ? A : 1'bz;
assign D = B & E;
...
endmodule
The input and output ports defined in the module declaration called EXAMPLE are the basic input and output I/O signals for the design. The inout port in Verilog is analogous to a bi-directional I/O pin on the device with the data flow for output versus input being controlled by the enable signal to the tristate buffer. The preceding example describes E as a tristate buffer with a high-true output enable signal. If oe = 1, the value of signal A will be output on the pin represented by E. If oe = 0, then the buffer is in high impedance (Z) and any input value driven on the pin E (from the external logic) will be brought into the device and fed to the signal represented by D.
Verilog Assignments
There are two forms of assignment statements in the Verilog language:
Continuous Assignments
Procedural Assignments
Continuous Assignments
Continuous assignments are used to model combinatorial logic in a concise way. Both explicit and implicit continuous assignments are supported. Explicit continuous assignments are introduced by the assign keyword after the net has been separately declared. Implicit continuous assignments combine declaration and assignment.
Note Delays and strengths given to a continuous assignment are ignored by XST.
Example of an explicit continuous assignment:
wire par_eq_1;
.....
assign par_eq_1 = select ? b : a;
Example of an implicit continuous assignment:
wire temp_hold = a | b;
Note Continuous assignments are only allowed on wire and tri data types. Procedural Assignments
Procedural assignments are used to assign values to variables declared as regs and are introduced by always blocks, tasks, and functions. Procedural assignments are usually used to model registers and FSMs.
XST includes support for combinatorial functions, combinatorial and sequential tasks, and combinatorial and sequential always blocks.
Combinatorial always blocks
Combinatorial logic can be modeled efficiently using two forms of time control, namely the # and @ Verilog time control statements. The # time control is ignored for synthesis and hence this section describes modeling combinatorial logic with the @ statement.
A combinatorial always block has a sensitivity list appearing within parenthesis after the word "always @". An always block is activated if an event (value change or edge) appears on one of the sensitivity list signals. This sensitivity list contains all signals that appear in conditions (If, Case, for example), and any signal appearing on the right hand side of an assignment.
Note In combinatorial processes, if a signal is not explicitly assigned in all branches of "If" or "Case"
statements, XST will generate a latch to hold the last value. To avoid latch creation, assure that all assigned signals in a combinatorial process are always explicitly assigned in all paths of the process statements. Different statements can be used in a process:
Variable and signal assignment
If... else statement
Case statement
For loop statement
Function and task call
The following sections provide examples of each of these statements.
if...else statement
If... else statements use true/false conditions to execute statements. If the expression evaluates to true, the first statement is executed. If the expression evaluates to false (or x or z), the else statement is executed. A block of multiple statements may be executed using begin and end keywords. If...else statements may be nested. The following example shows how a MUX can be described using an If...else statement.
Example 7-2 MUX Description Using If... Else Statement
module mux4 (sel, a, b, c, d, outmux);
input [1:0] sel;
input [1:0] a, b, c, d;
output [1:0] outmux;
reg [1:0] outmux;
always @(sel or a or b or c or d)
begin
if (sel[1])
if (sel[0])
outmux = d;
else
outmux = c;
else
if (sel[0])
outmux = b;
else
outmux = a;
end
endmodule
Case statement
Case statements perform a comparison to an expression to evaluate one of a number of parallel branches. The Case statement evaluates the branches in the order they are written. The first branch that evaluates to true is executed. If none of the branches match, the default branch is executed.
Note Do no use unbounded integers in case statements. Always bound integers to a specific number of bits, or results will be unpredictable.
Casez treats all z values in any bit position of the branch alternative as a don't care.
Casex treats all x and z values in any bit position of the branch alternative as a don't care.
The question mark (?) can be used as a "don't care" in any of the preceding case statements. The following example shows how a MUX can be described using a Case statement.
Example 7-3 MUX Description Using Case Statement
module mux4 (sel, a, b, c, d, outmux);
input [1:0] sel;
input [1:0] a, b, c, d;
output [1:0] outmux;
reg [1:0] outmux;
always @(sel or a or b or c or d)
begin
case (sel)
2'b00: outmux = a;
2'b01: outmux = b;
2'b10: outmux = c;
default: outmux = d;
endcase
end
endmodule
The preceding Case statement will evaluate the values of the input sel in priority order. To avoid priority processing, it is recommended that you use a parallel-case Verilog meta comment which will ensure parallel evaluation of the sel inputs as in the following.
Example:
always @(sel or a or b or c or d) //synthesis parallel_case
For and Repeat loops
When using always blocks, repetitive or bit slice structures can also be described using the "for" statement or the "repeat" statement.
input CLK, RST;
output [7:0] DO;
reg [7:0] DO;
always @( posedge CLK or posedge RST )
if (RST == 1'b1)
DO = 8'b00000000;
else
DO = DO + 8'b00000001;
endmodule
Assign and Deassign Statements
Assign and deassign statements are supported within simple templates.
The following is an example of the general template for assign / deassign statements:
module assig (RST, SELECT, STATE, CLOCK, DATA_IN);
input RST;
input SELECT;
input CLOCK;
input [0:3] DATA_IN;
output [0:3] STATE;
reg [0:3] STATE;
always @ ( RST )
if( RST )
begin
assign STATE = 4'b 0;
end else
begin
deassign STATE;
end
always @ ( posedge CLOCK )
begin
STATE = DATA_IN;
end
endmodule
Main limitations on support of the assign / deassign statement in XST are as follows:
For a given signal, there must be only one assign /deassign statement. For example, the following design will be rejected:
module dflop (RST, SET, STATE, CLOCK, DATA_IN);
input RST;
input SET;
input CLOCK;
input DATA_IN;
output STATE;
reg STATE;
always @ ( RST ) // block b1
if( RST )
assign STATE = 1'b 0;
else
deassign STATE;
always @ ( SET ) // block b1
if( SET )
assign STATE = 1'b 1;
else
deassign STATE;
always @ ( posedge CLOCK ) // block b2
begin
STATE = DATA_IN;
end
endmodule
The assign / deassign statement must be performed in the same always block through an if /else
statement. For example, the following design will be rejected:
module dflop (RST, SET, STATE, CLOCK, DATA_IN);
input RST;
input SET;
input CLOCK;
input DATA_IN;
output STATE;
reg STATE;
always @ ( RST or SET ) // block b1
case ({RST,SET})
2'b00: assign STATE = 1'b 0;
2'b01: assign STATE = 1'b 0;
2'b10: assign STATE = 1'b 1;
2'b11: deassign STATE;
endcase
always @ ( posedge CLOCK ) // block b2
begin
STATE = DATA_IN;
end
endmodule
You cannot assign a bit/part select of a signal through an assign / deassign statement. For example, the following design will be rejected:
module assig (RST, SELECT, STATE, CLOCK,DATA_IN);
input RST;
input SELECT;
input CLOCK;
input [0:7] DATA_IN;
output [0:7] STATE;
reg [0:7] STATE;
always @ ( RST ) // block b1
if( RST )
begin
assign STATE[0:7] = 8'b 0;
end else
begin
deassign STATE[0:7];
end
always @ ( posedge CLOCK ) // block b2
begin
if (SELECT)
STATE [0:3]= DATA_IN[0:3];
else
STATE [4:7]= DATA_IN[4:7];
end
Tasks and Functions
The declaration of a function or task is intended for handling blocks used multiple times in a design. They must be declared and used in a module. The heading part contains the parameters: input parameters (only) for functions and input/output/inout parameters for tasks. The content is similar to the combinatorial always block content. Recursive function and task calls are not supported.
Example 7-8 shows a function declared within a module. The ADD function declared is a single-bit adder. This function is called 4 times with the proper parameters in the architecture to create a 4-bit adder. The same example, described with a task, is shown in Example 7-9.
Example 7-8 Function Declaration and Function Call
module comb15 ( A, B, CIN, S, COUT);
input [3:0] A, B;
input CIN;
output [3:0] S;
output COUT;
wire [1:0] S0, S1, S2, S3;
function [1:0] ADD;
input A, B, CIN;
reg S, COUT;
begin
S = A ^ B ^ CIN;
COUT = (A&B) | (A&CIN) | (B&CIN);
ADD = {COUT, S};
end
endfunction
assign S0 = ADD ( A[0], B[0], CIN),
S1 = ADD ( A[1], B[1], S0[1]),
S2 = ADD ( A[2], B[2], S1[1]),
S3 = ADD ( A[3], B[3], S2[1]),
S = {S3[0], S2[0], S1[0], S0[0]},
COUT = S3[1];
endmodule
Example 7-9 Task Declaration and Task Enable
module EXAMPLE ( A, B, CIN, S, COUT);
input [3:0] A, B;
input CIN;
output [3:0] S;
output COUT;
reg [3:0] S;
reg COUT;
reg [1:0] S0, S1, S2, S3;
task ADD;
input A, B, CIN;
output [1:0] C;
reg [1:0] C;
reg S, COUT;
begin
S = A ^ B ^ CIN;
COUT = (A&B) | (A&CIN) | (B&CIN);
C = {COUT, S};
end
endtask
always @( A or B or CIN)
begin
ADD ( A[0], B[0], CIN, S0);
ADD ( A[1], B[1], S0[1], S1);
ADD ( A[2], B[2], S1[1], S2);
ADD ( A[3], B[3], S2[1], S3);
S = {S3[0], S2[0], S1[0], S0[0]};
COUT = S3[1];
end
endmodule
Blocking Versus Non-Blocking Procedural Assignments
The # and @ time control statements delay execution of the statement following them until the specified event is evaluated as true. Use of blocking and non-blocking procedural assignments have time control built into their respective assignment statement.
The # delay is ignored for synthesis.
The syntax for a blocking procedural assignment is shown in the following example:
reg a;
a = #10 (
b | c);
or
if (in1) out = 1'b0;
else out = in2;
As the name implies, these types of assignments block the current process from continuing to execute additional statements at the same time. These should mainly be used in simulation.
Non-blocking assignments, on the other hand, evaluate the expression when the statement executes, but allow other statements in the same process to execute as well at the same time. The variable change only occurs after the specified delay.
The syntax for a non-blocking procedural assignment is as follows:
variable <= @(posedge or negedge bit) expression;
The following shows an example of how to use a non-blocking procedural assignment.
if (in1) out <= 1'b1;
else out <= in2;
Constants, Macros, Include Files and Comments
This section discusses constants, macros, include files, and comments.
Constants
By default, constants in Verilog are assumed to be decimal integers. They can be specified explicitly in binary, octal, decimal, or hexadecimal by prefacing them with the appropriate syntax. For example, 4'b1010, 4'o12,
4'd10 and 4'ha all represent the same value.
Macros
Verilog provides a way to define macros as shown in the following example.
`define TESTEQ1 4'b1101
Later in the design code a reference to the defined macro is made as follows.
if (request == `TESTEQ1)
This is shown in the following example.
`define myzero 0
assign mysig = `myzero;
Verilog provides the `ifdef and `endif constructs to determine whether a macro is defined or not. These constructs are used to define conditional compilation. If the macro called out by the `ifdef command has been
defined, that code will be compiled. If not, the code following the `else command is compiled. The `else is not required, but the `endif must complete the conditional statement. The `ifdef and `endif constructs are shown in the following example.
`ifdef MYVAR
module if_MYVAR_is_declared;
...
endmodule
`else
module if_MYVAR_is_not_declared;
...
endmodule
`endif
Include Files
Verilog allows separating source code into more than one file. To use the code contained in another file, the current file has the following syntax:
`include "path/file-name-to-be-included"
Note The path can be relative or absolute.
Multiple `include statements are allowed in a single Verilog file. This is a great feature to make code modular and manageable in a team design environment where different files describe different modules of the design.
If files are referenced by an `include statement, they must not be manually added to the project. For example, at the top of a Verilog file you might see this:
`timescale 1ns/1ps
`include "modules.v"
...
If the specified file (in this case, modules.v) has been added to an ISE project and is specified with an `include, conflicts will occur and an error message displays:
ERROR:Xst:1068 - fifo.v, line 2. Duplicate declarations of module'RAMB4_S8_S8' Comments
There are two forms of comments in Verilog similar to the two forms found in a language like C++.
// Allows definition of a one-line comment.
/* You can define a multi-line comment by enclosing it as illustrated by this sentence*/
Structural Verilog Features
Structural Verilog descriptions assemble several blocks of code and allow the introduction of hierarchy in a design. The basic concepts of hardware structure are the module, the port and the signal. The component is the building or basic block. A port is a component I/O connector. A signal corresponds to a wire between components.
In Verilog, a component is represented by a design module. The module declaration provides the "external" view of the component; it describes what can be seen from the outside, including the component ports. The module body provides an "internal" view; it describes the behavior or the structure of the component.
The connections between components are specified within component instantiation statements. These statements specify an instance of a component occurring within another component or the circuit. Each component instantiation statement is labeled with an identifier. Besides naming a component declared in a local component declaration, a component instantiation statement contains an association list (the parenthesized list) that specifies which actual signals or ports are associated with which local ports of the component declaration. The Verilog language provides a large set of built-in logic gates which can be instantiated to build larger logic circuits. The set of logical functions described by the built-in gates include AND, OR, XOR, NAND, NOR and NOT. Here is an example of building a basic XOR function of two single bit inputs a and b.
module build_xor (a, b, c);
input a, b;
output c;
wire c, a_not, b_not;
not a_inv (a_not, a);
not b_inv (b_not, b);
and a1 (x, a_not, b);
and a2 (y, b_not, a);
or out (c, x, y);
endmodule
Each instance of the built-in modules has a unique instantiation name such as a_inv, b_inv, out. The wiring up of the gates describes an XOR gate in structural Verilog.
Example 7-10 gives the structural description of a half adder composed of four, 2 input nand modules. Example 7-10 Structural Description of a Half Adder
module halfadd (X, Y, C, S);
input X, Y;
output C, S;
wire S1, S2, S3;
nand NANDA (S3, X, Y);
nand NANDB (S1, X, S3);
nand NANDC (S2, S3, Y);
nand NANDD (S, S1, S2);
assign C = S3;
endmodule
Figure 7-1 Synthesized Top Level Netlist
The structural features of Verilog HDL also allow you to design circuits by instantiating pre-defined primitives such as gates, registers and Xilinx specific primitives like CLKDLL and BUFGs. These primitives are other than those included in the Verilog language. These pre-defined primitives are supplied with the XST Verilog libraries (unisim_comp.v).
Example 7-11 Structural Instantiation of Register and BUFG
module foo (sysclk, in, reset,out);
input sysclk, in, reset;
output out;
reg out;
wire sysclk_out;
FDC register (sysclk, reset, in, out); //position based
//referencing
BUFG clk (.O(sysclk_out), .I(sysclk)); //name based referencing
....
endmodule
The unisim_comp.v library file supplied with XST, includes the definitions for FDC and BUFG.
module FDC ( C, CLR, D, Q);
input C;
input CLR;
input D;
output Q;
endmodule
// synthesis attribute BOX_TYPE of FDC is "BLACK_BOX"
module BUFG ( O, I);
output O;
input I;
endmodule
// synthesis attribute BOX_TYPE of BUFG is "BLACK_BOX"
Parameters
Verilog modules support defining constants known as parameters which can be passed to module instances to define circuits of arbitrary widths. Parameters form the basis of creating and using parameterized blocks in a design to achieve hierarchy and stimulate modular design techniques. The following is an example of the use of parameters.
Example 7-12 Using Parameters
module lpm_reg (out, in, en, reset, clk);
parameter SIZE = 1;
input in, en, reset, clk;
output out;
wire [SIZE-1 : 0] in;
reg [SIZE-1 : 0] out;
always @(posedge clk or negedge reset)
begin
if (!reset) out <= SIZE'b0;
else if (en) out <= in;
else out <= out; //redundant assignment
end
endmodule
module top (); //portlist left blank intentionally
...
wire [7:0] sys_in, sys_out;
wire sys_en, sys_reset, sysclk;
lpm_reg #8 buf_373 (sys_out, sys_in, sys_en, sys_reset,sysclk);
...
endmodule
Instantiation of the module lpm_reg with a instantiation width of 8 will cause the instance buf_373 to be 8 bits wide.
assign lpm_reg.out = 8'hFF;
Verilog Limitations in XST
This section describes Verilog limitations in XST support for case sensitivity, and blocking and nonblocking assignments.
Case Sensitivity
XST supports case sensitivity as follows:
Designs can use case equivalent names for I/O ports, nets, regs and memories
Equivalent names are renamed using a postfix ("rnm
A rename construct is generated in the NGC file
Designs can use Verilog identifiers that differ only in case. XST will rename them using a postfix as with equivalent names.
Following is an example.
module upperlower4 (input1, INPUT1, output1, output2);
input input1;
input INPUT1;
For the above example, INPUT1 will be renamed to INPUT1_rnm0
The following restrictions apply for Verilog within XST:
Designs using equivalent names (named blocks, tasks, and functions) are rejected.
Example:
...
always @(clk)
begin: fir_main5
reg [4:0] fir_main5_w1;
reg [4:0] fir_main5_W1;
This code generates the following error message:
ERROR:Xst:863 - "design.v", line 6: Name conflict (
Designs using case equivalent module names are also rejected.
Example:
module UPPERLOWER10 (...);
...
module upperlower10 (...);
...
This example generates the following error message:
ERROR:Xst:909 - Module name conflict (UPPERLOWER10 and upperlower10).
Blocking and Nonblocking Assignments
XST rejects Verilog designs if a given signal is assigned through both blocking and nonblocking assignments as in the following example.
always @(in1) begin
if (in2) out1 = in1;
else out1 <= in2;
end
If a variable is assigned in both a blocking and nonblocking assignment, the following error message is generated:
ERROR:Xst:880 - "design.v", line n:
Cannot mix blocking and non blocking assignments
on signal
There are also restrictions when mixing blocking and nonblocking assignments on bits and slices.
The following example is rejected even if there is no real mixing of blocking and non blocking assignments:
if (in2) begin
out1[0] = 1'b0;
out1[1] <= in1;
end
else begin
out1[0] = in2;
out1[1] <= 1'b1;
end
Errors are checked at the signal level, not at the bit level.
If there is more than a single blocking/non blocking error, only the first one will be reported.
In some cases, the line number for the error might be incorrect (as there might be multiple lines where the signal has been assigned).
Integer Handling
There are several cases where XST handles integers differently from other synthesis tools, and so they must be coded in a particular way.
In case statements, do not use unbounded integers in case item expressions, as this will cause unpredictable results. In the following example, the case item expression "4" is an unbounded integer that will cause unpredictable results. To avoid problems, bound the "4" to 3 bits as shown below.
reg [2:0] condition1;
always @(condition1)
begin
case(condition1)
4 : data_out = 2; // < will generate bad logic
3'd4 : data_out = 2; // < will work
endcase
end
In concatenations, do not use unbounded integers, as this will cause unpredictable results. If you must use an expression that results in an unbounded integer, assign the expression to a temporary signal, and use the temporary signal in the concatenation as shown below.
reg [31:0] temp;
assign temp = 4'b1111 % 2;
assign dout = { 12/3,temp,din};
VerilogHDL的入门学习(可编辑修改word版)
先记下来： 1、不使用初始化语句； 2、不使用延时语句； 3、不使用循环次数不确定的语句，如：forever，while 等； 4、尽量采用同步方式设计电路； 5、尽量采用行为语句完成设计； 6、always 过程块描述组合逻辑，应在敏感信号表中列出所有的输入信号； 7、所有的内部寄存器都应该可以被复位； 8、用户自定义原件（UDP 元件）是不能被综合的。 一：基本 Verilog 中的变量有线网类型和寄存器类型。线网型变量综合成wire，而寄存器可能综合成WIRE，锁存器和触发器，还有可能被优化掉。 二：verilog 语句结构到门级的映射 1、连续性赋值：assign 连续性赋值语句逻辑结构上就是将等式右边的驱动左边的结点。因此连续性赋值的目标结点总是综合成由组合逻辑驱动的结点。Assign 语句中的延时综合时都将忽视。 2、过程性赋值： 过程性赋值只出现在always 语句中。 阻塞赋值和非阻塞赋值就该赋值本身是没有区别的，只是对后面的语句有不同的影响。 建议设计组合逻辑电路时用阻塞赋值，设计时序电路时用非阻塞赋值。 过程性赋值的赋值对象有可能综合成wire, latch,和flip-flop，取决于具体状况。如，时钟控制下的非阻塞赋值综合成flip-flop。 过程性赋值语句中的任何延时在综合时都将忽略。 建议同一个变量单一地使用阻塞或者非阻塞赋值。 3、逻辑操作符： 逻辑操作符对应于硬件中已有的逻辑门，一些操作符不能被综合：===、!==。 4、算术操作符： Verilog 中将reg 视为无符号数，而integer 视为有符号数。因此，进行有符号操
作时使用integer,使用无符号操作时使用reg。 5、进位： 通常会将进行运算操作的结果比原操作数扩展一位，用来存放进位或者借位。如：Wire [3:0] A,B; Wire [4:0] C; Assign C=A+B; C 的最高位用来存放进位。 6、关系运算符： 关系运算符：<,>,<=,>= 和算术操作符一样，可以进行有符号和无符号运算，取决于数据类型是reg，net 还是integer。 7、相等运算符：==，！= 注意：===和！==是不可综合的。 可以进行有符号或无符号操作，取决于数据类型 8、移位运算符： 左移，右移，右边操作数可以是常数或者是变量，二者综合出来的结果不同。 9、部分选择： 部分选择索引必须是常量。 10、BIT 选择： BIT 选择中的索引可以用变量，这样将综合成多路（复用）器。 11、敏感表：Always 过程中，所有被读取的数据，即等号右边的变量都要应放在敏感表中，不然，综合时不能正确地映射到所用的门。 12、IF： 如果变量没有在IF 语句的每个分支中进行赋值，将会产生latch。如果IF 语句中产生了latch，则IF 的条件中最好不要用到算术操作。Case 语句类似。Case 的条款可以是变量。 如果一个变量在同一个IF 条件分支中先赎值然后读取，则不会产生latch。如果先读取，后赎值，则会产生latch。 13、循环： 只有for-loop 语句是可以综合的。
(完整word版)Verilog-A30分钟快速入门教程
?Verilog-A 30分钟快速入门教程 进入正题，学了几天的Verilog-A，平台是Agilent ADS，主要参考“Verilog-AMS Language Reference Manual”和ADS的帮助文档。 现在的状态算是入门了，写了个简单的PLL。总结这几天的学习，觉得效率太低，我以前有一定Verilog基础，研一时学过一点VHDL-AMS，学到现在这个状态应该半天就够了；入门的话，30分钟足矣；跟着这个教程走，你会很快了解和熟悉Verilog-A。（前提是有一定的Verilog基础和电路基础） 1、基尔霍夫定律撑起了整个电路学的大厦（当然也可以认为基尔霍夫定律只是麦克斯韦方程的简化版），作为模拟电路描述语言Verilog-A，同样将基尔霍夫定律作为其基本，最重要的两个概念便是流量(Flow)和位(Potential)，在电学里是电流和电压，在力学里可以是力和距离，在热学里可以是功率和温差，等等。 在Verilog-A中，你可以将电阻电容电感等器件用一个方程式来表述，比如I(out) <+ V(out)/R，这样就产生了一个电阻，最后Verilog-A仿真器会用某种算法(迭代是最常见的)将I(out)和V(out)求解出来，然后根据这个解去算下一个时刻的I、V等，当然这仅仅是指时域仿真。 2、下面讲Verilog-A的语法： begin end //相当于C语言的一对大括号，与Verilog同 if ( expression ) true_statement ; [ else false_statement ; ] //与Verilog同 case ( expression ) case_item { case_item } endcase for ( procedural_assignment ; expression; procedural_assignment ) statement //case与for语句都跟Verilog、C语言类似 cross( expr [, dir [, time_tol [, expr_tol ]]] ); //cross用来产生一个event，如： @(cross(V(sample) -2.0, +1.0)) //指sample的电压超过2.0时触发该事件，将会执行后面的语句，+1.0表示正向越过，-1.0则相反 ddt( expr ) //求导，如： I(n1,n2) <+ C * ddt(V(n1, n2)); //表示了一个电容 idt( expr ,[ ic [, assert [, abstol ]]] ) //积分，如： V(out) <+ gain * idt(V(in) ,0) + gain * V(in); //比例积分，式中的0表示积分的初值 transition( expr [, time_delay [, rise_time [, fall_time [, time_tol ]]]] ) //将expr的值delay一下并指定上升下降沿时间，相当于一个传输门
Verilog-A 30分钟快速入门教程
?进入正题，学了几天的Verilog-A，平台是Agilent ADS，主要参考“Verilog-AMS L anguage Reference Manual”和ADS的帮助文档。 现在的状态算是入门了，写了个简单的PLL。总结这几天的学习，觉得效率太低，我以前有一定Verilog基础，研一时学过一点VHDL-AMS，学到现在这个状态应该半天就够了；入门的话，30分钟足矣；跟着这个教程走，你会很快了解和熟悉Verilog-A。（前提是有一定的Verilog 基础和电路基础） 1、基尔霍夫定律撑起了整个电路学的大厦（当然也可以认为基尔霍夫定律只是麦克斯韦方程的 简化版），作为模拟电路描述语言Verilog-A，同样将基尔霍夫定律作为其基本，最重要的两个概念便是流量(Flow)和位(Potential)，在电学里是电流和电压，在力学里可以是力和距离，在热学里可以是功率和温差，等等。 在Verilog-A中，你可以将电阻电容电感等器件用一个方程式来表述，比如I(out) <+ V(o ut)/R，这样就产生了一个电阻，最后Verilog-A仿真器会用某种算法(迭代是最常见的)将I(o ut)和V(out)求解出来，然后根据这个解去算下一个时刻的I、V等，当然这仅仅是指时域仿真。 2、下面讲Verilog-A的语法： begin end //相当于C语言的一对大括号，与Verilog同 if ( expression ) true_statement ; [ else false_statement ; ] //与Verilog同 case ( expression ) case_item { case_item } endcase for ( procedural_assignment ; expression; procedural_assignment ) statement //case与for语句都跟Verilog、C语言类似 cross( expr [, dir [, time_tol [, expr_tol ]]] ); //cross用来产生一个event，如：
3.2.1 Verilog HDL程序入门[共2页]
║68 第3章 硬件描述语言Verilog HDL基础 3.2 Verilog HDL程序基本结构 Verilog HDL是一种用于数字逻辑电路设计的语言。用Verilog HDL描述的电路设计就是该电路的Verilog HDL模型。Verilog HDL既是一种行为描述的语言，也是一种结构描述的语言。也就是说，既可以用电路的功能描述，也可以用元器件和它们之间的连接来建立所设计电路的Verilog HDL模型。Verilog模型可以是实际电路的不同级别的抽象。这些抽象的级别和它们对应的模型类型共有以下5种。 ?系统级（system）：用高级语言结构实现设计模块的外部性能的模型。 ?算法级（algorithm）：用高级语言结构实现设计算法的模型。 ?RTL级（Register Transfer Level）：描述数据在寄存器之间流动和如何处理这些数据的模型。 ?门级（gate-level）：描述逻辑门以及逻辑门之间的连接的模型。 ?开关级（switch-level）：描述器件中三极管和储存节点以及它们之间连接的模型。 一个复杂电路系统的完整Verilog HDL模型是由若干个Verilog HDL模块构成的，每一个模块又可以由若干个子模块构成。其中有些模块需要综合成具体电路，而有些模块只是与用户所设计的模块交互的现存电路或激励信号源。利用Verilog HDL语言结构所提供的这种功能就可以构造一个模块间的清晰层次结构来描述极其复杂的大型设计，并对所作设计的逻辑电路进行严格的验证。 Verilog HDL行为描述语言作为一种结构化和过程性的语言，其语法结构非常适合于算法级和RTL级的模型设计。这种行为描述语言具有以下功能。 ?可描述顺序执行或并行执行的程序结构。 ?用延迟表达式或事件表达式来明确地控制过程的启动时间。 ?通过命名的事件来触发其他过程里的激活行为或停止行为。 ?提供了条件、if-else、case、循环程序结构。 ?提供了可带参数且非零延续时间的任务（task）程序结构。 ?提供了可定义新的操作符的函数结构（function）。 ?提供了用于建立表达式的算术运算符、逻辑运算符、位运算符。 ? Verilog HDL语言作为一种结构化的语言也非常适合于门级和开关级的模型设计。因其结构化的特点又使它具有以下功能。 —提供了完整的一套组合型原语（primitive）； —提供了双向通路和电阻器件的原语； —可建立MOS器件的电荷分享和电荷衰减动态模型。 Verilog HDL的构造性语句可以精确地建立信号的模型。这是因为在Verilog HDL中，提供了延迟和输出强度的原语来建立精确程度很高的信号模型。信号值可以有不同的强度，可以通过设定宽范围的模糊值来降低不确定条件的影响。 Verilog HDL作为一种高级的硬件描述编程语言，有着类似C语言的风格。其中if语句、case语句等和C语言中的对应语句十分相似。如果读者已经掌握C语言编程的基础，那么学习Verilog HDL并不困难，只要对Verilog HDL某些语句的特殊方面着重理解，并加强上机练习就能很好地掌握它，利用它的强大功能来设计复杂的数字逻辑电路。下面将介绍Verilog
Verilog语法入门,初学者必看
Verilog的词法约定 1Verilog是大小写相关的，其中的关键字全部为小写。 2空白符由空格、制表符、和换行符组成。 3单行注释以“//”开始，verilog将忽略此处到行尾的内容。多行注释以“/*” 开始，以“*/”结束。多行注释不允许嵌套 4操作符有三种：单目操作符、双目操作符和三目操作符。 5数字声明 Verilog中有两种数字生命：指明位数的数字和不指明位数的数字 指明位数的数字表示形式：
VerilogHDL语法基础
Verilog HDL语法基础(1) Verilog的词法约定 1Verilog是大小写相关的，其中的关键字全部为小写。 2空白符由空格、制表符、和换行符组成。 3单行注释以“//”开始，verilog将忽略此处到行尾的内容。多行注释以“/ *”开始，以“*/”结束。多行注释不允许嵌套 4操作符有三种：单目操作符、双目操作符和三目操作符。 5数字声明 Verilog中有两种数字生命：指明位数的数字和不指明位数的数字 指明位数的数字表示形式：
verilog入门经验(一) always块使用
1. 信号的产生及always块使用注意事项 1.1 不要在不同的always块内为同一个变量赋值。即某个信号出现在<=或=左边时，只能在一个always块内。（详细解释见 Verilog HDL与数字电路设计 P38） 所以注意，在产生一个信号时，所有产生该信号的条件都应放在一个always块内考虑。 1.2 不要在同一个always块内同时使用阻塞赋值（=）和非阻塞赋值（<=）。 1.3 使用always块描述组合逻辑时使用阻塞赋值（=），在使用always块描述时序逻辑时使用非阻塞赋值（<=）。简单理解可以是，在电平敏感的always块内使用阻塞赋值，在边沿敏感的always块内使用非阻塞赋值。 1.4 任何在always块内被赋值的变量都必须是寄存器型（reg）。即<=或=左边的信号，必须是reg型，<=或=右边的信号可以是reg型也可以是wire型。 另，端口声明中被声明为input或inout型的端口，只能被定义为线网型（wire）；被声明为output型的端口，则可以被定义为线网型（wire）或者寄存器型（reg）。如果不定义，则默认为线网型（wire）。 1.5 always的敏感列表中可以同时包括多个电平敏感事件，也可以同时包括多个边沿敏感事件，但不能同时有电平和边沿敏感事件。另外，敏感列表中，同时包括一
个信号的上升沿敏感事件和下降沿敏感事件也是不允许的，因为这两个事件可以合并为一个电平事件。 2. 总clk的使用 always敏感列表里的边沿触发事件，就是一个clk信号，所以在制定ucf时，边沿触发事件信号都要被定义在clk IO端口上，有时随意分配的clk IO端口在Implement 时也会出错。需要到ucf中用 NET "polin" CLOCK_DEDICATED_ROUTE = FALSE; //polin为边沿触发事件信号 语句来规避错误。 所以在一个程序中，要尽量使用主clk作为always块的边沿触发信号。如果有些变量要通过某个信号的边沿触发来产生，那尽量将这个边沿触发信号做成一个判断条件，然后在产生变量时仍用主clk触发。 例程：要得到LCD大尺寸屏POL信号的2分频、8分频、16分频...，在控制板上拨动开关设置不同的状态，输出polout切换到不同的pol输入的分频信号。 思路，定义一个counter（cnt_pol）对输入pol信号进行计数，则cnt_pol的bit0位与pol输入信号一致， cnt_pol的bit1位为pol信号的2分频，bit2位为pol的4分频，bit3位为pol的8分频，bit4位为pol的16分频...
QuartusⅡ8.1入门教程(一个Verilog程序的编译和功能仿真)
Quartus Ⅱ8.1入门教程 （一个Verilog 程序的编译和功能仿真） Quartus Ⅱ 是Altera 公司推出的专业EDA 工具，支持原理图输入、硬件描述语言的输入等多种输入方式。硬件描述语言的输入方式是利用类似高级程序的设计方法来设计出数字系统。接下来我们对这种智能的EDA 工具进行初步的学习。使大家以后的数字系统设计更加容易上手。 第一步：打开软件 ● 快捷工具栏：提供设置（setting ），编译（compile ）等快捷方式，方便用户使用，用户也可以在菜单栏的下拉菜单找到相应的选项。 ● 菜单栏：软件所有功能的控制选项都可以在其下拉菜单中找到。 ● 信息栏：编译或者综合整个过程的详细信息显示窗口，包括编译通过信息和报错信息。 快捷工具栏 菜单栏 工作区 资源管理窗口 任务管理窗口
注意以下命名要一致。 第二步：新建工程（file>new Project Wizard）1 工程名称： 2添加已有文件（没有已有文件的直接跳过next）所建工程的保存路径 工程名称顶层模块名（芯片级设计为实体名），要求与工程名称相同 如果有已经存在的文 件就在该过程中添加， 软件将直接将用户所 添加的文件添加到工 程中。
3 选择芯片型号（我们选择MAX3000A 系列下的EPM3256AQC208-10芯片） (注：如果不下载到开发板上进行测试，这一步可以不用设置) 4 选择仿真，综合工具（第一次实验全部利用quartus 做，三项都选None ，然后next ） 所选的芯片的系列型号 快速搜索所需的芯片 选择芯片
5 工程建立完成（点finish） 选择第三方综合工具，如果 使用Quartus内部综合工具 则选择none 选择第三方仿真工具，如果 使用Quartus内部仿真工具 则选择none 选择时序分析仪 工程建立完成，该窗口显示所建立工程所有的芯片，其他第三方EDA工具选择情况，以及模块名等等信息。
Verilog-A 30分钟快速入门教程
Verilog-A 30分钟快速入门教程 进入正题，学了几天的Verilog-A，平台是Agilent ADS，主要参考“Verilog-AMS Language Reference Manual”和ADS的帮助文档。 现在的状态算是入门了，写了个简单的PLL。总结这几天的学习，觉得效率太低，我以前有一定Verilog基础，研一时学过一点VHDL-AMS，学到现在这个状态应该半天就够了；入门的话，30分钟足矣；跟着这个教程走，你会很快了解和熟悉Verilog-A。（前提是有一定的Verilog基础和电路基础） 1、基尔霍夫定律撑起了整个电路学的大厦（当然也可以认为基尔霍夫定律只是麦克斯韦方程的简化版），作为模拟电路描述语言Verilog-A，同样将基尔霍夫定律作为其基本，最重要的两个概念便是流量(Flow)和位(Potential)，在电学里是电流和电压，在力学里可以是力和距离，在热学里可以是功率和温差，等等。 在Verilog-A中，你可以将电阻电容电感等器件用一个方程式来表述，比如I(out) <+ V(out)/R，这样就产生了一个电阻，最后Verilog-A仿真器会用某种算法(迭代是最常见的)将I(out)和V(out)求解出来，然后根据这个解去算下一个时刻的I、V等，当然这仅仅是指时域仿真。 2、下面讲Verilog-A的语法： begin end //相当于C语言的一对大括号，与Verilog同 if ( expression ) true_statement ; [ else false_statement ; ] //与Verilog同 case ( expression ) case_item { case_item } endcase for ( procedural_assignment ; expression; procedural_assignment ) statement //case与for语句都跟Verilog、C语言类似 cross( expr [, dir [, time_tol [, expr_tol ]]] ); //cross用来产生一个event，如： @(cross(V(sample) -2.0, +1.0)) //指sample的电压超过2.0时触发该事件，将会执行后面的语句，+1.0表示正向越过，-1.0则相反 ddt( expr ) //求导，如： I(n1,n2) <+ C * ddt(V(n1, n2)); //表示了一个电容 idt( expr ,[ ic [, assert [, abstol ]]] ) //积分，如： V(out) <+ gain * idt(V(in) ,0) + gain * V(in); //比例积分，式中的0表示积分的初值 transition( expr [, time_delay [, rise_time [, fall_time [, time_tol ]]]] ) //将expr的值delay一下并指定上升下降沿时间，相当于一个传输门
Verilog入门训练4—三人表决器
实训3：三人表决器的设计与实现 问题提出：表决器既是多数通过事件，三个人参与表决，大于或等于二人即为通过。请设计一个数字组合逻辑电路，实现上述三人表决功能。 1.逻辑抽象 假设参与表决的三人分别为A、B、C，表决结果为F。当三人中有两人或以上同意，即 A、B、C三个输入中有两个或以上为1时，F=1。在FPGA开发板上，同样可以定义三个 拨动开关分别代表A、B和C，一个LED灯代表F，表决通过时，灯亮，否则灯灭。 2.列出真值表 得到：F=AB+BC+ AC 3.使用Quartus 8.0建立项目，建立过程和注意事项见前两周的实验指导，选择器件时随便 指定一个。这里的项目名称为voter3。（切记项目保存路径和实验过程中新建的文件保存路径都不要出现中文） 4.项目建好后，新建Verilog文件并输入代码 选择“File”——“New”——“Verilog HDL file”。第1种方法：直接根据逻辑表达式写出代码，即数据流描述方式。如下所示。保存文件，文件名同为voter3。
5.编译项目。“Processing”——“Start Compilation” 6.功能仿真 编译通过后，新建波形仿真文件：“File”——“New”，选择“Vector Waveform File”，如下图所示： 在出现的编辑界面左侧右键，选择如下： 在“Insert Node or Bus”里选择“Node Finder…”
在弹出来的“Node Finder”中，首先在“Filter”中选择“Pins：Unassigned”，然后点击“list”，在“Nodes Found”中会列出所有的引脚，第三步选择全部引脚（鼠标拉），点击“>>”，最后点击“OK”即可。在回到的“Insert Node or Bus”界面点击“OK”。 这时候会看到所有的引脚会列出来，如下所示，三个输入默认为低电平，输出F状态未知。 由实验原理可知，为了得到A、B、C三个信号不同的组合，设置A为10ns周期信号，B为20ns周期信号，C为40ns周期信号。设置方法如下： 选择输入“A”，点击右键，选择“Value”——“Clock”。 在Clock中设置周期为10ns。如下所示：
verilogzuoye入门程序
1.以结构描述方式实现下列逻辑： F=AB+ACD（CD的非）module f(data,A,B,C,D); input A,B,C,D; output data; and nd1(E,A,B), nd3(G,A,F); nand nd2(F,C,D); or nd4(data,G,E); endmodule 2.以连续赋值语句设计8位总线驱动器。module zongxian(bus,in,en); input[7:0] in; input en; output[7:0] bus; wire[7:0] in,bus; wire en; assign bus=(en==1)?in:8'hzz; endmodule 3.以always语句设计8位总线驱动器module zongxian(bus,in,en); input[7:0] in; input en; output[7:0] bus; reg[7:0] bus; always@(en or in) begin if(en==1)bus<=in; else bus<=8'hzz; end endmodule 4.以always语句设计8位双向总线驱动器。module zongxian(bus,out,in,t,en); input en,t; input[7:0] in; output[7:0] out; inout[7:0] bus; reg[7:0] bus,out; always@(en or in) if(!en)bus<=8'hzz; else bus<=in; always@(t or bus) if(!t)out<=bus; endmodule
Verilog HDL 入门教程(华为)
文档中心 文档编号 资源类别： HDL语言版本 1.0 密级 内部公开 共41页 Verilog HDL入门教程(仅供内部使用) 拟制： 批准： 批准： 中研基础 中研基础 日期：
日期： 日期： 2004.8.3 yyyy/mm/dd 版权所有不得复制 Verilog HDL 入门教程绝密请输入文档编号日期 2004.8.3 修订版本 1.00 描述 初稿完成 修订记录 作者
2004-08-16 第2页，共41页版权所有，侵权必究 Verilog HDL 入门教程 绝密请输入文档编号 目录 1 前 言 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 HDL设计方法学简 介 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 数字电路设计方 法 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 硬件描述语 言 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Verilog HDL入门教程
文档编号版本密级文档中心 1.0 内部公开 资源类别：HDL语言共41页Verilog HDL入门教程 (仅供内部使用) 拟制：中研基础日期：2004.8.3 批准：中研基础日期： 批准：日期：yyyy/mm/dd 版权所有不得复制
修订记录 日期修订版本描述作者2004.8.3 1.00 初稿完成
目录 1 前言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 HDL设计方法学简介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 数字电路设计方法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 硬件描述语言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 设计方法学. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 Verilog HDL简介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4.1 历史. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4.2 能力. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Verilog HDL 建模概述. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 模块. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.1 简单事例. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.2 模块的结构. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.3 模块语法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 时延. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 三种建模方式. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.1 结构化描述方式. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.2 数据流描述方式. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.3 行为描述方式. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.4 混合设计描述. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Verilog HDL 基本语法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 标识符. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 定义. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.2 关键词. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.3 书写规范建议. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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