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DS25BR400中文资料

DS25BR400

Quad Transceiver with Input Equalization and Output De-Emphasis

General Description

The DS25BR400is a quad 250Mbps – 2.5Gbps CML transceiver,or 8-channel buffer,for use in XAUI Fibre Chan-nel backplane and cable applications.With operation down to 250Mbps,the DS25BR400can be used in applications requiring both low and high frequency data rates.Each input stage has a fixed equalizer to reduce ISI distortion from board traces.The equalizers are grouped in fours and are enabled through two control pins.These control pins provide customers flexibility in XAUI applications where ISI distortion may vary from one direction to another.All output drivers have four selectable steps of de-emphasis to compensate against transmission loss across long FR4backplanes.The de-emphasis blocks are also grouped in fours.In addition,the DS25BR400also has loopback control capability on four channels.All CML drivers and receivers are internally termi-nated with 50?pull-up resistors.

Features

n Quad 2.5Gbps Transceiver or 8-Channel CML Serial Buffer

n 250Mbps –2.5Gbps Fully Differential Data Paths n Optional Fixed Input Equalization n Selectable Output De-emphasis n Individual Loopback Controls n On-chip Termination n +3.3V supply

n Low Power,1.3Watts MAX n Lead-less eLLP-60pin package (9mmx9mmx0.8mm,0.4mm pitch)

n ?40?C to +85?C Industrial Temperature Range n 6kV ESD Rating,HBM

Functional Block Diagram

20194201

May 2006

DS25BR400Quad Transceiver with Input Equalization and Output De-Emphasis

?2006National Semiconductor Corporation https://www.wendangku.net/doc/d35598929.html,

Connection Diagram

20194202

Leadless eLLP-60Pin Package (9mmx9mmx0.8mm,0.4mm pitch)Order number DS25BR400TSQ See NS Package Number SQA060

D S 25B R 400

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Pin Descriptions

Pin Name

Number

I/O Description

DIFFERENTIAL I/O

IB_0+ IB_0?51

I Inverting and non-inverting differential inputs of port_0.IB_0+and IB_0?are internally

connected to a reference voltage through a50?resistor.

OA_0+ OA_0?48

O Inverting and non-inverting differential outputs of port_0.OA_0+and OA_0?are connected to V CC through a50?resistor.

IB_1+ IB_1?43

I Inverting and non-inverting differential inputs of port_1.IB_1+and IB_1?are internally

connected to a reference through a50?resistor.

OA_1+ OA_1?40

O Inverting and non-inverting differential outputs of port_1.OA_1+and OA_1?are connected to V CC through a50?resistor.

IB_2+ IB_2?33

I Inverting and non-inverting differential inputs of port_2.IB_2+and IB_2?are internally

connected to a reference voltage through a50?resistor.

OA_2+ OA_2?36

O Inverting and non-inverting differential outputs of port_2.OA_2+and OA_2?are connected to V CC through a50?resistor.

IB_3+ IB_3?25

I Inverting and non-inverting differential inputs of port_3.IB_3+and IB_3?are internally

connected to a reference voltage through a50?resistor.

OA_3+ OA_3?28

O Inverting and non-inverting differential outputs of port_3.OA_3+and OA_3?are connected to V CC through a50?resistor.

IA_0+ IA_0?58

I Inverting and non-inverting differential inputs of port_0.IA_0+and IA_0?are internally

connected to a reference voltage through a50?resistor.

OB_0+ OB_0?55

O Inverting and non-inverting differential outputs of port_0.OB_0+and OB_0?are connected to V CC through a50?resistor.

IA_1+ IA_1?6

I Inverting and non-inverting differential inputs of port_1.IA_1+and IA_1?are internally

connected to a reference through a50?resistor.

OB_1+ OB_1?3

O Inverting and non-inverting differential outputs of port_1.OB_1+and OB_1?are connected to V CC through a50?resistor.

IA_2+ IA_2?10

I Inverting and non-inverting differential inputs of port_2.IA_2+and IA_2?are internally

connected to a reference voltage through a50?resistor.

OB_2+ OB_2?13

O Inverting and non-inverting differential outputs of port_2.OB_2+and OB_2?are connected to V CC through a50?resistor.

IA_3+ IA_3?18

I Inverting and non-inverting differential inputs of port_3.IA_3+and IA_3?are internally

connected to a reference voltage through a50?resistor.

OB_3+ OB_3?21

O Inverting and non-inverting differential outputs of port_3.OB_3+and OB_3?are connected to V CC through a50?resistor.

CONTROL(3.3V LVCMOS)

EQA60I This pin is active LOW.A logic LOW at EQA enables equalization for input channels

IA_0±,IA_1±,IA_2±,and IA_3±.By default,this pin is internally pulled high and

equalization is disabled.

EQB16I This pin is active LOW.A logic LOW at EQB enables equalization for input channels

IB_0±,IB_1±,IB_2±,and IB_3±.By default,this pin is internally pulled high and

equalization is disabled.

PreA_0 PreA_115

I PreA_0and PreA_1select the output de-emphasis levels(OA_0±,OA_1±,OA_2±,and

OA_3±).PreA_0and PreA_1are internally pulled high.Please see Table2for

de-emphasis levels.

PreB_0 PreB_131

I PreB_0and PreB_1select the output de-emphasis levels(OB_0±,OB_1±,OB_2±,and

OB_3±).PreB_0and PreB_1are internally pulled high.Please see Table2for

de-emphasis levels.

LB046I This pin is active LOW.A logic LOW at LB0enables the internal loopback path from IB_0±

to OA_0±.LB0is internally pulled high.Please see Table1for more information.

LB144I This pin is active LOW.A logic LOW at LB1enables the internal loopback path from IB_1±

to OA_1±.LB1is internally pulled high.Please see Table1for more information.

DS25BR400

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Pin Descriptions

(Continued)Pin Name

Pin Number I/O

Description

CONTROL (3.3V LVCMOS)LB232I This pin is active LOW.A logic LOW at LB2enables the internal loopback path from IB_2±to OA_2±.LB2is internally pulled high.Please see Table 1for more information.

LB330I This pin is active LOW.A logic LOW at LB3enables the internal loopback path from IB_3±to OA_3±.LB3is internally pulled high.Please see Table 1for more information.RSV 59

Reserve pin to support factory testing.This pin can be left open,tied to GND,or tied to GND through an external pull-down resistor.

POWER V CC

5,11,20,26,35,41,50,56

V CC =3.3V ±5%.

Each V CC pin should be connected to the V CC plane through a low inductance path,typically with a via located as close as possible to the landing pad of the V CC pin.

It is recommended to have a 0.01μF or 0.1μF,X7R,size-0402bypass capacitor from each V CC pin to ground plane.

GND

8,14,23,29,38,47,

53P

Ground reference.Each ground pin should be connected to the ground plane through a low inductance path,typically with a via located as close as possible to the landing pad of the GND pin.

GND DAP

DAP is the metal contact at the bottom side,located at the center of the eLLP-60pin package.It should be connected to the GND plane with at least 4via to lower the ground impedance and improve the thermal performance of the package.Note:I =Input,O =Output,P =Power

D S 25B R 400

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Functional Description

TABLE1.Logic Table for Loopback Controls

LB0Loopback Function

0Enable loopback from IB_0±to OA_0±.

1(default)Normal mode.Loopback disabled.

LB1Loopback Function

0Enable loopback from IB_1±to OA_1±.

1(default)Normal mode.Loopback disabled.

LB2Loopback Function

0Enable loopback from IB_2±to OA_2±.

1(default)Normal mode.Loopback disabled.

LB3Loopback Function

0Enable loopback from IB_3±to OA_3±.

1(default)Normal mode.Loopback disabled.

TABLE2.De-Emphasis Controls

PreA_[1:0]Default VOD Level in mV PP

(VODB)

De-Emphasis Level in mV PP

(VODPE)

De-Emphasis in dB

(VODPE/VODB)

00120012000 011200850?3 101200600?6 11(Default)1200426?9

PreB_[1:0]Default VOD Level in mV PP

(VODB)

De-Emphasis Level in mV PP

(VODPE)

De-Emphasis in dB

(VODPE/VODB)

00120012000 011200850?3 101200600?6 11(Default)1200426?9

De-emphasis is the primary signal conditioning function for use in compensating against backplane transmission loss. The DS25BR400provides four steps of de-emphasis rang-ing from0,?3,?6and?9dB,user-selectable dependent on the loss profile of the backplane.Figure1shows a driver

de-emphasis waveform.The de-emphasis duration is nomi-

nal188ps,corresponding to0.75bit-width at2.5Gbps.The

de-emphasis levels of switch-side and line-side can be indi-

vidually programmed.

DS25BR400

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Input Equalization

Each differential input of the DS25BR400has a fixed equal-izer front-end stage.It is designed to provide fixed equaliza-tion for short board traces with transmission losses of ap-proximately 5dB between 375MHz to 1.875GHz.Programmable de-emphasis together with input equalization ensures an acceptable eye opening for a 40-inch FR-4back-plane.

The differential input equalizer for inputs on Channel A and inputs on Channel B can be bypassed by using EQA and EQB,respectively.By default,the equalizers are internally pulled high and disabled.Therefore,EQA and EQB must be asserted LOW to enable equalization.

20194237

FIGURE 1.Driver De-Emphasis Differential Waveform (showing all 4de-emphasis steps)

D S 25B R 400

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Absolute Maximum Ratings(Note1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage(V CC)?0.3V to4V CMOS/TTL Input Voltage?0.3V to

(V CC+0.3V) CML Input/Output Voltage?0.3V to

(V CC+0.3V) Junction Temperature+150?C Storage Temperature?65?C to+150?C Lead Temperature

Soldering,4sec+260?C Thermal Resistance,θJA22.3?C/W Thermal Resistance,θJC 3.2?C/W

Thermal Resistance,ΦJB10.3?C/W (Note:assumes26thermal vias)

ESD Ratings((Note9))

HBM6kV

CDM1kV

MM350V

Recommended Operating Ratings

Min Typ Max Units Supply Voltage(V CC-GND) 3.135 3.3 3.465V Supply Noise Amplitude

10Hz to2GHz

100mV PP Ambient Temperature?40+85?C Case Temperature100?C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min

Typ

(Note2)

Max Units

LVCMOS DC SPECIFICATIONS

V IH High Level Input

Voltage 2.0

V CC

+0.3

V IL Low Level Input

Voltage

?0.30.8V

I IH High Level Input

Current V IN=V CC

?1010μA

I IL Low Level Input

Current V IN=GND

7594124μA

R PU Pull-High Resistance35k?RECEIVER SPECIFICATIONS

V ID Differential Input

Voltage Range AC Coupled Differential Signal.

Below1.25Gb/s

At1.25Gbps–3.125Gbps

Above3.125Gbps

This parameter is not production tested.

100

1750

1560

1200

mV P-P

V ICM Common Mode

Voltage at Receiver

Inputs Measured at receiver inputs reference to

ground. 1.3V

R ITD Input Differential

Termination On-chip differential termination between IN+

or IN?.

84100116?

R ITSE Input Termination

(single-end)On-chip termination IN+or IN?to GND for

frequency>100MHz.

50?

DRIVER SPECIFICATIONS

VODB Output Differential

Voltage Swing

without De-Emphasis R L=100?±1%

PreA_1=0;PreA_0=0

PreB_1=0;PreB_0=0

Driver de-emphasis disabled.

Running K28.7pattern at2.5Gbps.

(Figure6)

100012001400mV P-P

DS25BR400

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Electrical Characteristics

(Continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ (Note 2)

Max

Units

DRIVER SPECIFICATIONS V PE

Output De-Emphasis Voltage Ratio 20*log(VODPE/VODB)R L =100?±1%Running K28.7pattern at 2.5Gbps PreX_[1:0]=00

PreX_[1:0]=01PreX_[1:0]=10PreX_[1:0]=11

X =A/B channel de-emphasis drivers (Figure 1/Figure 6)0?3?6?9dB dB dB dB

t PE

De-Emphasis Width

Tested at ?9dB de-emphasis level,PreX[1:0]=11

X =A/B channel de-emphasis drivers See Figure 5on measurement condition.125200250ps

R OTSE Output Termination On-chip termination from OUT+or OUT?to V CC

425058?R OTD Output Differential Termination On-chip differential termination between OUT+and OUT?

100

?R OTSE

Mis-Match in Output Termination Resistors Mis-match in output termination resistors

V OCM

Output Common Mode Voltage 2.7V

POWER DISSIPATION P D

Power Dissipation

V DD =3.465V

All outputs terminated by 100?±1%.PreB_[1:0]=0,PreA_[1:0]=0

Running PRBS 27-1pattern at 2.5Gbps 1.3W

AC CHARACTERISTICS t R

Differential Low to High Transition Time

Measured with a clock-like pattern at 2.5Gbps,between 20%and 80%of the differential output voltage.De-emphasis disabled.

Transition time is measured with the fixture shown in Figure 6adjusted to reflect the transition time at the output pins.

t F

Differential High to Low Transition Time

80ps

t PLH

Differential Low to High Propagation Delay

Measured at 50%differential voltage from input to output.

1ns

t PHL

Differential High to Low Propagation Delay 1

ns t SKP Pulse Skew |t PHL –t PLH |

20ps t SKO

Output Skew (Note 7)

Difference in propagation delay between channels on the same part (Channel-to-Channel Skew)

100

t SKPP

Part-to-Part Skew (Note 7)Difference in propagation delay between devices across all channels operating under identical conditions

165ps

t LB

Loopback Delay Time

Delay from enabling loopback mode to signals appearing at the differential outputs Figure 4

4ns

D S 25B R 400

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Electrical Characteristics(Continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min

Typ

(Note2)

Max Units

AC CHARACTERISTICS

RJ Device Random Jitter

(Note5)At0.25Gbps

At1.5Gbps

At2.5Gbps

Alternating-10pattern.

De-emphasis disabled.

(Figure6)

ps rms

DJ Device Deterministic

Jitter(Note6)At0.25Mbps,PRBS7pattern

At1.5Gbps,K28.5pattern

At2.5Gbps,K28.5pattern

At2.5Gbps,PRBS7pattern

De-emphasis disabled.

(Figure6)

ps pp

DR Data Rate

(Note8)Alternating-10pattern

0.25 2.5Gbps

Note1:“Absolute Maximum Ratings”indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional.For guaranteed specifications and the test conditions,see the Electrical Characteristics Tables.Operation of the device beyond the maximum Operating

Ratings is not recommended.

Note2:Typical specifications are at TA=25C,and represent most likely parametric norms at the time of product characterization.The typical specifications are not guaranteed.

Note3:IN+and IN?are generic names that refer to one of the many pairs of complementary inputs of the DS25BR400.OUT+and OUT?are generic names that

refer to one of the many pairs of the complementary outputs of the DS25BR400.Differential input voltage V ID is defined as|IN+–IN?|.Differential output voltage

V OD is defined as|OUT+–OUT?|.

Note4:K28.7pattern is a10-bit repeating pattern of K28.7code group{0011111000}

K28.5pattern is a20-bit repeating pattern of+K28.5and?K28.5code groups{11000001010011111010}

Note5:Device output random jitter is a measurement of random jitter contributed by the device.It is derived by the equation SQRT[(RJ OUT)2–(RJ IN)2],where

RJ OUT is the total random jitter measured at the output of the device in ps(rms),RJ IN is the random jitter of the pattern generator driving the device.Below400Mbps,

system jitter and device jitter could not be separated.The250Mbps specification includes system random jitter.Please see Figure6for the AC test circuit.

Note6:Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device.It is derived by the equation(DJ OUT-DJ IN),where

DJ OUT is the total peak-to-peak deterministic jitter measured at the output of the device in ps(p-p).DJ IN is the peak-to-peak deterministic jitter at the input of the test

board.Please see Figure6for the AC test circuit.

Note7:t SKO is the magnitude difference in propagation delays between all data paths on one device.This is channel-to-channel skew.t SKPP is the worst case difference in propagation delay across multiple devices on all channels and operating under identical conditions.For example,for two devices operating under the

same conditions,t SKPP is the magnitude difference between the shortest propagation delay measurement on one device to the longest propagation delay measurement on another device.

Note8:This parameter is guaranteed by design and/or characterization and is not tested in production.

Note9:ESD tests conform to the following standards:

Human Body Model(HBM)applicable standard:MIL-STD-883,Method3015.7

Machine Model(MM)applicable standard:JESD22-A115-A(ESD MM std.of JEDEC)

Field-Induced Charge Device Model(CDM)applicable standard:JESD22-C101-C(ESD FICDM std.of JEDEC)

Timing Diagrams

20194236

FIGURE2.Driver Output Transition Time

DS25BR400

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Timing Diagrams

(Continued)

20194235

FIGURE 3.Propagation Delay

20194203

FIGURE 4.Loopback Delay Timing

20194239

FIGURE 5.Output De-Emphasis Duration

D S 25B R 400

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DS25BR400 Timing Diagrams(Continued)

20194234

FIGURE6.AC Test Circuit

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Physical Dimensions

inches (millimeters)unless otherwise noted

eLLP-60Package

Order Number DS25BR400TSQ NS Package Number SQA060

National does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.For the most current product information visit us at https://www.wendangku.net/doc/d35598929.html,.LIFE SUPPORT POLICY

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D S 25B R 400Q u a d T r a n s c e i v e r w i t h I n p u t

E q u a l i z a t i o n a n d O u t p u t D e -E m p h a s i s