LS7184-S中文资料
QUADRATURE CLOCK CONVERTER
FEATURES:
? x1, x2 and x4 resolution
? Programmable output pulse width (200ns to 140μs)? Excellent regulation of output pulse width ? TTL and low voltage CMOS compatible I/Os ? +3V to +5.5V operation (V DD - V SS )? LS7183, LS7184 (DIP);
LS7183-S, LS7184-S (SOIC) - See Figure 1
INPUT/OUTPUT DESCRIPTION:RBIAS (Pin 1)
Input for external component connection. A resistor connected between this input and V SS adjusts the output clock pulse width (Tow).
V DD (Pin 2)
Supply Voltage positive terminal.V SS (Pin 3)
Supply Voltage negative terminal .
A, B (Pin 4, Pin 5)
Quadrature Clock inputs A and B. Directional output pulses are generated from the A and B clocks according to Fig. 2. A and B inputs have built-in immunity for noise signals less than 50ns duration (Validation delay, T VD ). The A and B inputs are in-hibited during the occurrence of a directional output clock (UPCK or DNCK), so that spurious clocks resulting from en-coder dither are rejected.
MODE (Pin 6)
MODE is a 3-state input to select resolution x1, x2 or x4. The input quadrature clock rate is multiplied by factors of 1, 2 and 4
in x1, x2 and x4 mode respectively in producing the output UP/DN clocks (See Fig. 2). x1, x2 and x4 modes selected by the MODE input logic levels are as follows: Mode = 0 : x1 selected Mode = 1 : x2 selected Mode = Float : x4 selected LS7183 - DNCK (Pin 7)
In LS7183, this is the DOWN Clock Output. This output consists of low-going pulses generated when A input lags the B input.
LS7184 - UP/DN (Pin 7)
In LS7184, this is the count direction indication output.When A input leads the B input, the UP/DN output goes high indicating that the count direction is UP. When A input lags the B input, UP/DN output goes low, indicating that the count direction is DOWN.
LS7183 - UPCK (Pin 8)
In LS7183, this is the UP Clock output. This output con-sists of low-going pulses generated when A input leads the B input.
LS7184 - CLK (Pin 8)
In LS7184, this is the combined UP Clock and DOWN Clock output. The count direction at any instant is
indicated by the UP/DN output (Pin 7).
NOTE : For the LS7184, the timing of CLK and UP/DN requires that the counter interfacing with LS7184 counts
on the rising edge of the CLK pulses.
DESCRIPTION:
The LS7183 and LS7184 are CMOS quadrature clock con-verters. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B inputs of the LS7183/LS7184, are converted to strings of Up Clocks and Down Clocks (LS7183) or to a Clock and an Up/Down direction control (LS7184). These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder.
July 2003
RBIAS V DD(+V)V SS(-V)
A B MODE
DNCK UPCK PIN ASSIGNMENT - TOP VIEW
CLK
UP/DN FIGURE 1
123
4876
5
LS7184
RBIAS V DD(+V)
V SS(-V)
A B MODE
123
4
876
5LS7183
LSI
LSI
7183/84-071403-1
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
LS7183/LS7184
U L
?
A3800
ABSOLUTE MAXIMUM RATINGS:
PARAMETER SYMBOL VALUE UNITS
DC Supply Voltage V DD - V SS 7.0 V
Voltage at any input V IN V SS - 0.3 to V DD + 0.3 V
Operating temperature T A -20 to +85 °C
Storage temperature T STG -55 to +150 °C
DC ELECTRICAL CHARACTERISTICS:
(Unless otherwise specified V DD = 3V to 5V and TA = -20°C to +85°C)
PARAMETER SYMBOL MIN TYPE MAX UNITS CONDITON Supply Voltage V DD 3.0- 5.5V-
Supply current I DD-3045μA V DD = 3V
I DD-110150μA V DD = 5V
MODE input:
Logic 0V ml--0.6V-
Logic 1 V mh V DD - 0.6--V-
Logic float V mf(V DD/2) - 0.5V DD/2(V DD/2) + 0.5V-
Logic 0 input current I ml- 3.0 5.0μA V DD = 3V
I ml-12.016.0μA V DD = 5V
Logic 1 input current I mh--3.0-5.0μA V DD = 3V
I mh--12.0-16.0μA V DD = 5V
A,B inputs:
Logic 0 V ABl--0.3V DD V-
Logic 1V ABh0.7V DD--V-
Input current I ABlk-010nA-
RBIAS input:
External resistor R B5k-10M ohm-
All outputs:
Sink current I ol-1.2-1.8-mA Vo = 0.5V, V DD = 3V
I ol-2.5-3.5-mA Vo = 0.5V, V DD = 5V
Source current I oh 1.2 1.8-mA Vo = 2.5V, V DD = 3V
I oh 2.5 3.5-mA Vo = 4.5V, V DD = 5V TRANSIENT CHARACTERISTICS
(TA = -20°C to +85°C)
PARAMETER SYMBOL MIN TYPE MAX UNITS CONDITON Output Clock Pulse Width T OW190--ns See Fig. 2
A,B inputs:
Validation Delay T VD-2550ns V DD = 5V
T VD-50100ns V DD = 3V Phase Delay T PS T VD + T OW-Infinite s-
Pulse Width T PW2T PS-Infinite s-
Frequency f A,B--1/(2T PW)Hz-
Inupt to Output Delay T DS-200270ns V DD = 3V
T DS-110150ns V DD = 5V
7183/84-012703-2