部分作业解答
部分作业解答
1、简述WHEN_ELSE条件信号赋值语句和IF_ELSE顺序语句的异同。
答：WHEN_ELSE条件信号赋值语句中无标点，只有最后有分号；必须成对出现；
是并行语句，必须放在结构体中。IF_ELSE顺序语句中有分号；是顺序语句，必须放在进程中。
2、设计一个3-8译码器
输入端口：din 输入端，位宽为3位
EN 译码器输出使能，高电平有效
输出端口：xout 译码器输出，低电平有效
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODE3_8 IS
PORT ( DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
EN : IN STD_LOGIC;
XOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END DECODE3_8;
ARCHITECTURE ONE OF DECODE3_8 IS
BEGIN
PROCESS (DIN, EN)
BEGIN
IF EN = ‘1’ THEN
IF DIN = “111” THEN XOUT <= “”;
ELSIF DIN = “110” THEN XOUT <= “”;
ELSIF DIN = “101” THEN XOUT <= “”;
ELSIF DIN = “100” THEN XOUT <= “”;
ELSIF DIN = “011” THEN XOUT <= “”;
ELSIF DIN = “010” THEN XOUT <= “”;
ELSIF DIN = “001” THEN XOUT <= “”;
ELSE XOUT <= “”;
END IF;
END PROCESS;
END ONE;
3、具有清零端的4位二进制计数器如下图所示，请用VHDL语言编写其程序。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4 IS
PORT(CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
Q:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
ARCHITECTURE BEHAV OF CNT4 IS
BEGIN
PROCESS(CLR,CLK)
BEGIN
IF CLR='1' THEN Q<="0000";
ELSIF (CLK'EVENT AND CLK='1') THEN
Q<=Q+1;
END IF;
END PROCESS;
END BEHAV;
4、设计一数据选择器MUX,其系统模块图和功能表如下图所示。试采用下面三种方式中的两种来描述该数据选择器MUX的结构体。(a) if语句。(b) case 语句。(c) when else 语句。
SEL COUT
00
01
10
11
OTHERS
A or B
A xor B
A nor B
A and B
“XX”ARCHITECTURE ONE OF MYMUX IS
BEGIN
PROCESS (SEL, AIN, BIN)
BEGIN
IF SEL = “00” THEN COUT <= AIN OR BIN;
ELSIF SEL = “01” THEN COUT <= AIN XOR BIN;
ELSIF SEL = “10” THEN COUT <= AIN AND BIN;
ELSE COUT <= AIN NOR BIN;
END IF;
END PROCESS;
END ONE;
ARCHITECTURE TWO OF MYMUX IS
BEGIN
PROCESS (SEL, AIN, BIN)
BEGIN
CASE SEL IS
WHEN “00” => COUT <= AIN OR BIN;
WHEN “01” => COUT <= AIN XOR BIN;
WHEN “10” => COUT <= AIN AND BIN;
WHEN OTHERS => COUT <= AIN NOR BIN;
END CASE;
END PROCESS;
END TWO;
ARCHITECTURE THREE OF MYMUX IS
BEGIN
COUT <= AIN OR BIN WHEN SEL = “00” ELSE
AIN XOR BIN WHEN SEL = “01” ELSE
AIN AND BIN WHEN SEL = “10” ELSE AIN NOR BIN;
5、用VHDL语言描述共阳数码管的7段数码显示译码器的设计。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY DECL7S IS
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ;
END ;
ARCHITECTURE ONE OF DECL7S IS
BEGIN
PROCESS( A )
BEGIN
CASE A IS
WHEN "0000" => LED7S <= "1000000" ;
WHEN "0001" => LED7S <= "1111001" ;
WHEN "0010" => LED7S <= "0100100" ;
WHEN "0011" => LED7S <= "0110000" ;
WHEN "0100" => LED7S <= "0011001" ;
WHEN "0101" => LED7S <= "0010010" ;
WHEN "0110" => LED7S <= "0000010" ;
WHEN "0111" => LED7S <= "1111000" ;
WHEN "1000" => LED7S <= "0000000" ;
WHEN "1001" => LED7S <= "0010000" ;
WHEN "1010" => LED7S <= "0001000" ;
WHEN "1011" => LED7S <= "0000011" ;
WHEN "1100" => LED7S <= "1000110" ;
WHEN "1101" => LED7S <= "0100001" ;
WHEN "1110" => LED7S <= "0000110" ;
WHEN "1111" => LED7S <= "0001110" ;
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS ;
END ;
6、下图是一个含有上升沿触发的D触发器的时序电路，试写出此电路的VHDL设计文件。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1163.ALL;
ENTITY EXEN IS
PORT(
CL :IN STD_LOGIC;
CLK0 : IN STD_LOGIC;
OUT1: OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE HALARCH OF EXEN IS