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STPIC6A259中文资料

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March 2001s LOW R DS(on): 1? TYP

s OUTPUT SHORT-CIRCUIT PROTECTION s 75mJ AVAILANCHE ENERGY s EIGHT 350mA DMOS OUTPUTS s 50V SWITCHING CAPABILITY

s FOUR DISTINCT FUNCTION MODES s

LOW POWER CONSUMPTION

DESCRIPTION

This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers,and decoders or demultiplexers. This is a multifunctional device capable of operating as eight addressable latches or an 8-line demultiplexer with active-low DMOS outputs.Each open-drain DMOS transistor features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit.

Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs and enumerated in the function table. In the addressable-latch mode, data at the data-in (D)terminal is written into the addressed latch. The addressed DMOS-transistor output inverts the data input with all unadressed DMOS-transistor output remaining in their previuous state. In the MOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneus data in the latch, enable G should be held high (inactive) while the address lines are changing. In the 8-line demoultiplexing mode, the addressed output is inverted with respectto the D input and all other output are high. In the clear mode, all outputs are high and unaffected by the address and data inputs.

Separate power ground (PGND) and logic ground (LGND) terminals are providied to facilitate maximum system flexibility. All PGND terminals are interally connected, and each pGND terminal must be externally connected to the power system ground in order to minimize parasitic impedance.A single-point connection between LGND and PGND must be made externally in a manner that reduces crosstalk between the logi and load circuits.

The STPIC6A259 is offered in a termally enhanced SO-24 package. The STPIC6A259 is characterized for operation over the operating case temperature range -40°C to 125°C.

ORDERING CODES

Type Package

Comments

STPIC6A259M SO-24 Batwing (Tube)50parts per tube / 20tube per box

STPIC6A259MTR

SO-24 Batwing (Tape & Reel)

2500 parts per reel

STPIC6A259

POWER LOGIC 8-BIT ADDRESSABLE LATCH

This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.

PRELIMINARY DATA

STPIC6A259

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LOGIC SYMBOL AND PIN CONFIGURATION

FUNCTIONAL TABLE

INPUT AND OUTPUT EQUIVALENT CIRCUITS

INPUTS OUTPUT OF ADDRESSED DRAIN EACH OTHER DRAIN FUNCTION CLR G D H L H L Q io Addressable Latch H L L H Q io H H X Q io Q io Memory L L H L H 8-Line

Demultiplexer L L L H H L

Clear

SELECT INPUTS DRAIN ADDRESSED

S2S1S0L L L 0L L H 1L H L 2L H H 3H L L 4H L H 5H H L 6H

STPIC6A259 ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit V CC Logic Supply Voltage (See Note 2)7V V I Logic Input Voltage Range-0.3 to 7V V DS Power DMOS Drain to Source Voltage (See Note 2)50V

I DS Continuous Source to Drain Diode Anode Current 1A

I DS Pulsed Source to Drain Diode Anode Current (See Note 3)2A

I D Pulsed Drain Current, Each Output, All Output ON (T C=25°C) 1.1A

I D Continuous Current, Each Output, All Output ON (T C=25°C)350mA

I D Peak Drain Current Single Output (T C=25°C) (See Note 3) 1.1A

E AS Single Pulse Avalanche Energy (See Note 6)75mJ

I AS Avalanche Current (See Note 4)600mA

P d Continuous total dissipation (T C≤ 25°C)1750mW P d Continuous total dissipation (T C = 125°C)350mW T J Operating Virtual Junction Temperature Range-40 to +150°C T C Operating Case Temperature Range-40 to +125°C T stg Storage Temperature Range-65 to +150°C T L Lead Temperature 1.6mm (1/16inch) from case for 10 seconds260°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.

THERMAL DATA

Symbol Parameter Unit R thj-case Thermal Resistance Junction-case10°C/W R thj-amb Thermal Resistance Junction-ambient50°C/W

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min.Max.Unit V CC Logic Supply Voltage 4.5 5.5V V IH High Level Input Voltage0.85V CC V CC V V IL Low Level Input Voltage00.15V CC V

I DP Pulse Drain Output Current (T C=25°C, V CC=5V) (see note 3, 5)-1.80.6A

t su Set-up Time, D High Before G ↑ (see Figure 2)10ns t h Hold Time, D High Before G ↑ (see Figure 2)5ns t W Pulse Duration (see Figure 2)15ns T C Operating Case Temperature-40125°C

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STPIC6A259

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DC CHARACTERISTICS (V CC =5V, T C = 25°C, unless otherwise specified.)

SWITCHING CHARACTERISTICS (V CC =5V, T C = 25°C, unless otherwise specified.)

Note 1: All Voltage valuea are with respect to LGND and PGND Note 2: Each power DMOS source is internally connected to GND Note 3: Pulse duration ≤ 100ms and duty cycle ≤ 2%

Note 4: Drain Supply Voltage = 15V, starting junction temperature (T JS ) = 25°C. L = 210μH and I AS = 600mA (See Fig. 6)Note 5: Technique should limit T J - T C to 10°C maximum

Note 6: These parameters are measured with voltage sensing contacts separate from the current-carrying contacts.

Note 7: Nominal Current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5V at T C = 85°C.

Symbol

Parameter

Test Conditions

Min.Typ.

Max.

Unit V (BR)DSX Drain-to-Source breakdown Voltage

I D = 1mA

V V SD Source-to-Drain Diode Forward Voltage

I F = 350 mA (See Note 3)

0.8

1.1V I IH High Level Input Current V I = V CC

1μA I IL Low Level Input Current V I = 0-1

μA I CC Logic Supply Current I O = 0

0.5

5mA I OK Output Current at Which

Chopping Starts T C = 25°C (See Note 3 and Figg. 3, 4)

0.6

0.8 1.1

A I (nom)

Nominal Current

V DS(on) = 0.5V I (nom) = I D V CC = 5V T C =85°C (See Note 5, 6, 7)350

I D

Off-State Drain Current V DS = 40V T C =25°C 0.11μA V DS = 40V

T C =125°C 0.25μA R DS(on)

Termination Resistance

(See Note 5, 6 and figg. 9, 10)

I D = 350mA T C =25°C 1 1.5?I D = 350mA

T C =125°C

1.7

2.5

Symbol Parameter

Test Conditions

Min.

Typ.Max.

Unit t PHL Propagation Dealy Time, High to Low Level Output from D

C L = 30pF I

D = 350mA (See Figg. 1, 2, 11)

t PLH Propagation Dealy Time, Low to High Level Output from D

125ns

t r Rise Time, Drain Output 60ns t f Fall Time, Drain Output

30ns t a Reverse Recovery Current Rise Time I F = 350mA di/dt = 20A/μs (See Note 5, 6 and Fig. 5)100ns t rr

Reverse Recovery Time

300

STPIC6A259 LOGIC DIAGRAM

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STPIC6A259

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TYPICAL OPERATION MODE TEST CIRCUITS

TYPICAL OPERATION MODE WAVEFORMS

NOTE:

A) The word generator has the following characteristics: t r ≤ 10ns, t f ≤ 10ns, t W = 300ns, pulse repetition rate (PRR) = 5KHz, Z O = 50?B) C L

includes probe and jig capacitance.

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TYPICAL OPERATION MODE TEST CIRCUITS

SWITCHING TIME WAVEFORM

INPUT SETUP AND HOLD WAVEFORM

NOTE:

A) The word generator has the following characteristics: t r ≤ 10ns, t f ≤ 10ns, t W = 300ns, pulse repetition rate (PRR) = 5KHz, Z O = 50?B) C L

includes probe and jig capacitance.

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REVERSE RECOVERY CURRENT TEST CIRCUITS

SOURCE DRAIN DIODE WAVEFORM

NOTE:

A) The V GG amplitude and R G are adjusted for di/dt = 20A/μs. A V GG double-pulse trainn is used to set I F = 0.35A. where t 1 = 10μs, t 2 = 7μs and t 3 = 3μs

B) The Drain terminal under test is connected to the TPK test point. All other terminals are connected together and connected to the TPA test point.

C) I RM

= maximum recovery current.

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SINGLE PULSE AVALANCHE ENERGY TEST CIRCUITS

SINGLE PULSE AVALANCHE ENERGY WAVEFORM

NOTE:

A) The word generator has the following characteristics: t r ≤ 10ns, t f ≤ 10ns, Z O = 50?

B) Input pulse duration, tW is increased until peak current IAS = 600 mA. Energy test level is defined as E AS = (I AS x V (BR)DSX x t AV

)/2 = 75mJ.

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TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified T j = 25°C) Figure 1 : Maximum Continuous Drain Current vs

Figure 2 : Static Drain-Source ON-State Resistance vs Drain Current Figure 3 : MaximumPeak Drain Current vs

Number of Outputs Conducting Simultaneously Figure 4 : Static Drain-Source ON-State Resistance vs Logic Supply Voltage

Figure 5 : Chopping Mode Characteristics

Figure 6 : Output Current vs Case Temperature

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Figure 7 : Switching Time vs Case Temperature

Figure 8 : Switching Time vs Case Temperature

STPIC6A259 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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