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MAX1121EGK-TD中文资料

General Description

The MAX1121 is a monolithic 8-bit, 250Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high IF frequencies up to 500MHz. The product operates with conversion rates of up to 250Msps while consuming only 477mW.

At 250Msps and an input frequency of 100MHz, the MAX1121 achieves a spurious-free dynamic range (SF DR) of 68dBc. Its excellent signal-to-noise ratio (SNR) of 48.9dB at 10MHz remains flat (within 0.5dB)for input tones up to 500MHz. This makes the MAX1121ideal for wideband applications such as digital predis-tortion in cellular base-station transceiver systems.

The MAX1121 requires a single 1.8V supply. The ana-log input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2clock circuit, which allows the user to apply clock fre-quencies as high as 500MHz. This helps to reduce the phase noise of the input clock source. A differential LVDS sampling clock is recommended for best perfor-mance. The converter’s digital outputs are LVDS com-patible, and the data format can be selected to be either two’s complement or offset binary.

The MAX1121 is available in a 68-pin QF N with exposed pad (EP) and is specified over the industrial (-40°C to +85°C) temperature range.

F or pin-compatible, higher resolution versions of the MAX1121, refer to the MAX1122 (170Msps), the MAX1123 (210Msps), and the MAX1124 (250Msps)data sheets.

Applications

Wireless and Wired Broadband Communication Digital Oscilloscopes

Digital Predistortion Receivers Communications Test Equipment

Radar and Satellite Subsystems Antenna Array Processing Instrumentation

Features

?250Msps Conversion Rate

?SNR = 48.8dB/48.7dB at f IN = 100MHz/500MHz ?SFDR = 68dBc/63.8dBc at f IN = 100MHz/500MHz ?Single 1.8V Supply

?477mW Power Dissipation at 250Msps

?On-Chip Track-and-Hold and Internal Reference ?On-Chip Selectable Divide-by-2 Clock Input ?LVDS Digital Outputs with Data Clock Output ?Evaluation Kit Available (Order MAX1124EVKIT)

MAX1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

PART TEMP RANGE PIN-PACKAGE MAX1121EGK

-40°C to +85°C

68 QFN-EP*

Pin Configuration

Ordering Information

19-3077; Rev 2; 8/08

For pricing, delivery, and ordering information,please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at https://www.wendangku.net/doc/da10132830.html,.

________________________________________________________________Maxim Integrated Products

M A X 1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 2_______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AV CC to AGND......................................................-0.3V to +2.1V OV CC to OGND.....................................................-0.3V to +2.1V AV CC to OV CC .......................................................-0.3V to +2.1V AGND to OGND ....................................................-0.3V to +0.3V Analog Inputs to AGND...........................-0.3V to (AV CC + 0.3V)Digital Inputs to AGND.............................-0.3V to (AV CC + 0.3V)REF, REFADJ to AGND............................-0.3V to (AV CC + 0.3V)Digital Outputs to OGND.........................-0.3V to (OV CC + 0.3V)ESD on All Pins (Human Body Model).. (2000)

Continuous Power Dissipation (T A = +70°C)

68-Pin QFN (derate 41.7mW/°C above +70°C).........3333mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-60°C to +150°C Lead Temperature (soldering, 10s).................................+300°C Maximum Current into Any Pin............................................50mA

ELECTRICAL CHARACTERISTICS

(AV CC = OV CC = 1.8V, V AGND = V OGND = 0, f SAMPLE = 250MHz, differential sine-wave clock input drive, 0.1μF capacitor on REFIO,

MAX1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

_______________________________________________________________________________________3

ELECTRICAL CHARACTERISTICS (continued)

(AV CC = OV CC = 1.8V, V AGND = V OGND = 0, f SAMPLE = 250MHz, differential sine-wave clock input drive, 0.1μF capacitor on REFIO,

M A X 1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 4_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV CC = OV CC = 1.8V, V AGND = V OGND = 0, f SAMPLE = 250MHz, differential sine-wave clock input drive, 0.1μF capacitor on REFIO,

Note 2:Parameter guaranteed by design and characterization; T A = T MIN to T MAX .

Note 3:PSRR is measured with both analog and digital supplies connected to the same potential.

MAX1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

Typical Operating Characteristics

(AV CC = OV CC = 1.8V, V AGND = V OGND = 0, f SAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-tions, differential input drive, differential sine-wave clock input drive, 0.1μF capacitor on REFIO, internal reference, digital output pins differential R L = 100Ω, T A = +25°C.)

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-80-90

-60-70-40-50-30-10-200FFT PLOT (8192-POINT DATA RECORD,

COHERENT SAMPLING)

ANALOG INPUT FREQUENCY (MHz)A M P L I T U D E (d B )

100

140120

f SAMPLE = 250.0057MHz f IN = 11.5054MHz A IN = -0.4885MHz SNR = 48.9dB SFDR = 71.5dBc HD2 = -79.2dBc HD3 = -74.6dBc

HD2HD3

-90

-80-60-70-40-50-30-10-200FFT PLOT (8192-POINT DATA RECORD,

COHERENT SAMPLING)

ANALOG INPUT FREQUENCY (MHz)A M P L I T U D E (d B )

040608020100140120f SAMPLE = 250.0057MHz f IN = 60.0294MHz A IN = -0.4885MHz SNR = 49dB SFDR = 71.1dBc HD2 = -79.5dBc HD3 = -71.9dBc

HD2

HD3

-80-90

-60-70-40-50-30-10-200

040608020100140

120FFT PLOT (8192-POINT DATA RECORD,

COHERENT SAMPLING)

ANALOG INPUT FREQUENCY (MHz)

A M P L I T U D E (d

B )f SAMPLE = 250.0057MHz f IN = 183.5064MHz A IN = -0.5245MHz SNR = 48.8dB SFDR = 69.1dBc HD2 = -77.2dBc HD3 = -69.1dBc

HD2

HD3

-80-90

-60-70-40-50-30-10-200FFT PLOT (8192-POINT DATA RECORD,

COHERENT SAMPLING)

ANALOG INPUT FREQUENCY (MHz)

A M P L I T U D E (d

B )0

40608020100140

120HD3

HD2

f SAMLE = 250.0057MHz f IN = 500.516MHz A IN = -0.5235MHz SNR = 48.8dB SFDR = 63.8dBc HD2 = -70.8dBc HD3 = -63.8dBc

FUNDAMENTAL

SNR vs. ANALOG INPUT FREQUENCY (f SAMPLE = 250.0057MHz, A IN = -0.5dBFS)

SFDR vs. ANALOG INPUT FREQUENCY (f SAMPLE = 250.0057MHz, A IN = -0.5dBFS)

HD2/HD3 vs. ANALOG INPUT FREQUENCY SAMPLE = 250.0057MHz, A IN = -0.5dBFS)

f IN (MHz)

H D 2/H D 3 (d B c )

400

300

200

100

-90

-80

-70

-60-50

-100

500

HD3

HD2

-30-15-10-25-20-50ANALOG INPUT AMPLITUDE (dBFS)-30-15-10-25-20-50

ANALOG INPUT AMPLITUDE (dBFS)

M A X 1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 6_______________________________________________________________________________________

Typical Operating Characteristics (continued)

-90-65-75-85-70-80-50-55-60-40-45-35-30-30

-20

-15

-25

-10

-5

HD2/HD3 vs. ANALOG INPUT AMPLITUDE (f SAMPLE = 250.0057MHz, f IN = 60.0294MHz)

ANALOG INPUT AMPLITUDE (dBFS)

H D 2/H D 3 (d B c )

SNR vs. f SAMPLE

(f IN = 60.0294MHz, A IN = -0.5dBFS)

M A X 1121 t o c 11

f SAMPLE (MHz)

S N R (d B )

47.047.548.048.549.046.5

260

180

140

100

220

SFDR vs. f SAMPLE

(f IN = 60.0294MHz, A IN = -0.5dBFS)

M A X 1121 t o c 12

f SAMPLE (MHz)

S F D R (d B c )

220

140

100

4020

260

180

HD2/HD3 vs. f SAMPLE

(f IN = 60.03294MHz, A IN = -0.5dBFS)

f SAMPLE (MHz)

H D 2/H D 3 (d B c )

220

180

140

100

-92

-84

-76

-68-60-100

260

-80

-90

-60-70-40-50-30-10-200TWO-TONE IMD PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING)

ANALOG INPUT FREQUENCY (MHz)

A M P L I T U D E (d

B )0

100

140

120

f SAMPLE = 250.0057MHz f IN1 = 99.0318MHz f IN2 = 101.046MHz A IN1 = A IN2 = -7dBFS

IMD = -70dBc

2f IN1 - f IN2

2f IN2 -

f IN1

f IN1f IN2-0.5

-0.3-0.4-0.1-0.20.100.20.40.30.5

6496320128160192224256

INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE

M A X 1121 t o c 15

DIGITAL OUTPUT CODE

I N L (L S B )

-0.5

-0.4-0.20.10.30.50.4

0-0.3-0.10.264

128160192224256

DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE

M A X 1121 t o c 16

DIGITAL OUTPUT CODE

D N L (L S B )

20-2-4-6-8-10-12

100

1000GAIN BANDWIDTH PLOT

(f SAMPLE = 250.0057MHz, A IN = -0.5dBFS)

ANALOG INPUT FREQUENCY (MHz)

G A I N (d B )

SNR vs. TEMPERATURE (f IN = 65.0108MHz,f SAMPLE = 249.856MHz, A IN = -0.5dBFS)

M A X 1121 t o c 18

TEMPERATURE (°C)

S N R (d B )603510-1547.046.548.047.549.048.549.550.0

46.0

-4085

MAX1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

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Typical Operating Characteristics (continued)

SINAD vs. TEMPERATURE (f IN = 65.0108MHz f SAMPLE = 249.856MHz, A IN = -0.5dBFS)

TEMPERATURE (°C)

S I N A D (d B )

-15

50.049.549.048.548.047.547.046.546.0

-40

M A X 1121 t o c 19

SFDR vs. TEMPERATURE (f IN = 65.0108MHz,f SAMPLE = 249.856MHz, A IN = -0.5dBFS)

TEMPERATURE (°C)

S F D R (d B c )

-15

7550-40

POWER DISSIPATION vs. f SAMPLE (f IN = 60.0294MHz, A IN = -0.5dBFS)

f SAMPLE (MHz)

P D I S S (m W )

180

140

100

420410

440430

460450470480490

400

260

220

FS VOLTAGE vs. FS ADJUST RESISTOR

FS ADJUST RESISTOR (Ω)

V F S (V )

9008006007002003004005001001.181.201.221.241.261.281.301.321.341.16

01000

SNR vs. SUPPLY VOLTAGE (f IN = 60.0294MHz, A IN = -0.5dBFS)

SUPPLY VOLTAGE (V)

S N R (d B )

2.0

1.9

1.8

1.7

1.6

494847

46454443

1.5

2.1

INTERNAL REFERENCE vs. SUPPLY VOLTAGE

(f SAMPLE = 250.0057MHz)

SUPPLY VOLTAGE (V)

V R E F I O (V )

2.0

1.9

1.8

1.7

1.6

1.2310

1.2320

1.2330

1.2340

1.2350

1.2300

1.5

2.1

0.0E+00

4.0E+04

1.2E+05

8.0E+04

1.6E+05

2.0E+05126

127

128

NOISE HISTOGRAM

(DC INPUT, 256k-POINT DATA RECORD)

DIGITAL OUTPUT NOISE

C O

E C O U N T S PROPAGATION DELAY TIMES

vs. TEMPERATURE

TEMPERATURE (°C)

P R O P A G A T I O N D E L A Y (n s )

-15

234560-40

46.0

49.548.548.049.0

47.0

46.547.550.0

SINAD vs. CLOCK DUTY CYCLE (f IN = 1.8148MHz,

f SAMPLE = 249.856MHz, A IN = -0.5dBFS)

CLOCK DUTY CYCLE (%)

S I N A D (d B )

M A X 1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 8_______________________________________________________________________________________

MAX1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

_______________________________________________________________________________________9

Figure 1. MAX1121 Block Diagram

M A X 1121

Detailed Description— Theory of Operation

The MAX1121 uses a fully differential, pipelined archi-tecture that allows for high-speed conversion, opti-mized accuracy and linearity, while minimizing power consumption and die size.

Both positive (INP) and negative/complementary analog input terminals (INN) are centered around a common-mode voltage of 1.4V, and accept a differential analog input voltage swing of ±0.3125V each, resulting in a typi-cal differential full-scale signal swing of 1.25V P-P .

INP and INN are buffered prior to entering each track-and-hold (T/H) stage and are sampled when the differen-tial sampling clock signal transitions high. A 2-bit ADC following the first T/H stage then digitizes the signal, and controls a 2-bit digital-to-analog converter (DAC).

Digitized and reference signals are then subtracted,resulting in a fractional residue signal that is amplified before it is passed on to the next stage through another T/H amplifier. This process is repeated until the applied input signal has successfully passed through all stages of the 8-bit quantizer. F inally, the digital outputs of all stages are combined and corrected for in the digital cor-rection logic to generate the final output code. The result is a 8-bit parallel digital output word in user-selectable two’s complement or binary output formats with LVDS-compatible output levels. See F igure 1 for a more detailed view of the MAX1121 architecture.

Analog Inputs (INP, INN)

INP and INN are the fully differential inputs of the MAX1121. Differential inputs usually feature good rejec-tion of even-order harmonics, which allows for enhanced AC performance as the signals are progressing through the analog stages. The MAX1121 analog inputs are self-biased at a common-mode voltage of 1.4V and allow a differential input voltage swing of 1.25V P-P . Both inputs are self-biased through 2.2k Ωresistors, resulting in a typical differential input resistance of 4.4k Ω. It is recom-mended to drive the analog inputs of the MAX1121 in AC-coupled configuration to achieve best dynamic per-formance. See the AC-Coupled Analog Inputs section for a detailed discussion of this configuration.

On-Chip Reference Circuit

The MAX1121 features an internal 1.23V bandgap ref-erence circuit (Figure 3), which, in combination with an internal reference-scaling amplifier, determines the full-scale range of the MAX1121. Bypass REF IO with a 0.1μF capacitor to AGND. To compensate for gain errors or increase the ADC’s full-scale range, the volt-age of this bandgap reference can be indirectly adjust-ed by adding an external resistor (e.g., 100k Ωtrim potentiometer) between REF ADJ and AGND or REF ADJ and REF IO. See the Applications Information section for a detailed description of this process.

Clock Inputs (CLKP, CLKN)

Designed for a differential LVDS clock input drive, it is recommended to drive the clock inputs of the MAX1121with an LVDS-compatible clock to achieve the best dynamic performance. The clock signal source must be a high-quality, low phase noise to avoid any degrada-tion in the noise performance of the ADC. The clock inputs (CLKP, CLKN) are internally biased to 1.2V,accept a differential signal swing of 0.2V P-P to 1.0V P-P

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 10

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Figure 3. Simplified Reference Architecture

and are usually driven in AC-coupled configuration.See the Differential, AC-Coupled Clock Input in the Applications Information section for more circuit details on how to drive CLKP and CLKN appropriately.Although not recommended, the clock inputs also accept a single-ended input signal.

The MAX1121 also features an internal clock manage-ment circuit (duty-cycle equalizer) that ensures that the clock signal applied to inputs CLKP and CLKN is processed to provide a 50% duty cycle clock signal,which desensitizes the performance of the converter to variations in the duty cycle of the input clock source.Note that the clock duty-cycle equalizer cannot be turned off externally and requires a minimum clock fre-quency of >20MHz to work appropriately and accord-ing to data sheet specifications.

Clock Outputs (DCLKP, DCLKN)

The MAX1121 features a differential clock output, which can be used to latch the digital output data with an external latch or receiver. Additionally, the clock output can be used to synchronize external devices (e.g.,FPGAs) to the ADC. DCLKP and DCLKN are differential outputs with LVDS-compatible voltage levels. There is a 2.1ns delay time between the rising (falling) edge of CLKP (CLKN) and the rising edge of DCLKP (DCLKN).See Figure 4 for timing details.

MAX1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

______________________________________________________________________________________

Figure 4. System and Output Timing Diagram

Figure 5. Simplified LVDS Output Architecture

M A X 1121

Divide-by-2 Clock Control (CLKDIV)

The MAX1121 offers a clock control line (CLKDIV),which supports the reduction of clock jitter in a system.Connect CLKDIV to OGND to enable the ADC’s internal divide-by-2 clock divider. Data is now updated at one-half the ADC’s input clock rate. CLKDIV has an internal pulldown resistor and can be left open for applications that only operate with update rates one-half of the con-verter’s sampling rate. Connecting CLKDIV to OV CC allows data to be updated at the speed of the ADC input clock.

System Timing Requirements

F igure 4 depicts the relationship between the clock input and output, analog input, sampling event, and data output. The MAX1121 samples on the rising (falling) edge of CLKP (CLKN). Output data is valid on the next rising (falling) edge of the DCLKP (DCLKN)clock, but has an internal latency of nine clock cycles.

Digital Outputs (D0P/N–D7P/N, DCLKP/N,

ORP/N) and Control Input T /B

The digital outputs D0P/N–D7P/N, DCLKP/N, and ORP/N are LVDS compatible, and data on D0P/N–D7P/N is pre-sented in either binary or two’s complement format (Table

1). The T /B control line is an LVCMOS-compatible input,which allows the user to select the desired output for-mat. Pulling T /B low outputs data in two’s complement and pulling it high presents data in offset binary format on the 10-bit parallel bus. T /B has an internal pulldown resistor and may be left unconnected in applications using only two’s complement output format. All LVDS outputs provide a typical voltage swing of 0.4V around a common-mode voltage of approximately 1.2V, and must be terminated at the far end of each transmission line pair (true and complementary) with 100Ω. The LVDS outputs are powered from a separate power sup-ply, which can be operated between 1.7V and 1.9V.The MAX1121 offers an additional differential output pair (ORP, ORN) to flag out-of-range conditions, where out of range is above positive or below negative full scale. An out-of-range condition is identified with ORP (ORN) transitioning high (low).

Note:Although differential LVDS reduces single-ended transients to the supply and ground planes, capacitive loading on the digital outputs should still be kept as low as possible. Using LVDS buffers on the digital outputs of the ADC when driving off-board may improve overall performance and reduce system timing constraints.

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 12______________________________________________________________________________________

Applications Information

Full-Scale Range Adjustments Using the

Internal Bandgap Reference

The MAX1121 supports a full-scale adjustment range of 10% (±5%). To decrease the full-scale range, an exter-nal resistor value ranging from 13k Ωto 1M Ωmay be added between REF ADJ and AGND. A similar approach can be taken to increase the ADCs full-scale range. Adding a variable resistor, potentiometer, or predetermined resistor value between REF ADJ and REF IO increases the full-scale range of the data con-verter. F igure 6 shows the two possible configurations and their impact on the overall full-scale range adjust-ment of the MAX1121. Do not use resistor values of less than 13k Ωto avoid instability of the internal gain regula-tion loop for the bandgap reference.

Differential, AC-Coupled, PECL-Compatible

Clock Input

The preferred method of clocking the MAX1121 is differ-entially with LVDS- or PECL-compatible input levels. To accomplish this, a 50Ωreverse-terminated clock signal source with low phase noise is AC-coupled into a fast dif-ferential receiver such as the MC100LVEL16 (F igure 7).The receiver produces the necessary PECL output levels to drive the clock inputs of the data converter.

MAX1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

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Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale Range

Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration

M A X 1121

Differential, AC-Coupled Analog Input

An RF transformer provides an excellent solution to convert a single-ended source signal to a fully differen-tial signal, required by the MAX1121 for optimum dynamic performance. In general, the MAX1121 pro-vides the best SF DR and THD with fully differential input signals and it is not recommended to drive the ADC inputs in single-ended configuration. In differential input mode, even-order harmonics are usually lower since INP and INN are balanced, and each of the ADC inputs only requires half the signal swing compared to a single-ended configuration.

Figure 8 depicts a secondary-side termination of the 1:1transformer into two separate 25Ωloads. Terminating the transformer in this fashion reduces the potential effects of transformer parasitics. The source impedance combined with the shunt capacitance provided by a PCB and the ADC’s parasitic capacitance reduce the combined bandwidth to approximately 550MHz.

Single-Ended, AC-Coupled Analog Input

Although not recommended, the MAX1121 can be used in single-ended mode (F igure 9). Analog signals can be AC-coupled to the positive input INP through a 0.1μF capacitor and terminated with a 50Ωresistor to AGND. The negative input should be 25Ωreverse-ter-minated and AC grounded with a 0.1μF capacitor.

Grounding, Bypassing, and Board

Layout Considerations

The MAX1121 requires board layout design techniques suitable for high-speed data converters. This ADC pro-vides separate analog and digital power supplies. The analog and digital supply voltage pins accept input voltage ranges of 1.7V to 1.9V. Although both supply

types can be combined and supplied from one source,it is recommended to use separate sources to cut down on performance degradation caused by digital switch-ing currents, which can couple into the analog supply network. Isolate analog and digital supplies (AV CC and OV CC ) where they enter the PCB with separate net-works of ferrite beads and capacitors to their corre-sponding grounds (AGND, OGND).

To achieve optimum performance, provide each supply with a separate network of a 47μF tantalum capacitor in parallel with 10μF and 1μF ceramic capacitors.Additionally, the ADC requires each supply pin to be bypassed with separate 0.1μF ceramic capacitors (Figure 10). Locate these capacitors directly at the ADC supply pins or as close as possible to the MAX1121.Choose surface-mount capacitors, which are preferably located on the same side as the converter, to save space and minimize the inductance.

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 14______________________________________________________________________________________

Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination

Figure 9. Single-Ended AC-Coupled Analog Input Configuration

Multilayer boards with separated ground and power planes produce the highest level of signal integrity.Consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the ADC’s package. The two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. A major concern with this approach are the dynamic currents that may need to travel long dis-tances before they are recombined at a common source ground, resulting in large and undesirable ground loops. Ground loops can add to digital noise by coupling back to the analog front end of the converter,resulting in increased spur activity and a decreased noise performance.

Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground. To minimize the effects of digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching currents away from the sensitive analog sec-tions of the ADC. This does not require additional ground splitting, but can be accomplished by placing substantial ground connections between the analog front end and the digital outputs.

The MAX1121 is packaged in a 68-pin QF N-EP pack-age (package code: G6800-4), providing greater design flexibility, increased thermal efficiency, and opti-mized AC performance of the ADC. The EP must be soldered down to AGND.

In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PCB side of the package. This allows a solid attachment of the package to the PCB with standard infrared (IR) flow sol-dering techniques.

Note that thermal efficiency is not the key factor, since the MAX1121 features low-power operation. The exposed pad is the key element to ensure a solid ground connection between the DAC and the PCB’s analog ground layer.

Considerable care must be taken, when routing the digital output traces for a high-speed, high-resolution data converter. It is essential to keep trace lengths at a minimum and place minimal capacitive loading (less than 5pF ) on any digital trace to prevent coupling to sensitive analog sections of the ADC. It is recommend-ed to run the LVDS output traces as differential lines with 100Ωcharacteristic impedance from the ADC to the LVDS load device.

MAX1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

______________________________________________________________________________________15

Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1121

M A X 1121

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. However, the static linearity parameters for the MAX1121 are mea-sured using the histogram method with an input fre-quency of 10MHz.

Differential Nonlinearly (DNL)

Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. The MAX1121’s DNL specification is measured with the his-togram method based on a 10MHz input tone.

Dynamic Parameter Definitions

Aperture Jitter

F igure 11 depicts the aperture jitter (t AJ ), which is the sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (t AD ) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 11).

Signal-to-Noise Ratio (SNR)

F or a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantiza-tion error only and results directly from the ADC’s reso-lution (N bits):

SNR dB[max]= 6.02dB x N + 1.76dB

In reality, other noise sources such as thermal noise,clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the SNR calcula-tion and should be considered when determining the SNR in ADC.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig-nal to all spectral components excluding the fundamen-tal and the DC offset. In case of the MAX1121, SINAD is computed from a curve fit.

Spurious-Free Dynamic Range (SFDR)

SF DR is the ratio of RMS amplitude of the carrier fre-quency (maximum signal component) to the RMS value of the next-largest noise or harmonic distortion compo-nent. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the ADC’s full-scale range.

Two-Tone Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) inter-modulation products. The individual input tone levels are at -7dB full scale.

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 16______________________________________________________________________________________

Figure 11. Aperture Jitter/Delay Specifications

Pin-Compatible Higher Resolution Versions

Package Information

For the latest package outline information and land patterns, go to https://www.wendangku.net/doc/da10132830.html,/packages .

MAX1121

1.8V , 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

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