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IDT74ALVC1G00中文资料

IDT74ALVC1G00

FUNCTIONAL BLOCK DIAGRAM

3.3V CMOS

SINGLE 2-INPUT POSITIVE-NAND GATE

DESCRIPTION:

This single 2-input positive-NAND gate is built using advanced dual metal CMOS technology. The ALVC1G00 is designed for 1.65V to 3.6V V CC operation and performs the Boolean function Y = A ? B or Y = A + B in positive logic.

The ALVC1G00 has been designed with a ±24mA output driver.This driver is capable of driving a moderate to heavy load while maintaining speed performance.

APPLICATIONS:

? 3.3V High Speed Systems

? 3.3V and lower voltage computing systems

FEATURES:

–0.5 MICRON CMOS Technology

ESD > 2000V per MIL-STD-883, Method 3015;> 200V using machine model (C = 200pF, R = 0)–

0.65mm pitch PSOP package

–Extended commercial range of – 40°C to + 85°C –V CC = 3.3V ± 0.3V, Normal Range –V CC = 1.65V to 3.6V, Extended Range –V CC = 2.5V ± 0.2V

–CMOS power levels (0.4μW typ. static)

–Rail-to-Rail output swing for increased noise margin Drive Features for ALVC1G00:–High Output Drivers: ±24mA

–Suitable for heavy loads PIN CONFIGURATION

PSOP TOP VIEW

NOTE:

1.H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

(1)

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

CC

(1)

o NOTES:

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.V CC terminals.

3. All terminals except V CC .

NOTE:

1. As applicable to the device type.

NOTE:

1. Typical values are at V CC = 3.3V, +25°C ambient.

NOTE:

1. V IH and V IL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the

appropriate V CC range. T A = – 40°C to + 85°C.

o

(1)

NOTE:

1. See test circuits and waveforms. T A = – 40°C to + 85°C.

TEST CIRCUITS AND WAVEFORMS:

1.8V ± 0.15V TEST CIRCUITS AND WAVEFORMS:

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The IDT logo is a registered trademark of Integrated Device Technology, Inc.

ORDERING INFORMATION

CORPORATE HEADQUARTERS for SALES:

2975 Stender Way 800-345-7015 or 408-727-6116Santa Clara, CA 95054

fax: https://www.wendangku.net/doc/da10817755.html,*

PICOGATE-LOGIC (DY) PACKAGES

Due to their small size, PicoGate-Logic packages require more complex symbolization guidelines. IDT’s 5-pin PSOP (DY) packaged devices utilize a three-symbol name rule. The first symbol denotes device technology, the second symbol denotes device function, and the third symbol denotes a wafer fab/assembly site code for internal tracking.

EXAMPLES:

1. A PicoGate-Logic device with package code LR* is an IDT74LVC1G79A.

2. A PicoGate-Logic device with package code GC* is an IDT74ALVC1G04.PICOGATE-LOGIC (DY) PACKAGE SYMBOLIZATION GUIDELINES NOTE:

1. Code to be determined.

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