HT48R70A-1中文资料
HT48R70A-1/HT48C70-1
I/O Type 8-Bit MCU
Rev.1.601June 9,2004
General Description
The HT48R70A-1/HT48C70-1are 8-bit high perfor-mance,RISC architecture microcontroller devices spe-cifically designed for multiple I/O control product applications.The mask version HT48C70-1is fully pin and functionally compatible with the OTP version HT48R70A-1device.
The advantages of low power consumption,I/O flexibil-ity,timer functions,oscillator options,HALT and wake-up functions,watchdog timer,buzzer driver,as well as low cost,enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control,consumer products,subsystem con-trollers,etc.
Features
·Operating voltage:
f SYS =4MHz:2.2V~5.5V f SYS =8MHz:3.3V~5.5V
·Low voltage reset function ·56bidirectional I/O lines (max.)·1interrupt input
·2′16-bit programmable timer/event counter and
overflow interrupts
·On-chip RC oscillator,external crystal and RC oscil-
lator
·32768Hz crystal oscillator for timing purposes only ·Watchdog Timer
·8192′16program memory ROM ·224′8data memory RAM
·HALT function and wake-up feature reduce power
consumption
·16-level subroutine nesting
·Up to 0.5m s instruction cycle with 8MHz system clock
at V DD =5V
·Bit manipulation instruction ·16-bit table read instruction ·63powerful instructions
·All instructions in one or two machine cycles ·48-pin SSOP,64-pin QFP
package
Block Diagram
Rev.1.602June9,2004
Rev.1.603June9,2004
HT48C70-1
*The IC substrate should be connected to VSS in the PCB layout artwork.
Rev.1.604June9,2004
Pad Description
Pad Name I/O Options Description
PA0~PA7I/O
Wake-up
Pull-high*
CMOS or Schmitt
Input
Bidirectional8-bit input/output ports
Each bit can be configured as a wake-up input by options.Software instruc-
tions determine the CMOS output or Schmitt trigger or CMOS input with or with-
out pull high resistor(by options).
PB0~PB7I/O Pull-high*Bidirectional8-bit input/output ports
Software instructions determine the CMOS output or Schmitt trigger input (pull-high depends on options).
VSS??Negative power supply,ground
INT I?External interrupt Schmitt trigger without pull high resistor Edge trigger is activated during high to low transition.
TMR0I?Schmitt trigger input for Timer/Event Counter0 TMR1I?Schmitt trigger input for Timer/Event Counter1
PC0~PC7I/O Pull-high*Bidirectional8-bit input/output ports
Software instructions determine the CMOS output or Schmitt trigger input (pull-high depends on options).
RES I?Schmitt trigger reset input,active low VDD??Positive power supply
OSC1 OSC2I
O
Crystal
or RC
or RTC
OSC1and OSC2are connected to an RC network or a crystal(by options)for
the internal system clock.In the case of RC operation,OSC2is the output
terminal for1/4system clock.
These two pins also can be optioned as an RTC oscillator(32768Hz).In this
case,the system clock comes from an internal RC oscillator whose fre-
quency has4options(3.2MHz,1.6MHz,800kHz,400kHz)
PD0~PD7I/O Pull-high*Bidirectional8-bit input/output ports
Software instructions determine the CMOS output or Schmitt trigger input (pull-high depends on options).
PE0~PE7I/O Pull-high*Bidirectional8-bit input/output ports
Software instructions determine the CMOS output or Schmitt trigger input (pull-high depends on options).
PF0~PF7I/O Pull-high*Bidirectional8-bit input/output ports
Software instructions determine the CMOS output or Schmitt trigger input (pull-high depends on options).
PG0~PG7I/O Pull-high*Bidirectional8-bit input/output ports
Software instructions determine the CMOS output or Schmitt trigger input (pull-high depends on options).
Note:*The pull-high resistors of each I/O port(PA,PB,PC,PD,PE,PF,PG)are controlled by an option.
CMOS or Schmitt trigger option of port A is controlled by an option.
Absolute Maximum Ratings
Supply Voltage...........................V SS-0.3V to V SS+6.0V Storage Temperature............................-50°C to125°C Input Voltage..............................V SS-0.3V to V DD+0.3V Operating Temperature...........................-40°C to85°C
Note:These are stress ratings only.Stresses exceeding the range specified under2Absolute Maximum Ratings2may cause substantial damage to the device.Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-ity.
Rev.1.605June9,2004
Symbol Parameter
Test Conditions
Min.Typ.Max.Unit V DD Conditions
V DD Operating Voltage ?f SYS=4MHz 2.2? 5.5V ?f SYS=8MHz 3.3? 5.5V
I DD1Operating Current(Crystal OSC)3V
No load,f SYS=4MHz
?0.6 1.5mA 5V?24mA
I DD2Operating Current(RC OSC)3V
No load,f SYS=4MHz
?0.8 1.5mA 5V? 2.54mA
I DD3Operating Current(Crystal OSC)5V No load,f SYS=8MHz?35mA
I STB1Standby Current(WDT Enabled RTC Off)3V
No load,system HALT
??5m A 5V??10m A
I STB2Standby Current(WDT Disabled RTC Off)3V
No load,system HALT
??1m A 5V??2m A
I STB3Standby Current(WDT Disabled,RTC On)3V
No load,system HALT
??5m A 5V??10m A
V IL1Input Low Voltage for I/O Ports??0?0.3V DD V V IH1Input High Voltage for I/O Ports??0.7V DD?V DD V V IL2Input Low Voltage(RES)??0?0.4V DD V V IH2Input High Voltage(RES)??0.9V DD?V DD V V LVR Low Voltage Reset?LVRenabled 2.7 3.0 3.3V
I OL I/O Port Sink Current
3V V OL=0.1V DD48?mA
5V V OL=0.1V DD1020?mA
I OH I/O Port Source Current
3V V OH=0.9V DD-2-4?mA
5V V OH=0.9V DD-5-10?mA
R PH Pull-high Resistance 3V
?
2060100k W 5V103050k W
Rev.1.606June9,2004
Symbol Parameter
Test Conditions
Min.Typ.Max.Unit V DD Conditions
f SYS1System Clock(Crystal OSC)? 2.2V~5.5V400?4000kHz ? 3.3V~5.5V400?8000kHz
f SYS2System Clock(RC OSC)? 2.2V~5.5V400?4000kHz ? 3.3V~5.5V400?8000kHz
f SYS3System Clock(Internal RC OSC)5V 3.2MHz1800?5400kHz 1.6MHz900?2700kHz 800kHz450?1350kHz 400kHz225?675kHz
f TIMER Timer I/P Frequency(TMR)? 2.2V~5.5V0?4000kHz ? 3.3V~5.5V0?8000kHz
t WDTOSC Watchdog Oscillator Period
3V?4590180m s
5V?3265130m s
t WDT1Watchdog Time-out Period(WDT OSC)3V
Without WDT prescaler
112346ms 5V81733ms
t WDT2Watchdog Time-out Period(System Clock)?Without WDT prescaler?1024?t SYS t WDT3Watchdog Time-out Period(RTC OSC)?Without WDT prescaler?7.812?ms t RES External Reset Low Pulse Width??1??m s
t SST System Start-up Timer Period?Wake-up from HALT?1024?t SYS t INT Interrupt Pulse Width??1??m s
Rev.1.607June9,2004
Functional Description
Rev.1.608June 9,2004
Execution Flow
The system clock for the microcontroller is derived from either a crystal or an RC oscillator.The system clock is internally divided into four non-overlapping clocks.One instruction cycle consists of four system clock cycles.Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de-coding and execution takes the next instruction cycle.However,the pipelining scheme causes each instruc-tion to effectively execute in a cycle.If an instruction changes the program counter,two cycles are required to complete the instruction.Program Counter -PC
The program counter (PC)controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of pro-gram memory.
After accessing a program memory word to fetch an in-struction code,the contents of the program counter are
incremented by one.The program counter then points to the memory word containing the next instruction code.When executing a jump instruction,conditional skip ex-ecution,loading register,subroutine call or return from subroutine,initial reset,internal interrupt,external inter-rupt or return from interrupts,the PC manipulates the program transfer by loading the address corresponding to each instruction.
The conditional skip is activated by instructions.Once the condition is met,the next instruction,fetched during the current instruction execution,is discarded and a dummy cycle replaces it to get the proper instruction.Otherwise proceed to the next instruction.
The lower byte of the program counter (PCL)is a read-able and writeable register (06H).Moving data into the PCL performs a short jump.The destination will be within the current program ROM page.
When a control transfer takes place,an additional dummy cycle is required.
Execution Flow
Mode
Program Counter
*12*11*10*9*8*7*6*5*4*3*2*1*0Initial Reset 0000000000000External Interrupt
0000000000100Timer/Event Counter 0Overflow 0000000001000Timer/Event Counter 1Overflow 0
00
1
1
Skip PC+2Loading PCL *12*11*10*9*8@7@6@5@4@3@2@1@0Jump,Call Branch #12#11#10#9#8#7#6#5#4#3#2#1#0Return from Subroutine
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:*12~*0:Program counter bits
S12~S0:Stack register bits #12~#0:Instruction code bits
@7~@0:PCL bits
Program Memory-ROM
The program memory is used to store the program in-structions which are to be executed.It also contains data,table,and interrupt entries,and is organized into 8192′16bits,addressed by the program counter and ta-ble pointer.
Certain locations in the program memory are reserved for special usage:
·Location000H
This area is reserved for program initialization.After chip reset,the program always begins execution at lo-cation000H.
·Location004H
This area is reserved for the external interrupt service program.If the INT interrupt pin is activated,the inter-rupt enabled and the stack is not full,the program be-gins execution at location004H.
·Location008H
This area is reserved for the Timer/Event Counter0in-terrupt service program.If a timer interrupt results from a Timer/Event Counter0overflow,and if the interrupt is enabled and the stack is not full,the program begins ex-ecution at location008H.
·Location00CH
This location is reserved for the Timer/Event Counter 1interrupt service program.If a timer interrupt results from a Timer/Event Counter1overflow,and the inter-rupt is enabled and the stack is not full,the program begins execution at location00CH.
·Table location
Any location in the program memory can be used as look-up tables.The instructions2TABRDC[m]2(the current page,one page=256words)and2TABRDL [m]2(the last page)transfer the contents of the lower-order byte to the specified data memory,and the higher-order byte to TBLH(08H).The Table Higher-order byte register(TBLH)is read only.The ta-ble pointer(TBLP)is a read/write register(07H), which indicates the table location.Before accessing the table,the location must be placed in the TBLP.The TBLH is read only and cannot be restored.If the main
routine and the ISR(Interrupt Service Routine)both employ the table read instruction,the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR.Errors can occur.In other words,using the table read instruction in the main routine and the ISR simultaneously should be avoided.However,if the table read instruction has to be applied in both the main routine and the ISR,the interrupt is supposed to be disabled prior to the table read instruction.It will not be enabled until the TBLH has been backed up.All table related instructions re-quire two cycles to complete the operation.These ar-eas may function as normal program memory depending upon the requirements.
Stack Register-STACK
This is a special part of the memory which is used to save the contents of the program counter(PC)only.The stack is organized into16levels and is neither part of the data nor part of the program space,and is neither read-able nor writeable.The activated level is indexed by the stack pointer(SP)and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal,the
Program Memory
Instruction
Table Location
*12*11*10*9*8*7*6*5*4*3*2*1*0
TABRDC[m]P12P11P10P9P8@7@6@5@4@3@2@1@0 TABRDL[m]11111@7@6@5@4@3@2@1@0
Table Location
Note:*12~*0:Table location bits P12~P8:Current program counter bits @7~@0:Table pointer bits
Rev.1.609June9,2004
contents of the program counter are pushed onto the stack.At the end of a subroutine or an interrupt routine, signaled by a return instruction(RET or RETI),the pro-gram counter is restored to its previous value from the stack.After a chip reset,the SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes place,the interrupt request flag will be recorded but the acknowledge signal will be inhibited.When the stack pointer is decremented(by RET or RETI),the interrupt will be serviced.This feature prevents stack overflow al-lowing the programmer to use the structure more easily. In a similar case,if the stack is full and a2CALL2is sub-sequently executed,stack overflow occurs and the first entry will be lost(only the most recent16return ad-dresses are stored).
Data Memory-RAM
The data memory is designed with255′8bits.The data memory is divided into two functional groups:spe-cial function registers and general purpose data mem-ory(224′8).Most are read/write,but some are read only.
The special function registers include the indirect ad-dressing registers(R0;00H,R1;02H),timer/event0 higher order byte register(TMR0H;0CH),Timer/Event Counter0lower order byte register(TMR0L;0DH) Timer/Event Counter0control register(TMR0C;0EH), Timer/Event Counter1higher order byte register (TMR1H;0FH),Timer/Event Counter1lower order byte register(TMR1L;10H),Timer/Event Counter1control register(TMR1C;11H),program counter lower-order byte register(PCL;06H),memory pointer registers (MP0;01H,MP1;03H),accumulator(ACC;05H),table pointer(TBLP;07H),table higher-order byte register (TBLH;08H),status register(STATUS;0AH),interrupt control register(INTC;0BH),Watchdog Timer option setting register(WDTS;09H),I/O registers(PA;12H, PB;14H,PC;16H,PD;18H,PE;1AH,PF;1CH,PG;1EH) and I/O control registers(PAC;13H,PBC;15H,
PCC;17H,PDC;19H,PEC;1BH,PFC;1DH,PGC;1FH). The general purpose data memory,addressed from20H to FFH,is used for data and control information under in-struction commands.
All of the data memory areas can handle arithmetic, logic,increment,decrement and rotate operations di-rectly.Except for some dedicated bits,each bit in the data memory can be set and reset by2SET[m].i2and 2CLR[m].i2.They are also indirectly accessible through memory pointer registers(MP0or MP1).
Indirect Addressing Register
Location00H and02H are indirect addressing registers that are not physically implemented.Any read/write op-eration of[00H]([02H])will access data memory pointed to by MP0(MP1).Reading location00H(02H)itself indi-rectly will return the result00H.Writing indirectly results in no operation.
The memory pointer registers(MP0and MP1)are8-bit registers.
Accumulator
The accumulator is closely related to ALU operations.It is also mapped to location05H of the data memory and can carry out immediate data operations.The data movement between two data memory locations must pass through the accumulator.
RAM Mapping
Rev.1.6010June9,2004
Arithmetic and Logic Unit-ALU
This circuit performs8-bit arithmetic and logic operations. The ALU provides the following functions:
·Arithmetic operations(ADD,ADC,SUB,SBC,DAA)·Logic operations(AND,OR,XOR,CPL)·Rotation(RL,RR,RLC,RRC)
·Increment and Decrement(INC,DEC)
·Branch decision(SZ,SNZ,SIZ,SDZ....)
The ALU not only saves the results of a data operation but also changes the status register.
Status Register-STATUS
This8-bit register(0AH)contains the zero flag(Z),carry flag(C),auxiliary carry flag(AC),overflow flag(OV), power down flag(PDF),and watchdog time-out flag (TO).It also records the status information and controls the operation sequence.
With the exception of the TO and PDF flags,bits in the status register can be altered by instructions like most other registers.Any data written into the status register will not change the TO or PDF flag.In addi-tion operations related to the status register may give different results from those intended.The TO flag can be affected only by system power-up,a WDT time-out or executing the2CLR WDT2or2HALT2in-struction.The PDF flag can be affected only by exe-cuting the2HALT2or2CLR WDT2instruction or during a system power-up.
The Z,OV,AC and C flags generally reflect the status of the latest operations.
In addition,on entering the interrupt sequence or exe-cuting the subroutine call,the status register will not be pushed onto the stack automatically.If the contents of the status are important and if the subroutine can cor-rupt the status register,precautions must be taken to save it properly.Interrupt
The device provides an external interrupt and internal timer/event counter interrupts.The Interrupt Control Register(INTC;0BH)contains the interrupt control bits to set the enable or disable and the interrupt request flags.
Once an interrupt subroutine is serviced,all the other in-terrupts will be blocked(by clearing the EMI bit).This scheme may prevent any further interrupt nesting.Other interrupt requests may occur during this interval but only the interrupt request flag is recorded.If a certain inter-rupt requires servicing within the service routine,the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting.If the stack is full,the interrupt request will not be acknowledged,even if the related in-terrupt is enabled,until the SP is decremented.If immedi-ate service is desired,the stack must be prevented from becoming full.
All these kinds of interrupts have a wake-up capability. As an interrupt is serviced,a control transfer occurs by pushing the program counter onto the stack,followed by a branch to a subroutine at specified location in the pro-gram memory.Only the program counter is pushed onto the stack.If the contents of the register or status register (STATUS)are altered by the interrupt service program which corrupts the desired control sequence,the con-tents should be saved in advance.
External interrupts are triggered by a high to low transi-tion of the INT and the related interrupt request flag(EIF; bit4of INTC)will be set.When the interrupt is enabled, the stack is not full and the external interrupt is active,a subroutine call to location04H will occur.The interrupt request flag(EIF)and EMI bits will be cleared to disable other interrupts.
The internal Timer/Event Counter0interrupt is initial-ized by setting the Timer/Event Counter0interrupt re-quest flag(T0F;bit5of INTC),caused by a timer0 overflow.When the interrupt is enabled,the stack is not full and the T0F bit is set,a subroutine call to location
Labels Bits Function
C0C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation;otherwise C is cleared.C is also affected by a rotate through carry instruction.
AC1AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction;otherwise AC is cleared.
Z2Z is set if the result of an arithmetic or logic operation is zero;otherwise Z is cleared.
OV3OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit,or vice versa;otherwise OV is cleared.
PDF4PDF is cleared by system power-up or executing the2CLR WDT2instruction.PDF is set by exe-cuting the2HALT2instruction.
TO5TO is cleared by system power-up or executing the2CLR WDT2or HALT instruction.TO is set by a WDT time-out.
?6,7Unused bit,read as202
Status Register
Rev.1.6011June9,2004
08H will occur.The related interrupt request flag(T0F) will be reset and the EMI bit cleared to disable further in-terrupts.
The internal timer/even counter1interrupt is initialized by setting the Timer/Event Counter1interrupt request flag(T1F;bit6of INTC),caused by a timer1overflow. When the interrupt is enabled,the stack is not full and the T1F is set,a subroutine call to location0CH will oc-cur.The related interrupt request flag(T1F)will be reset and the EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine,other in-terrupt acknowledge signals are held until the2RETI2in-struction is executed or the EMI bit and the related interrupt control bit are set to1(if the stack is not full).T o return from the interrupt subroutine,2RET2or2RETI2may be invoked.RETI will set the EMI bit to enable an in-terrupt service,but RET will not.
Interrupts,occurring in the interval between the rising edges of two consecutive T2pulses,will be serviced on the latter of the two T2pulses,if the corresponding inter-rupts are enabled.In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit.
No.Interrupt Source Priority Vector
a External Interrupt104H
b Timer/Event Counter0Overflow208H
c Timer/Event Counter1Overflow30CH
The Timer/Event Counter0/1interrupt request flag (T0F/T1F),external interrupt request flag(EIF),enable Timer/Event Counter0/1interrupt bit(ET0I/ET1I),en-able external interrupt bit(EEI)and enable master inter-rupt bit(EMI)constitute an interrupt control register (INTC)which is located at0BH in the data memory.EMI, EEI,ET0I and ET1I are used to control the enabling or disabling of interrupts.These bits prevent the requested interrupt from being serviced.Once the interrupt request flags(T0F,T1F,EIF)are set,they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction.
It is recommended that a program does not use the 2CALL subroutine2within the interrupt subroutine.In-terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled,the original control sequence will be dam-aged once the2CALL2operates in the interrupt subrou-tine.
Oscillator Configuration
There are3oscillator circuits in the microcontroller.
All of them are designed for system clocks,namely the external RC oscillator,the external Crystal oscillator and the internal RC oscillator,which are determined by op-tions.No matter what oscillator type is selected,the sig-nal provides the system clock.The HALT mode stops the system oscillator and ignores an external signal to conserve power.
If an RC oscillator is used,an external resistor between OSC1and VDD is required and the resistance must range from24k W to1M W.The system clock,divided by 4,is available on OSC2,which can be used to synchro-nize external logic.The RC oscillator provides the most cost effective solution.However,the frequency of oscil-lation may vary with VDD,temperatures and the chip it-self due to process variations.It is,therefore,not suitable for timing sensitive operations where an accu-rate oscillator frequency is desired.
If the Crystal oscillator is used,a crystal across OSC1 and OSC2is needed to provide the feedback and phase shift required for the oscillator.No other external compo-nents are required.In stead of a crystal,a resonator can also be connected between OSC1and OSC2to get a
Register Bit https://www.wendangku.net/doc/da14010260.html,bel Function
INTC (0BH)0EMI Controls the master(global)interrupt(1=enabled;0=disabled)
1EEI Controls the external interrupt(1=enabled;0=disabled)
2ET0I Controls the Timer/Event Counter0interrupt(1=enabled;0=disabled) 3ET1I Controls the Timer/Event Counter1interrupt(1=enabled;0=disabled) 4EIF External interrupt request flag(1=active;0=inactive)
5T0F Internal Timer/Event Counter0request flag(1=active;0=inactive)
6T1F Internal Timer/Event Counter1request flag(1=active;0=inactive)
7?Unused bit,read as202
INTC Register
System Oscillator
Rev.1.6012June9,2004
frequency reference,but two external capacitors in OSC1and OSC2are required.If the internal RC oscilla-tor is used,the OSC1and OSC2can be selected as 32768Hz crystal oscillator(RTC OSC).Also,the fre-quencies of the internal RC oscillator can be3.2MHz, 1.6MHz,800kHz and400kHz(depends on the options).
The WDT oscillator is a free running on-chip RC oscilla-tor,and no external components are required.Even if the system enters the power down mode,the system clock is stopped,but the WDT oscillator still works within a period of approximately65m s@5V.The WDT oscillator can be disabled by options to conserve power.
Watchdog Timer-WDT
The WDT clock source is implemented by a dedicated RC oscillator(WDT oscillator),RTC clock or instruction clock(system clock divided by4),determines the op-tions.This timer is designed to prevent a software mal-function or sequence from jumping to an unknown location with unpredictable results.The Watchdog Timer can be disabled by options.If the Watchdog Timer is disabled,all the executions related to the WDT result in no operation.The RTC clock is enabled only in the in-ternal RC+RTC mode.
Once the internal WDT oscillator(RC oscillator with a period of65m s@5V normally)is selected,it is first di-vided by256(8-stage)to get the nominal time-out pe-riod of17ms@5V.This time-out period may vary with temperatures,VDD and process variations.By invoking the WDT prescaler,longer time-out periods can be real-ized.Writing data to WS2,WS1,WS0(bit2,1,0of the WDTS)can give different time-out periods.If WS2, WS1,and WS0are all equal to1,the division ratio is up to1:128,and the maximum time-out period is2.1s@5V seconds.If the WDT oscillator is disabled,the WDT clock may still come from the instruction clock and oper-ates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting pur-pose.In this situation the logic can only be restarted by external logic.The high nibble and bit3of the WDTS are reserved for users defined flags,which can be used to indicate some specified status.
If the device operates in a noisy environment,using the on-chip RC oscillator(WDT OSC)or32kHz crystal oscil-lator(RTC OSC)is strongly recommended,since the HALT will stop the system clock.
WS2WS1WS0Division Ratio
0001:1
0011:2
0101:4
0111:8
1001:16
1011:32
1101:64
1111:128
WDTS Register
The WDT overflow under normal operation will initialize 2chip reset2and set the status bit2TO2.But in the HALT mode,the overflow will initialize a2warm reset2and only the PC and SP are reset to zero.To clear the contents of WDT(including the WDT prescaler),three methods are adopted;external reset(a low level to RES),software in-struction and a2HALT2instruction.The software instruc-tion include2CLR WDT2and the other set-2CLR WDT12and2CLR WDT22.Of these two types of instruc-tion,only one can be active depending on the option-2CLR WDT times selection option2.If the2CLR WDT2is selected(i.e.CLRWDT times equal one),any execution of the2CLR WDT2instruction will clear the WDT.In the case that2CLR WDT12and2CLR WDT22are chosen (i.e.CLRWDT times equal two),these two instructions must be executed to clear the WDT;otherwise,the WDT may reset the chip as a result of time-out.
Power Down Operation-HALT
The HALT mode is initialized by the2HALT2instruction and results in the following...
·The system oscillator will be turned off but the WDT oscillator remains running(if the WDT oscillator is se-lected).
·The contents of the on chip RAM and registers remain unchanged.
·WDT and WDT prescaler will be cleared and re-counted again(if the WDT clock is from the WDT os-cillator).
·All of the I/O ports maintain their original status.·The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset,an interrupt,an external falling edge sig-nal on port A or a WDT overflow.An external reset
Watchdog Timer
Rev.1.6013June9,2004
causes a device initialization and the WDT overflow per-forms a2warm reset2.After the TO and PDF flags are examined,the reason for chip reset can be determined. The PDF flag is cleared by system power-up or execut-ing the2CLR WDT2instruction and is set when execut-ing the2HALT2instruction.The TO flag is set if the WDT time-out occurs,and causes a wake-up that only resets the PC and SP;the others remain in their original status.
The port A wake-up and interrupt methods can be con-sidered as a continuation of normal execution.Each bit in port A can be independently selected to wake-up the device by options.Awakening from an I/O port stimulus, the program will resume execution of the next instruc-tion.If it awakens from an interrupt,two sequence may occur.If the related interrupt is disabled or the interrupt is enabled but the stack is full,the program will resume execution at the next instruction.If the interrupt is en-abled and the stack is not full,the regular interrupt re-sponse takes place.If an interrupt request flag is set to 212before entering the HALT mode,the wake-up func-tion of the related interrupt will be disabled.Once a wake-up event occurs,it takes1024t SYS(system clock period)to resume normal operation.In other words,a dummy period will be inserted after a wake-up.If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles.If the wake-up results in the next instruction execution,this will be executed immediately after the dummy period is finished.
To minimize power consumption,all the I/O pins should be carefully managed before entering the HALT status. The RTC oscillator still runs in the HALT mode(if the RTC oscillator is enabled).
Reset
There are three ways in which a reset can occur:·RES reset during normal operation
·RES reset during HALT
·WDT time-out reset during normal operation
The WDT time-out during HALT is different from other chip reset conditions,since it can perform a2warm re-set2that resets only the PC and SP,leaving the other cir-cuits in their original state.Some registers remain un-changed during other reset conditions.Most registers are reset to the2initial condition2when the reset condi-tions are met.By examining the PDF and TO flags,the program can distinguish between different2chip resets2. TO PDF RESET Conditions
00RES reset during power-up
u u RES reset during normal operation
01RES wake-up HALT
1u WDT time-out during normal operation
11WDT wake-up HALT
Note:2u2stands for2unchanged2
To guarantee that the system oscillator is started and stabilized,the SST(System Start-up Timer)provides an extra-delay of1024system clock pulses when the sys-tem reset(power-up,WDT time-out or reset)or the system awakes from the HALT state.
When a system reset occurs,the SST delay is added during the reset period.Any wake-up from HALT will en-able the SST delay.
An extra option load time delay is added during system reset(power-up,WDT time-out at normal mode or reset).
The functional unit chip reset status are shown below. PC000H
Interrupt Disable
Prescaler Clear
WDT
Clear.After master reset,
WDT begins counting
Timer/Event Counter
Off
Input/Output Ports Input mode
SP Points to the top of the stack
Reset Circuit
Note:2*2Make the length of the wiring,which is con-nected to the RES pin as short as possible,to
avoid noise interference.
Reset Configuration
Reset Timing Chart
Rev.1.6014June9,2004
The states of the registers is summarized in the table.
Register
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
TMR0H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C00-01---00-01---00-01---00-01---uu-u u---TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C00-01---00-01---00-01---00-01---uu-u u---Program
Counter
000H000H000H000H000H
MP0xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
MP1xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu STATUS--00xxxx--1u uuuu--uu uuuu--01uuuu--11uuuu INTC-0000000-0000000-0000000-0000000-uuu uuuu WDTS00000111000001110000011100000111uuuu uuuu
PA11111111111111111111111111111111uuuu uuuu PAC11111111111111111111111111111111uuuu uuuu
PB11111111111111111111111111111111uuuu uuuu PBC11111111111111111111111111111111uuuu uuuu
PC11111111111111111111111111111111uuuu uuuu PCC11111111111111111111111111111111uuuu uuuu
PD11111111111111111111111111111111uuuu uuuu PDC11111111111111111111111111111111uuuu uuuu
PE11111111111111111111111111111111uuuu uuuu PEC11111111111111111111111111111111uuuu uuuu
PF11111111111111111111111111111111uuuu uuuu PFC11111111111111111111111111111111uuuu uuuu
PG11111111111111111111111111111111uuuu uuuu PGC11111111111111111111111111111111uuuu uuuu Note:2*2stands for2warm reset2
2u2stands for2unchanged2
2x2stands for2unknown2
Rev.1.6015June9,2004
Timer/Event Counter
Two timer/event counters(TMR0,TMR1)are imple-mented in the microcontroller.The Timer/Event Counter 0contains an16-bit programmable count-up counter and the clock may come from an external source or from the system clock divided by4or RTC.
The Timer/Event Counter1contains an16-bit program-mable count-up counter and the clock may come from an external source or from the system clock divided by4 or RTC.
Using the internal clock sources,there are2reference time-bases for Timer/Event Counter0.The internal clock source can be selected as coming from f TID(can always be optioned)or f RTC(enabled only system oscil-lator in the Int.RC+RTC mode)by options.
Using the internal clock sources,there are2reference time-bases for Timer/Event Counter 1.The internal clock source can be selected as coming from f SYS/4 (can always be optioned)or f RTC(enable only the sys-tem oscillator in the Int.RC+RTC mode)by options. Using external clock input allows the user to count exter-nal events,measure time internals or pulse widths,or generate an accurate time base.While using the inter-nal clock allows the user to generate an accurate time base.There are3registers related to the Timer/Event Counter 0;TMR0H([0CH]),TMR0L([0DH]),TMR0C([0EH]).Writ-ing TMR0L will only put the written data to an internal lower-order byte buffer(8bits)and writing TMR0H will transfer the specified data and the contents of the lower-order byte buffer to TMR0H and TMR0L preload registers,respectively.The Timer/Event Counter1preload register is changed by each writing TMR0H operations. Reading TMR0H will latch the contents of TMR0H and TMR0L counters to the destination and the lower-order byte buffer,respectively.Reading the TMR0L will read the contents of the lower-order byte buffer.The TMR0C is the Timer/Event Counter1control register,which defines the operating mode,counting enable or disable and active edge.
There are3registers related to Timer/Event Counter1; TMR1H(0FH),TMR1L(10H),TMR1C(11H).Writing TMR1L will only put the written data to an internal lower-order byte buffer(8bits)and writing TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H and TMR1L preload registers,respectively.The Timer/Event Counter1 preload register is changed by each writing TMR1H op-erations.Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destination and the
Label(TMR0C)Bits Function ?0~2Unused bit,read as202
T0E3To define the TMR0active edge of Timer/Event Counter0 (0=active on low to high;1=active on high to low)
T0ON4To enable or disable timer0counting (0=disabled;1=enabled)
?5Unused bit,read as202
T0M0 T0M16
7
To define the operating mode
01=Event count mode(external clock)
10=Timer mode(internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C Register
Label(TMR1C)Bits Function ?0~2Unused bit,read as202
T1E3To define the TMR1active edge of Timer/Event Counter1 (0=active on low to high;1=active on high to low)
T1ON4To enable or disable timer1counting (0=disabled;1=enabled)
?5Unused bit,read as202
T1M0 T1M16
7
To define the operating mode
01=Event count mode(external clock)
10=Timer mode(internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C Register
Rev.1.6016June9,2004
Rev.1.6017June 9,2004
lower-order byte buffer,respectively.Reading the TMR1L will read the contents of the lower-order byte buffer.The TMR1C is the Timer/Event Counter 1control register,which defines the operating mode,counting enable or disable and active edge.
The T0M0,T0M1(TMR0C),T1M0,T1M1(TMR1C)bits define the operating mode.The event count mode is used to count external events,which means the clock source comes from an external (TMR0/TMR1)pin.The timer mode functions as a normal timer with the clock source coming from the instruction clock or RTC clock (Timer0/Timer1).The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0/TMR1).The counting is based on the instruction clock or RTC clock (Timer0/Timer1).In the event count or timer mode,once the Timer/Event Counter 0/1starts counting,it will count from the current contents in the Timer/Event Counter 0/1to FFFFH.Once overflow occurs,the counter is reloaded from the Timer/Event Counter 0/1preload register and generates the interrupt request flag (T0F/T1F;bit 5/6of INTC)at the same time.
In the pulse width measurement mode with the T0ON/T1ON and T0E/T1E bits equal to one,once the TMR0/TMR1has received a transient from low to high (or high to
counting until level and will remain in activated one cycle measurement can be done.Until setting the T0ON/T1ON,the cycle measurement will function again as long as it receives further transient pulse.Note that,in this operating mode,the Timer/Event Counter 0/1starts counting not according to the logic level but ac-cording to the transient edges.In the case of counter overflows,the counter 0/1is reloaded from the Timer/Event Counter 0/1preload register and issues the interrupt request just like the other two modes.To en-able the counting operation,the timer ON bit (T0ON:bit 4of TMR0C;T1ON:bit 4of TMR1C)should be set to 1.In the pulse width measurement mode,the T0ON/T1ON will be cleared automatically after the measurement cy-cle is completed.But in the other two modes the T0ON/T1ON can only be reset by instructions.The overflow of the Timer/Event Counter 0/1is one of the wake-up sources.No matter what the operation mode is,writing a 0to ET0I/ET1I can disable the correspond-ing interrupt services.
In the case of Timer/Event Counter 0/1OFF condition,writing data to the Timer/Event Counter 0/1preload register will also reload that data to the Timer/Event Counter 0/1.But if the Timer/Event Counter 0/1is turned on,data written to it will only be kept in the Timer/Event Counter 0/1preload register.The Timer/Event Counter 0/1will still operate until overflow occurs (a Timer/Event time).When is As clock this must be Timer/Event Counter 1
Input/Output Ports
There are56bidirectional input/output lines in the microcontroller,labeled from PA to PG,which are mapped to the data memory of[12H],[14H],[16H], [18H],[1AH],[1CH]and[1EH]respectively.All of these I/O ports can be used for input and output operations. For input operation,these ports are non-latching,that is, the inputs must be ready at the T2rising edge of instruction2MOV A,[m]2(m=12H,14H,16H,18H,1AH, 1CH or1EH).For output operation,all the data is latched and remains unchanged until the output latch is rewritten.
Each I/O line has its own control register(PAC,PBC, PCC,PDC,PEC,PFC,PGC)to control the input/output configuration.With this control register,CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically(i.e. on-the-fly)under software control.To function as an in-put,the corresponding latch of the control register must write212.The input source also depends on the control register.If the control register bit is212,the input will read the pad state.If the control register bit is202,the contents of the latches will move to the internal bus.The latter is possible in the2read-modify-write2instruction.For output function,CMOS is the only configuration. These control registers are mapped to locations13H, 15H,17H,19H,1BH,1DH and1FH.
After a chip reset,these input/output lines remain at high levels or floating state(depending on the pull-high op-tions).Each bit of these input/output latches can be set or cleared by2SET[m].i2and2CLR[m].i2(m=12H,14H, 16H,18H,1AH,1CH or1EH)instructions.
Some instructions first input data and then follow the output operations.For example,2SET[m].i2,2CLR [m].i2,2CPL[m]2,2CPLA[m]2read the entire port states into the CPU,execute the defined operations (bit-operation),and then write the results back to the latches or the accumulator.
Each line of port A has the capability of waking-up the device.
There is a pull-high option available for all I/O lines(port option).Once the pull-high option of an I/O line is se-lected,the I/O line have pull-high resistor.Otherwise, the pull-high resistor is absent.It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state.
Input/Output Ports
Rev.1.6018June9,2004
Low Voltage Reset-LVR
The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device.If the supply voltage of the device is within the range 0.9V~V LVR,such as changing a battery,the LVR will au-tomatically reset the device internally.
The LVR includes the following specifications:
·The low voltage(0.9V~V LVR)has to remain in their original state to exceed1ms.If the low voltage state does not exceed1ms,the LVR will ignore it and do not perform a reset function.
·The LVR uses the2OR2function with the external RES signal to perform chip reset.The relationship between V DD and V LVR is shown below. Note:V OPR is the voltage range for proper chip opera-tion at4MHz system clock.
Low Voltage Reset
Note:*1:To make sure that the system oscillator has stabilized,the SST provides an extra delay of 1024system clock pulses before entering the normal operation.
*2:Since low voltage has to be maintained in its original state and exceed1ms,therefore1ms delay enters the reset mode.
Options
The following table shows all kinds of options in the microcontroller.All of the options must be defined to ensure proper system functioning.
No.Options
1WDT clock source:WDT oscillator or f SYS/4or RTC oscillator or disable
2CLRWDT instructions:1or2instructions
3Timer/Event Counter0clock sources:f SYS/4or RTCOSC
4Timer/Event Counter1clock sources:f SYS/4or RTCOSC
5PA bit wake-up enable or disable
6PA CMOS or Schmitt input
7PA,PB,PC,PD,PE,PF,PG pull-high enable or disable(By port)
8System oscillator
Ext.RC,Ext.crystal,Int.RC+RTC
9Int.RC frequency selection3.2MHz,1.6MHz,800kHz or400kHz
10LVR enable or disable
Rev.1.6019June9,2004
Application Circuits
Note:The resistance and capacitance for reset circuit should be designed to ensure that the VDD is stable and re-mains in a valid range of the operating voltage before bringing to high.
2*2Make the length of the wiring,which is connected to the RES pin as short as possible,to avoid noise
interference.
The following table shows the C1,C2and R1value according different crystal values.(For reference only) Crystal or Resonator C1,C2R1 4MHz Crystal0pF10k W
4MHz Resonator10pF12k W
3.58MHz Crystal0pF10k W
3.58MHz Resonator25pF10k W
2MHz Crystal&Resonator25pF10k W
1MHz Crystal35pF27k W
480kHz Resonator300pF9.1k W
455kHz Resonator300pF10k W
429kHz Resonator300pF10k W
The function of the resistor R1is to ensure that the oscillator will switch off should low voltage condi-
tions occur.Such a low voltage,as mentioned here,is one which is less than the lowest value of the
MCU operating voltage.Note however that if the LVR is enabled then R1can be removed.
Rev.1.6020June9,2004