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MAX1717BEEG+T中文资料

General Description

The MAX1717 step-down controller is intended for core CPU DC-DC converters in notebook computers. It fea-tures a dynamically adjustable output, ultra-fast tran-sient response, high DC accuracy, and high efficiency needed for leading-edge CPU core power supplies.Maxim’s proprietary Quick-PWM? quick-response,constant-on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency.The output voltage can be dynamically adjusted through the 5-bit digital-to-analog converter (DAC)inputs over a 0.925V to 2V range. A unique feature of the MAX1717 is an internal multiplexer (mux) that accepts two 5-bit DAC settings with only five digital input pins. Output voltage transitions are accomplished with a proprietary precision slew-rate control ?that mini-mizes surge currents to and from the battery while guaranteeing “just-in-time” arrival at the new DAC setting.High DC precision is enhanced by a two-wire remote-sensing scheme that compensates for voltage drops in the ground bus and output voltage rail. Alternatively,the remote-sensing inputs can be used together with the MAX1717’s high DC accuracy to implement a volt-age-positioned circuit that modifies the load-transient response to reduce output capacitor requirements and full-load power dissipation.

Single-stage buck conversion allows these devices to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the +5V system supply instead of the battery) at a higher switching frequency allows the mini-mum possible physical size.

The MAX1717 is available in a 24-pin QSOP package.

Applications

Notebook Computers with SpeedStep? or Other Dynamically Adjustable Processors

2-Cell to 4-Cell Li+ Battery to CPU Core Supply Converters

5V to CPU Core Supply Converters

Features

?Quick-PWM Architecture

?±1% V OUT Accuracy Over Line and Load ?5-Bit On-Board DAC with Input Mux

?Precision-Adjustable V OUT Slew Control ?0.925V to 2V Output Adjust Range

?Supports Voltage-Positioned Applications ?2V to 28V Battery Input Range

?Requires a Separate +5V Bias Supply

?200/300/550/1000kHz Switching Frequency ?Over/Undervoltage Protection

?Drives Large Synchronous-Rectifier FETs ?700μA (typ) I CC Supply Current

?2μA (typ) Shutdown Supply Current ?2V ±1% Reference Output

?VGATE Transition-Complete Indicator ?

Small 24-Pin QSOP Package

MAX1717

________________________________________________________________Maxim Integrated Products 1

Ordering Information

Pin Configuration appears at end of data sheet.

?Patent pending.

Quick-PWM is a trademark of Maxim Integrated Products.SpeedStep is a trademark of Intel Corp.

Minimal Operating Circuit

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at https://www.wendangku.net/doc/d115024306.html,.

+ Denotes lead-free package.

M A X 1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V+ = +15V, V = V = SKP/SDN = +5V, V = 1.6V, T = 0°C to +85°C , unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

V+ to GND..............................................................-0.3V to +30V V CC , V DD to GND.....................................................-0.3V to +6V D0–D4, A/B,VGATE, to GND ..................................-0.3V to +6V SKP/SDN to GND ...................................................-0.3V to +16V ILIM, FB, FBS, CC, REF, GNDS,TON,

TIME to GND..........................................-0.3V to (V CC + 0.3V)DL to GND..................................................-0.3V to (V DD + 0.3V)BST to GND............................................................-0.3V to +36V DH to LX.....................................................-0.3V to (BST + 0.3V)

LX to BST..................................................................-6V to +0.3V REF Short Circuit to GND...........................................Continuous Continuous Power Dissipation

24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW Operating Temperature Range ..........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature.........................................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°C

MAX1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = +15V, V CC = V DD = SKP/SDN = +5V, V OUT = 1.6V, T A = 0°C to +85°C , unless otherwise noted.)

M A X 1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = +15V, V CC = V DD = SKP/SDN = +5V, V OUT = 1.6V, T A = 0°C to +85°C , unless otherwise noted.)

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V+ = +15V, V CC = V DD = SKP/SDN = +5V, V OUT = 1.6V, T A = -40°C to +85°C , unless otherwise noted.) (Note 3)

MAX1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

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ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = +15V, V

= V = SKP/SDN = +5V, V =1.6V, T = -40°C to +85°C , unless otherwise noted.) (Note 3)

Note 1:Output voltage accuracy specifications apply to DAC voltages from 0.925V to 2V. Includes load-regulation error.

Note 2:On-Time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0, BST forced to 5V, and a 500pF

capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to MOSFET switching speeds.

Note 3:Specifications to -40°C are guaranteed by design and not production tested.

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Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs 6_______________________________________________________________________________________

Typical Operating Characteristics

(Circuit of Figure 1, components of Table 1, V+ = +12V, V DD = V CC = SKP/SDN = +5V, V OUT = 1.6V, T A = +25°C, unless otherwise noted.)

500.01

0.1

EFFICIENCY vs. LOAD CURRENT 300kHz STANDARD APPLICATION,

CIRCUIT 1

100

9080

LOAD CURRENT (A)

E F F I C I E N C Y (%)

0.01

0.1

EFFICIENCY vs. LOAD CURRENT 300kHz VOLTAGE POSITIONED, CIRCUIT 2

100

9080

LOAD CURRENT (A)

E F F I C I E N C Y (%)

500.01

0.1

EFFECTIVE EFFICIENCY vs. LOAD CURRENT 300kHz VOLTAGE POSITIONED, CIRCUIT 2

100

NONPOSITIONED LOAD CURRENT (A)

E F F E C T I V E E F F I C I E N C Y (%)

500.01

0.1

EFFICIENCY vs. LOAD CURRENT 550kHz VOLTAGE POSITIONED, CIRCUIT 3

100

9080LOAD CURRENT (A)E F F I C I E N C Y (%)

500.01

0.1

EFFECTIVE EFFICIENCY vs. LOAD CURRENT 550kHz VOLTAGE POSITIONED, CIRCUIT 3

100

NONPOSITIONED LOAD CURRENT (A)

E F F E C T I V E E F F I C I E N C Y (%

)

500.01

0.1

EFFICIENCY vs. LOAD CURRENT 1000kHz, +5V, CIRCUIT 4

100

9080LOAD CURRENT (A)

E F F I C I E N C Y (%

)

500.01

0.1

EFFECTIVE EFFICIENCY vs. LOAD CURRENT

1000kHz, +5V, CIRCUIT 4

100

6090

80NONPOSITIONED LOAD CURRENT (A)

E F F E C T I V E E F F I C I E N C Y (%)

0.01

0.1

EFFICIENCY vs. LOAD CURRENT 1000kHz VOLTAGE POSITIONED,

CIRCUIT 5

100

609080LOAD CURRENT (A)

E F F I C I E N C Y (%)

0.01

0.1

EFFECTIVE EFFICIENCY vs. LOAD CURRENT

1000kHz VOLTAGE POSITIONED,

CIRCUIT 5

100

NONPOSITIONED LOAD CURRENT (A)

E F F E C T I V E E F F I C I E N C Y (%)

MAX1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

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400

300200

100

FREQUENCY vs. LOAD CURRENT

LOAD CURRENT (A)

F R E Q U E N C Y (k H z )

12501000750

500

2500

FREQUENCY vs. LOAD CURRENT

LOAD CURRENT (A)

F R E Q U E N C Y (k H z )

400

350300

250

200

FREQUENCY vs. INPUT VOLTAGE

INPUT VOLTAGE (V)

F R E Q U E N C Y (k H z )

1200

1000800

600

400

FREQUENCY vs. INPUT VOLTAGE

INPUT VOLTAGE (V)

F R E Q U E N C Y (k H z )

300

310

330

320

340

350

-40

-20

8085

FREQUENCY vs. TEMPERATURE

TEMPERATURE (°C)

F R E Q U E N C Y (k H z )

010

20152530-40

-20

80OUTPUT CURRENT AT CURRENT LIMIT

vs. TEMPERATURE

TEMPERATURE (°C)

C U R R E N T (A )

01.00.52.01.5

2.5

3.00

105152025

CONTINUOUS-TO-DISCONTINUOUS INDUCTOR CURRENT POINT

INPUT VOLTAGE (V)

L O A D C U R R E N T (A )

151052025305

13117

151719212325INDUCTOR CURRENT PEAKS AND VALLEYS vs. INPUT VOLTAGE

INPUT VOLTAGE (V)

I N D U C T O R C U R R E N T (A )

1000800600

400

20005

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

INPUT VOLTAGE (V)

S U P P L Y C U R R E N T (μA )

Typical Operating Characteristics (continued)

(Circuit of Figure 1, components of Table 1, V+ = +12V, V DD = V CC = SKP/SDN = +5V, V OUT = 1.6V, T A = +25°C, unless otherwise noted.)

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Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs 8_______________________________________________________________________________________

1000800600

400

200

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

INPUT VOLTAGE (V)

S U P P L Y C U R R E N T (μA )

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

INPUT VOLTAGE (V)

S U P P L Y C U R R E N T (m A )

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

INPUT VOLTAGE (V)

S U P P L Y C U R R E N T (m A )

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

INPUT VOLTAGE (V)

S U P P L Y C U R R E N T (m A )

10μs/div

LOAD-TRANSIENT RESPONSE

A = V OUT , 50mV/div, AC-COUPLED

B = INDUCTOR CURRENT, 10A/div

300kHz STANDARD APPLICATION, CIRCUIT 1,PWM MODE

10μs/div

LOAD-TRANSIENT RESPONSE

A = V OUT , 50mV/div, AC-COUPLED

B = INDUCTOR CURRENT, 10A/div

300kHz VOLTAGE POSITIONED,CIRCUIT 2, PWM MODE

5μs/div

LOAD-TRANSIENT RESPONSE

A = V OUT , 50mV/div, AC-COUPLED

B = INDUCTOR CURRENT, 10A/div

550kHz VOLTAGE POSITIONED, CIRCUIT 3,PWM MODE

4μs/div

LOAD-TRANSIENT RESPONSE

A = V OUT , 50mV/div, AC-COUPLED

B = INDUCTOR CURRENT, 10A/div

1000kHz +5V, CIRCUIT 4, PWM MODE

4μs/div

LOAD-TRANSIENT RESPONSE

A = V OUT , 50mV/div, AC-COUPLED

B = INDUCTOR CURRENT, 10A/div

1000kHz VOLTAGE POSITIONED, CIRCUIT 5,PWM MODE

Typical Operating Characteristics (continued)

(Circuit of Figure 1, components of Table 1, V+ = +12V, V DD = V CC = SKP/SDN = +5V, V OUT = 1.6V, T A = +25°C, unless otherwise noted.)

MAX1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

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B C

100μs/div

STARTUP WAVEFORM

A = V OUT , 1V/div

B = INDUCTOR CURRENT, 10A/div

C = SKP/SDN, 5V/div

300kHz VOLTAGE POSITIONED,CIRCUIT 2, PWM MODE,NO LOAD B

100μs/div

STARTUP WAVEFORM

A = V OUT , 1V/div

B = INDUCTOR CURRENT, 10A/div

C = SKP/SDN, 5V/div

300kHz VOLTAGE POSITIONED,CIRCUIT 2, I OUT =12A B

C D

50μs/div

DYNAMIC OUTPUT VOLTAGE TRANSITION

M A X 1717 t o c 30

300kHz STANDARD APPLICATION, CIRCUIT 1,PWM MODE, V OUT = 1.35V TO 1.6V, I OUT = 0.3A, R TIME = 120k Ω

A = V OUT , 200mV/div, AC-COUPLED

B = INDUCTOR CURRENT, 10A/div

C = VGATE, 5V/div

D = A/B, 5V/div

B C D

50μs/div

DYNAMIC OUTPUT VOLTAGE TRANSITION

M A X 1717 t o c 31

300kHz STANDARD APPLICATION, CIRCUIT 1,PWM MODE, V OUT = 1.35V TO 1.6V,I OUT = 12A, R TIME = 120k ΩA = V OUT , 200mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div C = VGATE, 5V/div D = A/B, 5V/div

C D

20μs/div

DYNAMIC OUTPUT VOLTAGE TRANSITION

M A X 1717 t o c 32

A = V OUT , 200mV/div, AC-COUPLED

B = INDUCTOR CURRENT, 10A/div

C = VGATE, 5V/div

D = A/B, 5V/div

1000kHz +5V, CIRCUIT 4,

PWM MODE, V OUT = 1.35V TO 1.6V,I OUT = 0.3A, R TIME = 51k Ω

40μs/div

OUTPUT OVERLOAD WAVEFORM

A = V OUT , 500mV/div

B = INDUCTOR CURRENT, 10A/div

300kHz VOLTAGE POSITIONED, CIRCUIT 2,

PWM MODE

Typical Operating Characteristics (continued)

(Circuit of Figure 1, components of Table 1, V+ = +12V, V DD = V CC = SKP/SDN = +5V, V OUT = 1.6V, T A = +25°C, unless otherwise noted.)

M A X 1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

Pin Description

Typical Operating Characteristics (continued)

(Circuit of Figure 1, components of Table 1, V+ = +12V, V DD = V CC = SKP/SDN = +5V, V OUT = 1.6V, T A = +25°C, unless otherwise noted.)

B C

100μs/div

SHUTDOWN WAVEFORM

A M A X 1717 t o c 34

300kHz VOLTAGE POSITIONED, CIRCUIT 2,PWM MODE, NO LOAD

A = V OUT , 1V/div

B = INDUCTOR CURRENT, 10A/div B

100μs/div

SHUTDOWN WAVEFORM

M A X 1717 t o c 35

300kHz VOLTAGE POSITIONED, CIRCUIT 2,PWM MODE, I OUT = 12A A = V OUT , 1V/div

B = INDUCTOR CURRENT, 10A/div

C = SKP/SDN, 5V/div

MAX1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

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Pin Description (continued)

M A X 1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs 12______________________________________________________________________________________

MAX1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

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Table 1. Component Selection for Standard Applications

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Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs 14

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Detailed Description

+5V Bias Supply (V CC and V DD )

The MAX1717 requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook’s 95% efficient +5V system supply.Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the +5V supply can be generated with an external linear regulator.

The +5V bias supply must provide V CC (PWM con-troller) and V DD (gate-drive power), so the maximum current drawn is:

I BIAS = I CC + f (Q G1+ Q G2) = 10mA to 40mA (typ)where I CC is 700μA (typ), f is the switching frequency,and Q G1and Q G2are the MOSFET data sheet total gate-charge specification limits at V GS = 5V.

V+ and V DD can be tied together if the input power source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SKP/SDN going from low to high or open) must be delayed until the battery voltage is pre-sent to ensure startup.

Free-Running, Constant On-Time PWM

Controller with Input Feed-Forward

The Quick-PWM control architecture is a pseudofixed-frequency, constant-on-time current-mode type with volt-age feed-forward (Figure 2). This architecture relies on the output filter capacitor’s ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input volt-age and directly proportional to output voltage. Another one-shot sets a minimum off-time (400ns typ). The on-time one-shot is triggered if the error comparator is low,

the low-side switch current is below the current-limit threshold, and the minimum off-time one-shot has timed out.

On-Time One-Shot (TON)

The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+ input, and proportional to the output voltage. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a con-stant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-cur-rent operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple.

On-Time = K (V OUT + 0.075V) / V IN

where K is set by the TON pin-strap connection and 0.075V is an approximation to accommodate the expect-ed drop across the low-side MOSFET switch (Table 3).The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics (±10% at 200kHz and 300kHz, ±12% at 550kHz and 1000kHz).On-times at operating points far removed from the condi-tions specified in the Electrical Characteristics can vary over a wide range. For example, the 1000kHz setting will typically run about 10% slower with inputs much greater than +5V due to the very short on-times required.

On-times translate only roughly to switching frequencies.The on-times guaranteed in the Electrical Character-istics are influenced by switching delays in the external high-side MOSFET. Resistive losses, including the inductor, both MOSFETs, output capacitor ESR, and PC board copper losses in the output and ground tend to raise the switching frequency at higher output currents.

MAX1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

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Figure 2. Functional Diagram

M A X 1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

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The dead-time effect increases the effective on-time,reducing the switching frequency. It occurs only in PWM mode (SKP/SDN = open) and dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time.

For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is:

f = (V OUT + V DROP1) / t ON (V IN + V DROP1 - V DROP2)where V DROP1is the sum of the parasitic voltage drops in the inductor discharge path, includin

g synchronous rectifier, inductor, and PC board resistances; V DROP2is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PC board resistances; t ON is the on-time calculated by the MAX1717.

Integrator Amplifiers

Three integrator amplifiers provide a fine adjustment to the output regulation point. One amplifier integrates the difference between G NDS and G ND, a second inte-grates the difference between FBS and FB. The third amplifier integrates the difference between REF and the DAC output. These three transconductance amplifiers’outputs are directly summed inside the chip, so the integration time constant can be set easily with one capacitor. The g m of each amplifier is 160μS (typ).

The integrator block has the ability to lower the output voltage by 2% and raise it by 6%. For each amplifier, the differential input voltage range is at least ±70mV total,including DC offset and AC ripple. The integrator corrects for approximately 90% of the total error, due to finite gain.The FBS amplifier corrects for DC voltage drops in PC board traces and connectors in the output bus path between the DC-DC converter and the load. The GNDS amplifier performs a similar DC correction task for the output ground bus. The third integrator amplifier cor-rects the small offset of the error amplifier and provides an averaging function that forces V OUT to be regulated at the average value of the output ripple waveform.

Integrators have both beneficial and detrimental char-acteristics. Although they correct for drops due to DC bus resistance and tighten the DC output voltage toler-ance limits by averaging the peak-to-peak output ripple,they can interfere with achieving the fastest possible

load-transient response. The fastest transient response is achieved when all three integrators are disabled.This can work very well if the MAX1717 circuit is placed very close to the CPU.

All three integrators can be disabled by connecting FBS to V CC . When the integrators are disabled, CC can be left unconnected, which eliminates a component,but leaves GNDS connected to any convenient ground.When the inductor is in continuous conduction, the output voltage will have a DC regulation higher than the trip level by 50% of the ripple. In discontinuous conduction (SKP/SDN open, light-loaded), the output voltage will have a DC regulation higher than the trip level by approximately 1.5% due to slope compensation.There is often a connector, or at least many milliohms of PC board trace resistance, between the DC-DC con-verter and the CPU. In these cases, the best strategy is to place most of the bulk bypass capacitors close to the CPU, with just one capacitor on the other side of the connector near the MAX1717 to control ripple if the CPU card is unplugged. In this situation, the remote-sense lines (GNDS and FBS) and integrators provide a real benefit.

When operating the MAX1717 in a voltage-positioned circuit (Figure 3), G NDS can be offset with a resistor divider from REF to GND, which causes the GNDS inte-grator to increase the output voltage by 90% of the applied offset (27mV typ). A low-value (5m Ωtyp) voltage-positioning resistor is added in series between the external inductor and the output capacitor. FBS is con-nected to FB directly at the junction of the external inductor and the voltage-positioning resistor. The net effect of these two changes is an output voltage that is slightly higher than the programmed DAC voltage at light loads, and slightly less than the DAC voltage at full-load current. For further information on voltage-posi-tioning,see the Applications section.

Automatic Pulse-Skipping Switchover

In skip mode (SKP/SDN high), an inherent automatic switchover to PFM takes place at light loads (Figure 4).This switchover is effected by a comparator that trun-cates the low-side switch on-time at the inductor current’s zero crossing. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between con-tinuous and discontinuous inductor-current operation (see the Continuous-to-Discontinuous Inductor Current Point graph in the Typical Operating Characteristics ).

MAX1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

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For a battery range of 7V to 24V, this threshold is rela-tively constant, with only a minor dependence on bat-tery voltage:where K is the on-time scale factor (Table 3). The load-current level at which PFM/PWM crossover occurs,

I LOAD(SKIP), is equal to 1/2 the peak-to-peak ripple cur-rent, which is a function of the inductor value (Figure 4).For example, in the standard application circuit this becomes:

The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used.

The switching waveforms may appear noisy and asyn-chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-tran-

sient response (especially at low input voltage levels).

Figure 3. Voltage-Positioned Circuit

M A X 1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs 18

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Forced-PWM Mode (SKP/SDN Open)

The low-noise forced-PWM mode (SKP/SDN open) dis-ables the zero-crossing comparator that controls the

low-side switch on-time. This causes the low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop strives to maintain a duty ratio of V OUT /V BATT . The benefit of forced-PWM mode is to keep the switching frequency fairly constant, but it comes at a cost: the no-load battery current can be 10mA to 40mA, depending on the external MOSFETs and switching frequency.

Forced-PWM mode is most useful for reducing audio-frequency noise and improving the cross-regulation of multiple-output applications that use a flyback trans-former or coupled inductor.

Current-Limit Circuit

The current-limit circuit employs a unique “valley” current-sensing algorithm that uses the on-resistance of the low-side MOSFET as a current-sensing element. If the current-sense signal is above the current-limit thresh-old, the PWM is not allowed to initiate a new cycle (Figure 5). The actual peak current is greater than the current-limit threshold by an amount equal to the induc-tor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a func-tion of the MOSFET on-resistance, inductor value, and battery voltage. The reward for this uncertainty is robust, lossless overcurrent sensing. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. There is also a negative current limit that prevents exces-sive reverse inductor currents when V OUT is sinking cur-rent. The negative current-limit threshold is set to approxi-mately 120% of the positive current limit, and therefore tracks the positive current limit when ILIM is adjusted.The current-limit threshold is adjusted with an external resistor-divider at ILIM. The current-limit threshold adjustment range is from 50mV to 300mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM. The threshold defaults to 100mV when ILIM is connected to V CC . The logic threshold for switchover to the 100mV default value is approximately V CC - 1V.

The adjustable current limit accommodates MOSFETs with a wide range of on-resistance characteristics (see the Design Procedure section).

Carefully observe the PC board layout guidelines to ensure that noise and DC errors don’t corrupt the cur-rent-sense signals seen by LX and G ND. Place the IC close to the low-side MOSFET with short, direct traces,making a Kelvin sense connection to the source and drain terminals.

MOSFET Gate Drivers (DH, DL)

The DH and DL drivers are optimized for driving mod-erate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in the notebook CPU environment, where a large V BATT - V OUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the high-side FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate for the adaptive dead-time cir-cuit to work properly. Otherwise, the sense circuitry in the MAX1717 will interpret the MOSFET gate as “off” while there is actually still charge left on the gate. Use very

Figure 4. Pulse-Skipping/Discontinuous Crossover Point Figure 5. “Valley” Current-Limit Threshold Point

MAX1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs

short, wide traces measuring 10 to 20 squares (50 to 100mils wide if the MOSFET is 1 inch from the MAX1717).The dead time at the other edge (DH turning off) is determined by a fixed 35ns (typ) internal delay.

The internal pull-down transistor that drives DL low is robust, with a 0.5Ωtypical on-resistance. This helps prevent DL from being pulled up during the fast rise-time of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier MOSFET. However, for high-current applications,you might still encounter some combinations of high-and low-side FETs that will cause excessive gate-drain coupling, which can lead to efficiency-killing, EMI-producing shoot-through currents. This is often remedied by adding a resistor in series with BST, which increases the turn-on time of the high-side FET without degrading the turn-off time (Figure 6).

POR

Power-on reset (POR) occurs when V CC rises above approximately 2V, resetting the fault latch and preparing the PWM for operation. V CC undervoltage lockout (UVLO) circuitry inhibits switching, forces VG ATE low,and forces the DL gate driver high (to enforce output overvoltage protection).When V CC rises above 4.2V, the DAC inputs are sampled and the output voltage begins to slew to the DAC setting.

For automatic startup, the battery voltage should be present before V CC . If the MAX1717 attempts to bring the output into regulation without the battery voltage present, the fault latch will trip. The SKP/SDN pin can be toggled to reset the fault latch.

Shutdown

When SKP/SDN goes low, the MAX1717 goes into low-power shutdown mode. VG ATE goes low immediately.The output voltage ramps down to 0 in 25mV steps at the clock rate set by R TIME . When the DAC reaches the 0V setting, DL goes high, DH goes low, the reference is turned off, and the supply current drops to about 2μA.When SKP/SDN goes high or floats, the reference pow-ers up, and after the reference UVLO is passed, the DAC target is evaluated and switching begins. The slew-rate controller ramps up from zero in 25mV steps to the currently selected code value (based on A/B ).There is no traditional soft-start (variable current limit)circuitry, so full output current is available immediately.VGATE goes high after the slew-rate controller has ter-minated and the output voltage is in regulation. As soon as VGATE goes high, full power is available.

UVLO

If the V CC voltage drops low enough to trip the UVLO comparator, it is assumed that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, DL is forced high in this mode.This will force the output to GND, but it will not use the slew-rate controller. This results in large negative inductor current and possibly small negative output voltages. If V CC is likely to drop in this fashion, the output can be clamped with a Schottky diode to G ND to reduce the negative excursion.

DAC Inputs D0–D4

The digital-to-analog converter (DAC) programs the output voltage. It typically receives a preset digital code from the CPU pins, which are either hard-wired to G ND or left open-circuit. They can also be driven by digital logic, general-purpose I/O, or an external mux.Do not leave D0–D4 floating—use 1M Ωor less pull-ups if the inputs may float. D0–D4 can be changed while the SMPS is active, initiating a transition to a new output voltage level. If this mode of DAC control is used, connect A/B high. Change D0–D4 together, avoiding greater than 1μs skew between bits. Otherwise, incorrect DAC readings may cause a partial transition to the wrong voltage level, followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages (Table 4) are compatible with Intel’s mobile Pentium ?III specification.

Pentium is a registered trademark of Intel Corp.

M A X 1717

Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs 20______________________________________________________________________________________

A/B Internal Mux

The MAX1717 contains an internal mux that can be used to select one of two programmed DAC codes and output voltages. The internal mux is controlled with the A/B pin,which selects between the A mode and the B mode. In the A mode, the voltage levels on D0–D4 select the out-put voltage according to Table 4. Do not leave D0–D4floating; there are no internal pull-up resistors.

The B mode is programmed by external resistors in series with D0–D4, using a unique scheme that allows two sets of data bits using only one set of pins (Figure 7). When A/B goes low (or during power-up with A/B low), D0–D4 are tested to see if there is a large resis-tance in series with the pin. If the voltage level on the pin is a logic low, an internal switch connects the pin to an internal 40k Ωpull-up for about 4μs to see if the pin voltage can be forced high (Figure 8). If the pin voltage cannot be pulled to a logic high, the pin is considered low impedance and its B-mode logic state is low. If the pin can be pulled to a logic high, the impedance is considered high and so is the B-mode logic state.Similarly, if the voltage level on the pin is a logic high,an internal switch connects the pin to an internal 8k Ωpull-down to see if the pin voltage can be forced low. If so, the pin is high-impedance and its B-mode logic state is high. Otherwise, its logic state is low.

A high pin impedance (and logic high) is 100k Ωor greater, and a low impedance (and logic low) is 1k Ωor less. The Electrical Characteristics guaranteed levels for these impedances are 95k Ωand 1.05k Ωto allow the use of standard 100k Ωand 1k Ωresistors with 5% tolerance.If the output voltage codes are fixed at PC board design time, program both codes with a simple combi-nation of pin-strap connections and series resistors (Figure 7). If the output voltage codes are chosen dur-ing PC board assembly, both codes can be indepen-dently programmed with resistors (Figure 9). This matrix of 10 resistor-footprints can be programmed to all possible A-mode and B-mode code combinations with only five resistors.

Often, one or more output-voltage codes are provided directly by the CPU’s VID pins. If the CPU actively dri-ves these pins, connect A/B high (A mode) and let the CPU determine the output voltages. If the B mode is needed for startup or other reasons, insert resistors in series with D0–D4 to program the B-mode voltage. Be sure that the VID pins are actively driven at all times.If the CPU’s VID pins float, the open-circuit pins can present a problem for the MAX1717’s internal mux. The

processor’s VID pins can be used for the A-mode set-ting, together with suitable pull-up resistors. However,the B-mode VID code is set with resistors in series with D0–D4, and in order for the B-mode to work, any pins intended to be B-mode logic low must appear to be low impedance, at least for the 4μs sampling interval.

Note:In the no-CPU state, DH and DL are held low and the slew-rate controller is set for 0.9V.