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XC3064A中文资料

User I/Os Horizontal Configurable Device CLBs Array Max Flip-Flops

Longlines

Data Bits

XC3020A 648 x 8642561614,779XC3030A 10010 x 10803602022,176XC3042A 14412 x 12964802430,784XC3064A 22416 x 141206883246,064XC3090A

320

16 x 20

144

928

64,160

Features ?Enhanced, high performance FPGA family with five

device types

–Improved redesign of the basic XC3000 LCA Family

–Logic densities from 1,000 to 6,000 gates –Up to 144 user-definable I/Os

?Superset of the industry-leading XC3000 family

–Identical to the basic XC3000 in structure, pin out,design methodology, and software tools

–100% compatible with all XC3000, XC3000L,and XC3100 bitstreams

–Improved routing and additional features

?Additional programmable interconnection points

(PIPs)

–Improved access to longlines and CLB clock enable inputs

–Most efficient XC3000-class solution to bus-ori-ented designs

? Advanced 0.8 μ CMOS static memory technology

–Low quiescent and active power consumption

?Performance specified by logic delays, faster than

corresponding XC3000 versions

?XC3000A-specific features

–4 mA output sink and source current

–Error checking of the configuration bitstream

–Soft startup starts all outputs in slew-limited mode upon power-up

–Easy migration to the XC3400 series of HardWire mask programmed devices for high-volume production.

Description

The XC3000A family offers the following enhancements over the popular XC3000 family:

The XC3000A family has additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines.The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing.

During configuration, the XC3000A devices check the bitstream format for stop bits in the appropriate positions.Any error terminates the configuration and pulls INIT Low.When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited . This feature, called Soft Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the XC3000family, determined by the individual configuration option.The XC3000A family is a superset of the XC3000 family.Any bitstream used to configure an XC3000 or XC3100device configures an XC3000A device exactly the same way.

XC3000A

Logic Cell Array Family

Product Specifications

XC3000A Logic Cell Array Family

Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision.

Absolute Maximum Ratings

Symbol Description Units

V CC Supply voltage relative to GND–0.5 to +7.0V

V IN Input voltage with respect to GND–0.5 to V CC +0.5V

V TS Voltage applied to 3-state output–0.5 to V CC +0.5V

T STG Storage temperature (ambient)–65 to +150°C

T SOL Maximum soldering temperature (10 s @ 1/16 in.)+260°C Junction temperature plastic+125°C T J

Junction temperature ceramic+150°C Note:Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum

Ratings conditions for extended periods of time may affect device reliability.

Operating Conditions

Symbol Description Min Max Units

V CC Supply voltage relative to GND Commercial 0°C to +85°C junction 4.75 5.25V Supply voltage relative to GND Industrial -40°C to +100°C junction 4.5 5.5V V IHT High-level input voltage — TTL configuration 2.0V CC V

V ILT Low-level input voltage — TTL configuration00.8V

V IHC High-level input voltage — CMOS configuration70%100%V CC

V ILC Low-level input voltage — CMOS configuration020%V CC

T IN Input signal transition time250ns At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.

Symbol Description

Min Max

Units V OH High-level output voltage (@ I OH = –4.0 mA, V CC min) 3.86

V OL Low-level output voltage (@ I OL = 4.0 mA, V CC min)0.40

V V OH High-level output voltage (@ I OH = –4.0 mA, V CC min )

3.76

V OL Low-level output voltage (@ I OL = 4.0 mA, V CC min )0.40

V V CCPD Power-down supply voltage (PWRDWN must be Low) 2.30

V I CCPD

Power-down supply current (V CC(MAX) @ T MAX )50μA

I CCO

Quiescent LCA supply current in addition to I CCPD *

Chip thresholds programmed as CMOS levels

500μA Chip thresholds programmed as TTL levels

10mA I IL Input Leakage Current

–10+10

μA

C IN

Input capacitance, all packages except PGA175

(sample tested)

All Pins except XTL1 and XTL210pF XTL1 and XTL215pF

Input capacitance, PGA 175

(sample tested)

All Pins except XTL1 and XTL215pF XTL1 and XTL2

20pF I RIN Pad pull-up (when selected) @ V IN = 0 V (sample tested)0.020.17mA I RLL

Horizontal Longline pull-up (when selected) @ logic Low

3.4

*With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the

LCA device configured with a MakeBits tie option.

DC Characteristics Over Operating Conditions

Industrial

Commercial

XC3000A Logic Cell Array Family

Speed Grade

-7-6Description

Symbol

Max

Units

Global and Alternate Clock Distribution*

Either:Normal IOB input pad through clock buffer

to any CLB or IOB clock input

T PID 7.57.0ns Or:Fast (CMOS only) input pad through clock

buffer to any CLB or IOB clock input T PIDC 6.0

5.7

TBUF driving a Horizontal Longline (L.L.)*I to L.L. while T is Low (buffer active)

T IO 4.5 4.0ns T ↓ to L.L. active and valid with single pull-up resistor T ON 9.08.0ns T ↓ to L.L. active and valid with pair of pull-up resistors T ON 11.010.0ns T ↑ to L.L. High with single pull-up resistor T PUS 16.014.0ns T ↑ to L.L. High with pair of pull-up resistors T PUF 10.08.0ns

BIDI

Bidirectional buffer delay

T BIDI

1.7 1.5ns

CLB Switching Characteristic Guidelines

Buffer (Internal) Switching Characteristic Guidelines

Timing is based on the XC3042A, for other devices see XACT timing calculator.

CLB Output (X, Y) (Combinatorial)

CLB Input (A,B,C,D,E)

CLB Clock

CLB Input (Direct In)

CLB Input (Enable Clock)

CLB Output (Flip-Flop)

CLB Input (Reset Direct)

CLB Output (Flip-Flop)

X5424

CLB Switching Characteristic Guidelines (continued)

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.

Speed Grade-7-6

Description Symbol Min Max Min Max Units Combinatorial Delay

Logic Variables A, B, C, D, E, to outputs X or Y

FG Mode1T ILO 5.1 4.1ns

F and FGM Mode 5.6 4.6ns Sequential delay

Clock k to outputs X or Y8T CKO 4.5 4.0ns Clock k to outputs X or Y when Q is returned

through function generators F or G to drive X or Y

FG Mode T QLO9.58.0ns

F and FGM Mode10.08.5ns Set-up time before clock K

Logic Variables A, B, C, D, E

FG Mode2T ICK 4.5 3.5ns

F and FGM Mode 5.0 4.0ns

Data In DI4T DICK 4.0 3.0ns Enable Clock EC6T ECCK 4.5 4.0ns Hold Time after clock K

Logic Variables A, B, C, D, E3T CKI00ns Data In DI5T CKDI 1.0 1.0ns Enable Clock EC7T CKEC 2.0 2.0ns Clock

Clock High time11T CH 4.0 3.5ns Clock Low time12T CL 4.0 3.5ns Max. flip-flop toggle rate F CLK113.0135.0MHz Reset Direct (RD)

RD width13T RPW 6.0 5.0ns delay from RD to outputs X or Y9T RIO 6.0 5.0ns Global Reset (RESET Pad)*

RESET width (Low)T MRW16.014.0ns delay from RESET pad to outputs X or Y T MRQ19.017.0ns *Timing is based on the XC3042A, for other devices see XACT timing calculator.

Notes:The CLB K to Q output delay (T CKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (T CKDI, #5) of any CLB on the same die.

XC3000A Logic Cell Array Family

IOB Switching Characteristic Guidelines

REGISTERED IN

DIRECT IN

OUT

3- STATE

I/O Block (I)

I/O Pad Input

I/O Clock (IK/OK)

I/O Block (RI)

RESET

I/O Block (O)

I/O Pad TS

I/O Pad Output

(Direct)

I/O Pad Output

(Registered)

X5425

RRI

IOB Switching Characteristic Guidelines (continued)

Speed Grade-7-6

Description Symbol Min Max Min Max Units Propagation Delays (Input)

Pad to Direct In (I)3T PID 4.0 3.0ns Pad to Registered In (Q) with latch transparent T PTG15.014.0ns Clock (IK) to Registered In (Q)4T IKRI 3.0 2.5ns Set-up Time (Input)

Pad to Clock (IK) set-up time1T PICK14.012.0ns Propagation Delays (Output)

Clock (OK) to Pad(fast)7T OKPO8.07.0ns same(slew rate limited)7T OKPO18.015.0ns Output (O) to Pad(fast)10T OPF 6.0 5.0ns same(slew-rate limited)10T OPS16.013.0ns 3-state to Pad begin hi-Z (fast)9T TSHZ10.09.0ns same(slew-rate limited)9T TSHZ20.012.0ns 3-state to Pad active and valid (fast)8T TSON11.010.0ns same(slew -rate limited)8T TSON21.018.0ns Set-up and Hold Times (Output)

Output (O) to clock (OK) set-up time5T OOK8.07.0ns Output (O) to clock (OK) hold time6T OKO00ns Clock

Clock High time11T IOH 4.0 3.5ns Clock Low time12T IOL 4.0 3.5ns Max. flip-flop toggle rate F CLK113.0135.0MHz Global Reset Delays (based on XC3042A)

RESET Pad to Registered In (Q)13T RRI24.023.0ns RESET Pad to output pad (fast)15T RPO33.029.0ns

(slew-rate limited)15T RPO43.037.0ns Notes:1.Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see page XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.

2.Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the

internal pull-up resistor or alternatively configured as a driven output or driven from an external source.

3.Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract

clock delay (pad to IK) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.

4.T PID, T PTG, and T PICK are 3 ns higher for XTL2 when the pin is configured as a user input.

XC3000A Logic Cell Array Family

PINS 44

100

132144160164175176208223

TOP-TOP-TYPE PLAST.

PLAST.PLAST.PLAST.CERAM PLAST.PLAST.PLAST.BRAZED PLAST.CERAM.PLAST.

PLAST.BRAZED PLAST.CERAM.PLAST.

PLAST.CERAM.

PLCC VQFP PLCC PLCC PGA PQFP

TQFP

VQFP CQFP PGA PGA TQFP PQFP CQFP PGA PGA TQFP

PQFP PGA

CODE

PC44VQ64PC68

PC84

PG84

PQ100TQ100VQ100CB100PP132PG132TQ144PQ160CB164PP175PG175TQ176PQ208PG223

-7

I C

I -6C

C C C -7C

I C

I C I C I C

I C I C

I -6C

C C C C -7C

I C

I C I C

I C

I -6C C

C C C -7C I C

I C I C I C

I -6C C

C -7 C I C I C

I C

I -6

C = Commercial = 0° to +70° C I = Industrial = -40 to +85° C M = Mil Temp = -55° to +125° C B = MIL-STD-883C Class B XC3064A XC3042A XC3030A XC3020A XC3090A

For a detailed description of the device architecture, see pages 2-105 through 2-123.

For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132.For detailed lists of package pin-outs, see pages 2-140 through 2-150.For package physical dimensions and thermal data, see Section 4.

Ordering Information

Example:XC3020A-6PC84C

Component Availability Number of Pins Temperature Range

Package Type

Block Delay

Device Type C = Commercial = 0° to +85° C I = Industrial = -40° to +100° C M = Mil Temp = -55° to +125° C B = MIL-STD-883C Class B