VByOne TX Spec V1.5
VByOne Tx Spec.
1Introduction.............................................................................................................- 1 -2Features...................................................................................................................- 1 -3Block diagram.........................................................................................................- 2 -4Interface Signals......................................................................................................- 8 -5Input SPEC............................................................................................................- 10 -6Clock structure......................................................................................................- 11 -7Input data format...................................................................................................- 13 -8Timing margin for integration..............................................................................- 16 -9VByOneTx_Reg interface......................................................................................- 3 -10RGB2VByOne interface.......................................................................................- 17 -
Version and Notes
Version Date Notes
28th 2010 Initial version based on VByOne 1.0 Jul.
PHY
28th 2010 Add the PXCLK for PLL, Change 1.1 Jul.
the LOCKN and HTPDN to four
input, add 3D mode
24th 2010 Add register reg_lanes_num for 1.2 Aug.
RGB2VByOne，change the
structure and interface
31th 2010 Change the LOCKN and HTPDN 1.3 Aug.
to eight, change the clock structure
and top level diagram
4th 2010 Make more clear
1.4 Sep.
1.5 Sep.
28th 2010 Add link diagram and phy
diagram, change the interface
according current design
1Introduction
VByOne targets a high speed data transmission of video signals based on internal connection of
Fig.1-1 Top level diagram
As shown in fig.1-1, the VByOne TX is a major module of the chip, which will receive the video data from DPORT and sent out according to VByOne SPEC.
2Features
The main features are as following:
Supports up to 3.75Gbps data rate (effective data rate 3Gbps)
Supports scrambling and Clock Data Recovery (CDR) to reduce EMI
Output lanes flexible mapping
Configurable 1/2/4/8 lanes
Color depth 18/24/30/36/32/40-bit
PI interface for register read/write
Test mode control for ATPG
3 Block diagram
VbyOne TX
RGB2VByOne
VByOneTx_Reg
VH_FIELDBET_PG
Main logic
PHY_VX1_TOP PHY_PMAPCS_TOP
Epcs _link
phy phy
phy
phy phy phy phy phy
Thine Link Top Thine_Link Thine_Link
Thine_Link Thine_Link Thine_Link Thine_Link Thine_Link Thine_Link
Glue logic (clock divider and tie high/low)
SYS
As shown in above figure, the VByOne TX includes five main modules, RGB2VByOne VByOneTx_Reg, Thine_Link_TOP,PHY_Vx1_Top and the SYS. The RGB2VByOne module will change the video format and do flexible mapping between the 8 lanes. The VByOneTx_Reg handle the register control logic, Thine_Link_Top will do change the input data to 8bit and do encoder and scramble, while PHY_VX1_TOP will receives data from link layer and sent out serially, the SYS will control reset and clock, make sure there is no remove and recover problem for asynchronous reset.
3.1 RGB2Vbyone
3.1.1 Features
The main features are as following:
Input TTL data Odd/Even channel exchange Output lanes flexible mapping Configurable 1/2/4/8 lanes
Color depth 18/24/30/36/32/40-bit PI interface for register read/write Test mode control for ATPG
3.1.2 Block diagram
RGB2VByOne
Swap conrtol
Lane mapping output
VByOneTx_Reg
Link and phy control
d_data
de/hsync /vshync pxl_clk
VH_FIELDBET _PG
pxl_data_x_o de/hsync/vsync
Phy_test_en
Afifo Control Sync fifo data fifo
As shown in above figure, the RGB2V-by-One block has two clocks, one is dclk, another is pxl_clk, whose relationship is as following: pxl_clk = dclk*bus_number/lanes_number
bus number equal to 1 for single bus, 2 for dual bus
Tab. 3-1 the relationship of pclk and dxl_clk Items 1 lanes 2 lanes 4lanes 8 lanes Single pixel mode 1 1/2 1/4 1/8 Dual pixel mode
NA 1 1/2 1/4 pxl_clk frequency is very low(20-125MHz), dual pixel mode input should be avoid in 1 lane case, which will make the design more simple.
3.1.3 VByOneTx_Reg interface Tab. 3-2 VByoneTx_Reg interface Signal name Bit
width
Description
OCP_c_clk_i 1
Register access clock, which is used for
register W/R
OCP_c_rtsn_i 1 Reset signal for cfg_clk, low active OCP_c_Mcmd_i[2:0] 3 OCP bus command OCP_c_MAddr_i[16:0] 17 OCP access address OCP_c_MData_i[31:0] 32 OCP write data
OCP_c_MByteEn_i[3:0] 1 Byte enable signals, each bit enable one
byte in OCP_c_MData_i
to
master
OCP
Respond
OCP_c_SResp_o[1:0] 1
OCP_c_SData[31:0]_o 32 Read data from register
OCP_c_SCmdAccept_o Master data accept by slave, High active reg_color_swap_o[2:0] 3 color swap 0:RGB,1:RBG,2:GBR,
3:GRB,4:BRG,5BGR,others:RGB(the
RGB can be replaced by CrYCb, in
YCbCr444mode)
reg_color_depth_o[2:0] 3
depth,
Color
0000:18bit RGB/YCbCr444
0001:24bit RGB/YCbCr444
0010:30bit RGB/YCbCr444
0011:36bit RGB/YCbCr444
0100:32bit RGBW/RGBY
0101:40bit RGBW/RGBY
0110:16bit YCbCr422
0111:20bit YCbCr422
1000:24bit YCbCr422
1001:32bit YCbCr422
reg_pixel_mode_o 1 Pixel bus number, 0: single bus, 1:dual
bus
reg_channel_swap_o 1 Chanel swap for dual bus mode, 0:
[odd,even], 1: [even,odd]
reg_lanes_num_o[2:0] 3 The output lanes number ,0: 1 lanes,1: 2
lanes, 2: 3lanes, 3: 4lanes, 4: 5 lanes, 5:
6lanes, 6 7lanes, 7 8lanes
reg_lane1_map_o[2:0] 3 Lane 1 output select, 0: segment 0,
1:segment 1, 2:segment 2, 3:segment 3,
4:segment 4, 5:segment 5, 6:segment 6,
7:segment 7
reg_lane2_map_o[2:0] 3 Lane 2 output select, 0: segment 0,
1:segment 1, 2:segment 2, 3:segment 3,
4:segment 4, 5:segment 5, 6:segment 6,
7:segment 7
reg_lane3_map_o[2:0] 3 Lane 3 output select, 0: segment 0,
1:segment 1, 2:segment 2, 3:segment 3,
4:segment 4, 5:segment 5, 6:segment 6,
7:segment 7
reg_lane4_map_o[2:0] 3 Lane 4 output select, 0: segment 0,
1:segment 1, 2:segment 2, 3:segment 3,
4:segment 4, 5:segment 5, 6:segment 6,
7:segment 7
reg_lane5_map_o[2:0] 3 Lane 5 output select, 0: segment 0,
1:segment 1, 2:segment 2, 3:segment 3,
4:segment 4, 5:segment 5, 6:segment 6,
7:segment 7
reg_lane6_map_o[2:0] 3 Lane 6 output select, 0: segment 0,
1:segment 1, 2:segment 2, 3:segment 3,
4:segment 4, 5:segment 5, 6:segment 6,
7:segment 7
reg_lane7_map_o[2:0] 3 Lane 7 output select, 0: segment 0,
1:segment 1, 2:segment 2, 3:segment 3,
4:segment 4, 5:segment 5, 6:segment 6,
7:segment 7
reg_ctl_o[23:0] 24 Data in V-by-one blank period(connect
to RGB2VByOne)
:
=0b
= 1
M
phy_mode[2]
=
Reg_phy_mode_o[3:0] 4
o
- PLL F factor and 3B/4B/5B mode per
pixel clock
o phy_mode[1:0]==00b : F=3, 3B mode
o phy_mode[1:0]==01b : F=4, 4B mode
o phy_mode[1:0]==10b : F=5, 5B mode
Reg_HTPDN_CTL_RESET_EN_o 1 Use hot plug control the PHY reset, 1:
enable, 0:disable
REG_RD_THLD_o[3:0] 1 Fifo read start threshold,
Reg_auto_recover_sel_o[3:0] 4 When fifo error, recover the digital logic
Reg_3d_en_o 1 3D enable control, when enable, the
input three_d_en and lr_view signal will
be sent out
Reg_pro_intf_reset_o 1 ABI programmable interface reset
control, this signal should be remove
after reg_phy_mode is ready
Reg_fast_int_o 1 This signal just use to speed up the
simulation
Reg_link_pd_o[7:0] 8 Link power down control, high active
Reg_pd_lane_o[7:0] 8 Power lane control, high active
Reg_pd_lpclkp_o 1 LPCLKp clock domain power down
control, high active
Reg_pd_LSCLKp_o 1 LSCLKp clock domain power down
control, high active
Reg_reset_LPCLKp_o 1 LPCLKp clock domain software reset
control, high active
Reg_reset_phy_o 1 Phy software reset control, high active
output
select.
hsync/vsync/de
Debug
Reg_debug_ctl_sel_o 1
1:select the output signal, 0: select the
input signal
Reg_debug_clk_div_o 2 Debug clock divider, 0: div2,
1:div4,2:div6,3: no diviver
Reg_debug_clk_sel_o 2 Debug clock source select. 0?: disable
the debug clock output, 10: select the
Lsclkpdiv, 11: select the lpclkpdiv HTPDN_i[7:0] 8 The hot plug status of each lane receiver,
1: the receiver is not ready, 0 the receiver
is ready
PLL_STABLE_i[7:0] 8 Pll lock indicator, high active
Sync_fifo_underrun_intp_i 1 Sync fifo underrun interrupt
Sync_fifo_overrun_intp_i 1 Sync fifo overrun interrupt
Data_fifo_underrun_intp_i 1 data fifo underrun interrupt
data_fifo_overrun_intp_i 1 Data fifo overrun interrupt
reg_req_o 1 Register request. This request is kept
asserted until the reg_ack signal is
asserted for acknowledgement of the
request.
reg_ack_o 1 Register acknowledge. This signal is
asserted for one clock cycle in order to
acknowledge the register access request
reg_req.
reg_lane_o[7:0] 8 Lane select : This signal defines which
lanes are accessed and must be one-hot
encoded for read transaction. For write
transaction, one or several lanes can be
written in the same time when several
bits are asserted.
reg_rwn_o 1 Read/WriteN : When set, this signal
defines a read operation, otherwise a
write operation.
reg_addr_o[7:0] 8 Register address : this signal defines the
byte address of the transaction.
reg_wdata_o[7:0] 8 Register Write data bus : this signal
defines the data to write in register
reg_rdata_i[7:0] 8 Register Read data bus: this signal
defines the data read from the specifies
lane register space.
The input for this module is standard OCP PI bus, the output is control register for
reg2V-By-One and PHY layer module.
The OCP PI bus document is shown in OCP-IP_OpenCoreProtocolSpecification-2.2.
3.2 Link
Fig. 3-3 the Link diagram
At first, the link training for CDR is performed. After Link training finished, the Transmitter starts the normal mode operation.
In the Packer, the input data from user logic are packed to the packet include 8bit data character. After the packing, packets are scrambled with pseudo random numbers in the Scrambler. On Encoder, the scrambled 8bit packet data is encoded to 10bit character for an approximate DC balance as well as sufficient 0-1 and 1-0 transitions for the CDR. At last, 10bit data character is serialized to 1bit stream by the Serializer.
The Receiver performs the inverse process to convert the serial data from the Transmitter to the pixel data for user logic.
3.3 PHY
Fig. 3-4 the PHY diagram
The PHY will receive the data from link and send data out one bit by one bit. Current PHY is based on pcie PHY, in our application the RX and 8b/10B encoder is never used. There is a programmable interface for each hard macro, the address is as following:
0x400~ 0x07FC : lane 0
0x800~ 0x0BFC: lane 1
0xC00~ 0x0FFC: lane 2
0x1000~0x13FC: lane 3
0x1400~0x17FC: lane 4
0x1800~0x1BFC: lane 5
0x1C00~0x1FFC: lane 6
0x2000~0x23FC: lane 7
0x2400~0x27FC:
4Interface Signals
The interface signals are as following:
Table 4-1 the interface signals
Signal name Bit width Description
Input clock and signals
dclk_i 1 clock, when works in single pixel mode, the
frequency is video data clock, while in dual
pixel mode, the frequency is half of the video
data clock
drstn_i 1 Reset signal for dclk, low active
d_data_odd_i[47:0] 48 Odd video data in dual pixel
mode(P1,P3,P5…), unused in single pixel
mode
d_data_even_i[47:0] 48 Even video data in dual pixel mode
(P0,P2,P4…)and video data in single pixel
mode
de_i 1 data valid indicator, when high indicate the
pixel data is valid
Timing
signal
hsync_i 1
Timing
signal
vsync_i 1
three_d_en_i 1 Indicate current frame is 3D or 2D,
1:3D,0:2D
lr_view_i 1 Indicate the next frame is left view or right
view for 3D mode, just update at the last
pixel of last line in current frame
1:left view,0:right view
pxl_ref_clk_i 1 PHY PLL reference clock, from the another
PLL, make sure the jitter meet the requirment reset 1 Hard ware reset for IP
HTPDN_i[7:0] 8 Hot plug indicator from RX, [n]for lane n, n
equal to 0 (7)
LOCKN_i[7:0] 8 PLL Lock indicator form RX, [n]for lane n, n
equal to 0 (7)
ATPG test clock and reset
Phy_test_en_i 1 ATPG PHY TEST, when in test mode, the
pxl_ref_clk_i should be the test clock
Scan_mode 1 Can mode cut clean reset logic for PHY Scan_clk Multplex scan_clk with any other clocks
when in scan mode, for PHY
enable
scanen 1
Scan
acjatpP 8 Output from PHY
acjtagN 8 Output from PHY
aIDDQ 8 Output from PHY
OCP PI register control bus
OCP_c_clk_i 1 Register access clock, which is used for
register W/R
OCP_c_rtsn_i 1 Reset signal for cfg_clk, low active
OCP_c_Mcmd_i[2:0] 3 OCP
command
bus
OCP_c_MAddr_i[16:0] 17 OCP access address
data
write
OCP_c_MData_i[31:0] 32 OCP
OCP_c_MByteEn_i[3:0] 1 Byte enable signals, each bit enable one byte
in OCP_c_MData_i
OCP_c_SResp_o[1:0] 1 Respond to OCP master
OCP_c_SData[31:0]_o 32 Read data from register
OCP_c_SCmdAccept_o 1 Master data accept by slave, High active
Analog I/O
TXDP 8 Serial differential positive output from PHY TXDN 8 Serial differential negative output from PHY RXDP 8 The pcie input, not used in Vx1
RXDN 8 The pcie input, not used in Vx1
Rext 1 External resistance connected to lane 0 for
PHY
VDDPLL 8 Power supply for PHY
PLL_REF_RETURN 8 Power supply for PHY
VAUX 8 Power supply for PHY
VDDIO 8 Power supply for PHY
VSSIO 8 Power supply for PHY
Debug interface
signal
debug
reset
Pll
Vx1_pll_rstn 1
Vx1_debug_clk 1 Debug clock output select
Vx1_debug_pll_status[7:0] 8 Pll status
output
hsync
Vx1_debug_hsync 1 Debug
vsync
output
Vx1_debug_vsync 1 Debug
output
de
Debug
Vx1_debug_de 1
5Input SPEC
The input video is capture and processing, the video format must meet the lanes constraints for processing, the detail is as following:
1.Horizontal_total_pixel_number = n * lanes number
2.Horizontal_active_pixel_number = m * lanes number
3.Horizontal_front_porch ≥ lanes number
4.Horizontal_back_porch ≥ lanes number
Horizontal_hsync_width ≥ lanes number
6Clock structure
RGB2VByOne
VH_FIELDBET_PG
Main logic
pix_ref_clk_i (100MHz)
LPCLKp_icg
pix_clk_i
GATECLK
GATECLK
CLK_PG_i
Fig. 6-1 clock structure
The clock structure is shown as above, the pix_clk will be used as reference for
PHY_Vx1_TOP. The PCIE PLL use pix_clk as reference to generate LSCLKp and PHY required clock, the LSCLKp will be used to generate the LPCKp (the LRCLKp will connect to LPCLKp )and MXCLKp[4:0] in the PHY_VX1_TOP, the detail relationship is as following:
pix_clk_i Vs LRCLKp Vs LPCKp: the same clock have the same frequency and same phase ( a little different with Thine’s solution, Thine use the inversed clock)
LPCLKp Vs LSCLKp: the LPCLKp is generated from LSCLKp, f PIX_CLK=f LSCKp/N, N equal to 3/4/5 for different mode
MXCLKp Vs LSCKp: MXCLKp works as the “One HOT” enable signal for data each byte. ie) In the 3ByteMode, only one of MXCLK[2:0] should be HIGH for each LSCLKp cycle, and there should be no LSCLKp cycle where none of MXCLKp[2:0] is HIGH That is to say, the MXCLKp have the same frequency with LSCLKp, but the duty cycle of the MXCLKp is not 50%, it is 1/Xbyte mode, in 3 byte mode is 33.3% and in 4byte mode is 25%, in 5byte mode is 20%, this signals repeat as the “One HOT” enable signal as following picture.
3byte mode. f LSCLKp = 3 * f LPCLKp f LSCLKp= 3 *f MXCLKp (phase different)
5byte mode. f LSCLKp = 5 * f LPCLKp f LSCLKp= 5 *f MXCLKp (phase different)
7Input data format
The input data include control signal signals (de/hsync/vsync) and video data, the video data width is 60 bit, whose format is different according to color depth and work mode, the detail is shown as Tab6-1.
Tab. 7-1 The video data in different color depth
TTL_Signal 36bpp
RGB/
YCbCr444
30bpp
RGB/
YCbCr444
24bpp
RGB/
YCbCr444
18bpp
RGB/
YCbCr444
40bpp
RGBW/
RGBY
32bpp
RGBW/
RGBY
D[47] R/Cr[11] R/Cr[9] R/Cr[7] R/Cr[5] R[9] R[7] D[46] R/Cr[10] R/Cr[8] R/Cr[6] R/Cr[4] R[8] R[6] D[45] R/Cr[9] R/Cr[7] R/Cr[5] R/Cr[3] R[7] R[5] D[44] R/Cr[8] R/Cr[6] R/Cr[4] R/Cr[2] R[6] R[4] D[43] R/Cr[7] R/Cr[5] R/Cr[3] R/Cr[1] R[5] R[3] D[42] R/Cr[6] R/Cr[4] R/Cr[2] R/Cr[0] R[4] R[2] D[41] R/Cr[5] R/Cr[3] R/Cr[1] R[3] R[1] D[40] R/Cr[4] R/Cr[2] R/Cr[0] R[2] R[0] D[39] R/Cr[3] R/Cr[1] R[1]
D[38] R/Cr[2] R/Cr[0] R[0]
D[37] R/Cr[1]
D[36] R/Cr[0]
D[35] G/Y[11] G/Y[9] G/Y[7] G/Y[5] G[9] G[7]
D[34] G/Y[10] G/Y[8] G/Y[6] G/Y[4] G[8] G[6]
D[33] G/Y[9] G/Y[7] G/Y[5] G/Y[3] G[7] G[5]
D[32] G/Y[8] G/Y[6] G/Y[4] G/Y[2] G[6] G[4]
D[31] G/Y[7] G/Y[5] G/Y[3] G/Y[1] G[5] G[3]
D[30] G/Y[6] G/Y[4] G/Y[2] G/Y[0] G[4] G[2]
D[29] G/Y[5] G/Y[3] G/Y[1] G[3] G[1]
D[28] G/Y[4] G/Y[2] G/Y[0] G[2] G[0]
D[27] G/Y[3] G/Y[1] G[1]
D[26] G/Y[2] G/Y[0] G[0]
D[25] G/Y[1]
D[24] G/Y[0]
D[23] B/Cb[11] B/Cb[9] B/Cb[7] B/Cb[5] B[9] B[7]
D[22] B/Cb[10] B/Cb[8] B/Cb[6] B/Cb[4] B[8] B[6]
D[21] B/Cb[9] B/Cb[7] B/Cb[5] B/Cb[3] B[7] B[5]
D[20] B/Cb[8] B/Cb[6] B/Cb[4] B/Cb[2] B[6] B[4]
D[19] B/Cb[7] B/Cb[5] B/Cb[3] B/Cb[1] B[5] B[3]
D[18] B/Cb[6] B/Cb[4] B/Cb[2] B/Cb[0] B[4] B[2]
D[17] B/Cb[5] B/Cb[3] B/Cb[1] B[3] B[1]
D[16] B/Cb[4] B/Cb[2] B/Cb[0] B[2] B[0]
D[15] B/Cb[3] B/Cb[1] B[1]
D[14] B/Cb[2] B/Cb[0] B[0]
D[13] B/Cb[1]
D[12] B/Cb[0]
D[11] W/Y[9] W/Y[7] D[10] W/Y[8] W/Y[6] D[9] W/Y[7] W/Y[5] D[8] W/Y[6] W/Y[4] D[7] W/Y[5] W/Y[3] D[6] W/Y[4] W/Y[2] D[5] W/Y[3] W/Y[1] D[4] W/Y[2] W/Y[0] D[3] W/Y[1]
D[2] W/Y[0]
D[1]
D[0]
TTL_Signal 32bpp
YCbCr422
24bpp
YCbCr422
20bpp
YCbCr422
16bpp
YCbCr422
D[47] Cb/Cr[15] Cb/Cr[11] Cb/Cr[9] Cb/Cr[7] D[46] Cb/Cr[14] Cb/Cr[10] Cb/Cr[8] Cb/Cr[6] D[45] Cb/Cr[13] Cb/Cr[9] Cb/Cr[7] Cb/Cr[5]
D[44] Cb/Cr[12] Cb/Cr[8] Cb/Cr[6] Cb/Cr[4] D[43] Cb/Cr[11] Cb/Cr[7] Cb/Cr[5] Cb/Cr[3] D[42] Cb/Cr[10] Cb/Cr[6] Cb/Cr[4] Cb/Cr[2] D[41] Cb/Cr[9] Cb/Cr[5] Cb/Cr[3]
D[40] Cb/Cr[8] Cb/Cr[4] Cb/Cr[2]
D[39] Cb/Cr[7] Cb/Cr[3] Cb/Cr[1]
D[38] Cb/Cr[6] Cb/Cr[2] Cb/Cr[0]
D[37] Cb/Cr[5] Cb/Cr[1]
D[36] Cb/Cr[4] Cb/Cr[0]
D[35] Y[15] Y[11] Y[9] Y[7]
D[34] Y[14] Y[10] Y[8] Y[6]
D[33] Y[13] Y[9] Y[7] Y[5]
D[32] Y[12] Y[8] Y[6] Y[4]
D[31] Y[11] Y[7] Y[5] Y[3]
D[30] Y[10] Y[6] Y[4] Y[2]
D[29] Y[9] Y[5] Y[3] Y[1]
D[28] Y[8] Y[4] Y[2] Y[0]
D[27] Y[7] Y[3] Y[1]
D[26] Y[6] Y[2] Y[0]
D[25] Y[5] Y[1]
D[24] Y[4] Y[0]
D[23] Cb/Cr[3]
D[22] Cb/Cr[2]
D[21] Cb/Cr[1]
D[20] Cb/Cr[0]
D[19] Y[3]
D[18] Y[2]
D[17] Y[1]
D[16] Y[0]
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3] D[2] D[1] D[0]
Note: when working in dual pixel mode the frequency of dclk is just half of the pixel clock
The input data maybe signal pixel mode and dual pixel mode, the difference is data
mapping, the odd data is invalid in dual single pixel mode, while the whole bytes is valid in dual pixel mode. The single pixel mode and dual pixel mode is shown in Fig. 7-1 and Fig. 7-2.
Fig.7-1 single pixel mode
8
Timing margin for integration
In order to make sure there is enough timing margin for integration, all the output signal s from IP must be output through register directly. Besides, the design target for each clock
domain is shown in Tab 8-1. Clock domain Max. clock frequency(MHz)
dclk 420 pxl_clk 125 OCP_c_clk_i 50
Notes: the Max. Clock frequency is real application case, Please add uncertain for each
clock domain when do synthesis.
9RGB2VByOne interface
Table 9-1 the interface signals
Signal name Bit width Description
dclk_i 1 clock, when works in single pixel mode, the
frequency is video data clock, while in dual
pixel mode, the frequency is half of the video
data clock
drstn_i 1 Reset signal for dclk, low active
d_data_odd_i[47:0] 48 Odd video data in dual pixel
mode(P1,P3,P5…), unused in single pixel
mode
d_data_even_i[47:0] 48 Even video data in dual pixel mode
(P0,P2,P4…)and video data in single pixel
mode
de_i 1 data valid indicator, when high indicate the
pixel data is valid
signal
Timing
hsync_i 1
signal
Timing
vsync_i 1
three_d_en_i 1 Indicate current frame is 3D or 2D,
1:3D,0:2D
lr_view_i 1 Indicate the next frame is left view or right
view for 3D mode, just update at the last
pixel of last line in current frame
1:left view,0:right view
depth,
reg_color_depth_i[2:0] 3 Color
0000:18bit RGB/YCbCr444
0001:24bit RGB/YCbCr444
0010:30bit RGB/YCbCr444
0011:36bit RGB/YCbCr444
0100:32bit RGBW/RGBY
0101:40bit RGBW/RGBY
0110:16bit YCbCr422
0111:20bit YCbCr422
1000:24bit YCbCr422
1001:32bit YCbCr422
reg_color_swap_i[2:0] 3 color swap 0:RGB,1:RBG,2:GBR,
3:GRB,4:BRG,5BGR,others:RGB(the RGB
can be replaced by CrYCb, in
YCbCr444mode)
reg_pixel_mode_i 1 Pixel bus number, 0: single bus, 1:dual bus reg_lanes_num_i[2:0] 3 The output lanes number ,0: 1 lanes,1: 2
lanes, 2: 3lanes, 3: 4lanes, 4: 5 lanes, 5: