lpm_shiftreg
101 Innovation Drive San Jose, CA 95134 (408) 544-7000 https://www.wendangku.net/doc/e81441986.html, lpm_shiftreg Megafunction
Quartus II Software Version: 6.0
Document Version: 2.0
Document Date:August 2006
Copyright ? 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
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Altera Corporation lpm_shiftreg Megafunction User Guide August 2006
UG-033105-2.0
Altera Corporation
iii
August 2006Contents
Contents
About this User Guide
Revision History ........................................................................................................................................ v How to Contact Altera .............................................................................................................................. v Typographic Conventions ...................................................................................................................... vi Chapter 1. About this Megafunction
Device Family Support ......................................................................................................................... 1–1Introduction ............................................................................................................................................ 1–2Features ................................................................................................................................................... 1–2General Description ............................................................................................................................... 1–2Common Applications .................................................................................................................... 1–3Resource Utilization & Performance .................................................................................................. 1–4Chapter 2. Getting Started
System Requirements ............................................................................................................................ 2–1MegaWizard Plug-In Manager Customization ................................................................................. 2–1MegaWizard Page Descriptions .......................................................................................................... 2–1Inferring Megafunctions from HDL Code .................................................................................... 2–7Instantiating Megafunctions in HDL Code ....................................................................................... 2–8Identifying a Megafunction after Compilation ................................................................................. 2–8Simulation ............................................................................................................................................... 2–8Quartus II Simulation ...................................................................................................................... 2–8EDA Simulation ................................................................................................................................ 2–9SignalTap II Embedded Logic Analyzer ............................................................................................ 2–9Design Example: Configurable 8-Bit SIPO or PISO Shift Register ............................................... 2–10Design Files ..................................................................................................................................... 2–10Example 1 .............................................................................................................................................. 2–10Generate a Configurable 8-Bit SIPO or PISO Shift Register ..................................................... 2–10Implement the Configurable 8-Bit SIPO or PISO Shift Register .............................................. 2–15Functional Results — S imulate the 8-Bit Shift Register in Quartus II ...................................... 2–17Functional Results — S imulate the 8-Bit Shift Register in ModelSim-Altera ......................... 2–19Design Example: Time Delay ............................................................................................................. 2–21Design Files ..................................................................................................................................... 2–21Example 2 ........................................................................................................................................ 2–21Generate the Time Delay Design ................................................................................................. 2–21Implement the Time Delay Design .............................................................................................. 2–27Functional Results — S imulate the Time Delay Design in Quartus II ..................................... 2–28Functional Results — S imulate the Time Delay Design in ModelSim-Altera ........................ 2–30
iv
Altera
Corporation lpm_shiftreg Megafunction User Guide August 2006Contents lpm_shiftreg Megafunction User Guide
Conclusion ............................................................................................................................................ 2–31Chapter 3. Specifications
Ports & Parameters ................................................................................................................................ 3–1
Altera Corporation
v August 2006
lpm_shiftreg Megafunction User Guide
About this User Guide
Revision History
The table below displays the revision history for the chapters in this User Guide.How to Contact
Altera
For the most up-to-date information about Altera ? products, go to the Altera worldwide web site at https://www.wendangku.net/doc/e81441986.html, . For technical support on this product, go to https://www.wendangku.net/doc/e81441986.html,/mysupport . For additional information about Altera products, consult the sources shown below.Chapter
Date Version Changes Made All
August 2006 2.0Updated for Quartus II 6.0 software release.All
July 2005 4.2Updated for Quartus II 4.2 software release.All March 2005 1.0Initial https://www.wendangku.net/doc/e81441986.html,rmation Type
USA & Canada All Other Locations T echnical support https://www.wendangku.net/doc/e81441986.html,/mysupport/
https://www.wendangku.net/doc/e81441986.html,/mysupport/ (800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m. Pacific Time)(408) 544-7000 (1)(7:00 a.m. to 5:00 p.m. Pacific Time)
Product literature https://www.wendangku.net/doc/e81441986.html, https://www.wendangku.net/doc/e81441986.html,
Altera literature services literature@https://www.wendangku.net/doc/e81441986.html, (1)literature@https://www.wendangku.net/doc/e81441986.html, (1)
Non-technical customer service (800) 767-3753(7:00 a.m. to 5:00 p.m. Pacific Time)(408) 544-7000
(7:30 a.m. to 5:30 p.m. Pacific Time)
FTP site
https://www.wendangku.net/doc/e81441986.html, https://www.wendangku.net/doc/e81441986.html, Note to table:
(1)You can also contact your local Altera sales office or sales representative.
vi
Altera Corporation lpm_shiftreg Megafunction User Guide August 2006Typographic Conventions
Typographic
Conventions
This document uses the typographic conventions shown below.Visual Cue
Meaning Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. bold type External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: f MAX , \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design.
Italic type Internal timing parameters and variables are shown in italic type.
Examples: t PIA , n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example:
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. “Subheading Title”References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “T ypographic Conventions.”
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi , input. Active-low signals are denoted by suffix n , e.g., resetn .
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf . Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN ), as well as logic function names (e.g., TRI ) are shown in
Courier.
1.,
2.,
3., and
a.,
b.,
c., etc.
Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ■ ● ?
Bullets are used in a list of items when the sequence of the items is not important. v
The checkmark indicates a procedure that consists of one step only.1 The hand points to information that requires special attention.
c The caution indicates require
d information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.
w The warning indicates information that should be read prior to starting or
continuing the procedure or processes.
r The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
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lpm_shiftreg Megafunction User Guide
Chapter 1. About this Megafunction Device Family
Support
Megafunctions provide either full or preliminary support for target Altera ? device families, as described below:■Full support means the megafunction meets all functional and timing requirements for the device family and may be used in production designs.■Preliminary support means the megafunction meets all functional requirements, but may still be undergoing timing analysis for the device family. It may be used in production designs with caution.Table 1–1 shows level of support for each Altera device family.Table 1–1. Device Family Support Device Family Support Stratix ? II Full Stratix II GX Full Stratix GX Full Stratix Full Cyclone ? II Full Cyclone Full HardCopy ? II Full HardCopy Stratix Full MAX ? II Full MAX 7000Full MAX 3000Full APEX ? II Full APEX 20KC Full APEX 20KE Full FLEX ? 10K Full FLEX 10KA Full FLEX 10KE Full FLEX 6000Full ACEX ? 1K Full
1–2
Altera Corporation lpm_shiftreg Megafunction User Guide August 2006Introduction
Introduction As design complexities increase, use of vendor-specific IP blocks has
become common design methodology. Altera provides parameterizable
megafunctions optimized for Altera device architectures. Using
megafunctions instead of coding your own logic saves valuable design
time, offering more efficient logic synthesis and device implementation.
Scale the megafunction's size by simply setting parameters.
Features The lpm_shiftreg megafunction implements a shift register and offers
many additional features, including:
■
Fully parameterizable ■
Synchronous or asynchronous inputs to shift register ■
Synchronous parallel load ■
Left/right register shifting ■
Optional inputs, including clock enable input, serial shift data input, and parallel input ■Optional outputs, including data output and serial shift data output
General
Description The lpm_shiftreg megafunction is a storage megafunction provided in the Quartus II ? MegaWizard ? Plug-In Manager. Shift registers are a type
of sequential logic circuit, mainly for storage of digital data. They are a
group of flip-flops connected in a chain so that the output from one
flip-flop becomes the input of the next flip-flop. Most of the registers
possess no characteristic internal sequence of states. All the flip-flops are
driven by a common clock and are set or reset simultaneously. A shift
register is useful for converting parallel signals to serial signals and vice
versa.
Shift register megafunction provided by Altera is a very versatile
parameterizable block of logic. Thus long delay chains can be instantiated
using this megafunction. This megafunction provides for either left shift
or right shift of the input data bits. Data that has to be shifted is either
loaded in parallel into the registers synchronously or in serial through the
'shiftin ' input of the megafunction. The loaded data is then shifted
with the rising edge of clock input.
The shift operation is a single clock-edge operation with an active-high
clock enable feature. When enable is High, the input (D) is loaded into the
first bit of the shift register, and each bit is shifted to the next highest bit
position. Figure 1–1 illustrates the shift operations. Cascading of shift
registers is another way of using the lpm_shiftreg megafunction to
achieve higher shift count or bit count.
Optional inputs are available to asynchronously clear or set the registers,
or synchronously clear or set the registers. Using this feature, you can
either set the initial value of all the registers to 1, or to a desired value.
About this Megafunction
Parallel output q[] is used to read parallel data from the shift register.
Parallel data is always available on the q[] outputs at every clock. When
data is shifted serially with every clock, you get the MSB of the q[]
output on the 'shiftout' pin. A shift operation is shown in Figure 1–1. Figure 1–1. Shift Operation
Common Applications
Use the lpm_shiftreg megafunction to replace all other types of shift
register functions.
Shift registers enable the development of efficient designs for
applications that require delay or latency compensation. Shift registers
are also useful in synchronous FIFO and content addressable memory
(CAM) designs. Shift registers are often used as the state register in a
sequential device. Usually, the next state is determined by shifting right
and inserting a primary input or output into the next position (for
example, a finite memory machine). They are very effective for sequence
detectors. Shift registers are used for Serial interconnection of systems
that keeps interconnection cost low with serial interconnect. Shift
registers are used for Bit Serial Operations. Bit serial operations can be
performed quickly through device iteration.
The lpm_shiftreg megafunction finds applications where there is a
need to shift the data in or out of digital systems. Serial to Parallel
Conversion, Parallel to Serial Conversion, and delay generation for
multistage pipeline stages are some of the common applications of a shift
register.
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1–4
Altera Corporation lpm_shiftreg Megafunction User Guide August 2006Resource Utilization & Performance
Resource
Utilization &
Performance This megafunction uses one logic cell per bit. Table 1–2 shows the resource usage for each Altera device family.The MegaWizard ? Plug-In Manager reports approximate resource
utilization based on user specification and parameters, available in the
lower left corner of the MegaWizard Plug-In Manager screen.Table 1–2. lpm_shiftreg Resource Usage
Device Family
Optimization (1)Width Logic Elements Stratix II
Balanced 8-Bit 8 ALUT Stratix GX
Balanced 8-Bit 8 logic elements Stratix
Balanced 8-Bit 8 logic elements
Cyclone II
Balanced 8-Bit 8 logic elements Cyclone
Balanced 8-Bit 8 logic elements MAX II
Balanced 8-Bit 8 logic elements MAX 7000
Balanced 8-Bit 8 registers MAX 3000
Balanced 8-Bit 8 registers APEX II
Balanced 8-Bit 8 registers APEX 20KC
Balanced 8-Bit 8 registers APEX 20KE
Balanced 8-Bit 8 registers FLEX 10K
Balanced 8-Bit 8 registers FLEX 10KA
Balanced 8-Bit 8 registers FLEX 10KE
Balanced 8-Bit 8 registers FLEX 6000
Balanced 8-Bit 8 registers ACEX 1K
Balanced 8-Bit 8 registers Note for Table 1–2:
(1)Choose a design implementation that balances high performance with minimal
logic usage. This setting is available for Cyclone series, MAX II, Stratix, and Stratix
II devices only. The balanced optimization logic option can be set on the
Assignments menu in Analysis and Synthesis settings .
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lpm_shiftreg Megafunction User Guide
Chapter 2. Getting Started System
Requirements
The instructions in this section require the following hardware and software:■ A PC running the Windows 2000/XP , Red Hat Linux Enterprise 3 or 4, or a Sun workstation running the Solaris 8 or 9 operating system ■The Quartus ? II software version 6.0 or higher MegaWizard
Plug-In Manager
Customization
Use the MegaWizard ? Plug-In Manager to specify the lpm_shiftreg megafunction features for each shift register function in your design.Start the MegaWizard Plug-In Manager in one of the following ways:■On the Tools menu, click the MegaWizard Plug-In Manager command.■When working in the Block Editor, click MegaWizard Plug-In Manager in the Symbol dialog box.■Start the stand-alone version of the MegaWizard Plug-In Manager by typing the following command at the command prompt:qmegawiz r MegaWizard
Page
Descriptions
This section provides descriptions of the options available on the individual pages of the lpm_shiftreg wizard.On page 1 of the MegaWizard Plug-In Manager, you can choose to Create a new custom megafunction variation , Edit an existing megafunction variation , or Copy an existing custom megafunction variation (Figure 2–1).
MegaWizard Page Descriptions
Figure 2–1. MegaWizard Plug-In Manager [page 1]
On page 2a of the wizard, specify plug-in, select device family, output file
type, and name of output file (Figure 2–2). Choose AHDL (.tdf), VHDL
(.vhd), or Verilog HDL (.v). You can also create a clearbox instantiation for
third-party EDA tools.
2–2Altera Corporation lpm_shiftreg Megafunction User Guide August 2006
Getting Started
Figure 2–2. MegaWizard Plug-In Manager [page 2a]
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2–4
Altera Corporation lpm_shiftreg Megafunction User Guide August 2006MegaWizard Page Descriptions
On page 3 of the wizard, select the width of the output bus, specify the
shift direction, shift register output, and optional inputs. (Figure 2–3).Figure 2–3. MegaWizard Plug-In Manager [page 3]
Table 2–1 describes the options on page 3 of the lpm_shiftreg
wizard.Table 2–1. lpm_shiftreg MegaWizard Plug-in Manager Page 3 Options (Part 1 of 2)
Function
Description How wide should the 'q' output bus
be?
Select the width for the 'q' output bus. The maximum size of the 'q' output bus can be 256 bits. Manually enter widths greater than 256.Which direction do you want the
registers to shift?Select 'left ' or 'right ' to define the direction of data shift.
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On page 4, specify synchronous and asynchronous inputs (Figure 2–4).Figure 2–4. lpm_shiftreg Wizard [page 4]Which outputs do you want (select at least one)?
Select 'Data output ' (parallel output), 'Serial shift data output ', or select both.
Do you want any optional inputs?Select optional inputs to shift register. Select 'Clock Enable input '
to provide enable function to clock input. Load shift register with parallel
data. Use serial shift data input feature to put serial data into shift register.
Table 2–1. lpm_shiftreg MegaWizard Plug-in Manager Page 3 Options (Part 2 of 2)
Function Description
2–6
Altera Corporation lpm_shiftreg Megafunction User Guide August 2006MegaWizard Page Descriptions
On page 6 of the wizard, specify the types of files to be generated. Choose
from HDL wrapper file, (
(.bsf ), Instantiation template file (
Black Box declaration file (
Function Description
Do you want any optional inputs?Select synchronous and/or asynchronous inputs. Use synchronous or asynchronous set and clear inputs of the shift register as optional features.
Synchronous
inputs Shift register has optional synchronous clear and set inputs. Use 'clear ' input to clear all registers synchronously. Use 'set ' input to either set all q[] outputs to 1’s or to a particular
value specified in 'Set to ' field. The sclr signal affects q[] outputs before polarity is
applied to ports. If both sset and sclr are used and both are asserted, sclr is dominant.
Asynchronous inputs.
Shift register has optional asynchronous clear and set options. Use 'clear ' to
asynchronously clear all q[] outputs. aclr signal affects q[] outputs before polarity is
applied to ports. Use 'set ' input to either set all q[] outputs to 1’s or to a particular value
specified in 'Set to ' field. The aclr signal affects q[] outputs before polarity is applied
to ports. If both aset and aclr are used and both are asserted, aclr is dominant.
Altera Corporation
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f For more information about the ports for the lpm_shiftreg
megafunction, refer to the Specifications chapter in this User Guide.Inferring Megafunctions from HDL Code
Synthesis tools, including the Quartus II integrated synthesis, recognize specific types of HDL code, automatically inferring the appropriate megafunction when a megafunction will provide optimal results. The Quartus II software uses the Altera ? megafunction code when compiling your design, even if it was not specifically instantiated. The Quartus II software infers megafunctions which are optimized for Altera devices, so the area and/or performance may be better than generic HDL code. Use megafunctions to access Altera architecture-specific features, such as memory, DSP blocks, and shift registers, providing improved
performance compared with basic logic elements.
2–8
Altera Corporation lpm_shiftreg Megafunction User Guide August 2006Instantiating Megafunctions in HDL Code
Refer to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook for more information.
Instantiating
Megafunctions
in HDL Code When you use the MegaWizard Plug-In Manager to set up and parameterize a megafunction, it creates either a VHDL or Verilog HDL wrapper file that instantiates the megafunction (a black-box
methodology). For some megafunctions, you can generate a fully
synthesizable netlist for improved results with EDA synthesis tools, such as Synplify and Precision RTL Synthesis (a clear-box methodology). Both clear-box and black-box methodologies are described in the third-party synthesis support chapters in the Quartus II Handbook .
■
Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook ■
Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook ■
Synplicity Synplify & Synplify Pro Support chapter in volume 1 of the Quartus II Handbook ■Mentor Graphics Precision RTL Synthesis Support chapter in volume 1
of the Quartus II Handbook
Identifying a
Megafunction
after
Compilation During compilation with the Quartus II software, analysis and elaboration is performed to build the structure of your design. To locate your megafunction in the Project Navigator window, expand the compilation hierarchy and find the megafunction by its name.To search for node names within the megafunction (using the Node
Finder), click Browse (…) in the Look in box and select the megafunction in the Hierarchy box.
Simulation
The Quartus II Simulation tool provides an easy-to-use, integrated
solution for performing simulations. The following sections describe the simulation options.Quartus II Simulation
With the Quartus II Simulator, you can perform two types of simulations: functional and timing. The functional simulation enables you to verify the logical operation of your design without taking into consideration the timing delays in the FPGA. This simulation is performed using only your RTL code. When performing a functional simulation, you can view signals that exist before synthesis. You can find these signals with the Registers: pre-synthesis, Design Entry, or Pin filters in the Node Finder. The top-level ports of megafunctions are found using these three filters.
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In contrast, timing simulation in the Quartus II software verifies the operation of your design with annotated timing information. This simulation is performed using the post place-and-route netlist. When performing a timing simulation, you are able to view signals that exist after place-and-route. These signals are found with the Post-Compilation filter of the Node Finder. During synthesis and place-and-route, the names of RTL signals change. Therefore, it might be difficult to find signals from your megafunction instantiation in the Post-Compilation filter. To preserve the names of your signals during the synthesis and place-and-route stages, use the synthesis attributes keep or preserve . These are Verilog and VHDL synthesis attributes that direct analysis & synthesis to keep a particular wire, register, or node intact. Use these synthesis attributes to keep a combinational logic node so you can observe the node during simulation. Refer to the Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook .EDA Simulation Depending on the third-party simulation tool you are using, refer to the appropriate chapter in the Simulation section in volume 3 of the Quartus II Handbook . These tool-specific chapters show you how to perform functional and gate-level timing simulations including megafunctions, and the necessary files and file directories.SignalTap II
Embedded Logic
Analyzer
The SignalTap ? II embedded logic analyzer provides a method of debugging the Altera megafunctions within your design. With the SignalTap II embedded logic analyzer, capture and analyze data samples for top-level ports of the megafunctions in your design while your system is running at full speed.To monitor signals from your megafunctions, first configure the SignalTap II embedded logic analyzer in the Quartus II software, and include the analyzer as part of your project. The Quartus II software seamlessly embeds the analyzer with your design in the selected device.f
For more information about using the SignalTap II embedded logic analyzer, refer to the Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in volume 3 of the Quartus II Handbook .
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Altera Corporation lpm_shiftreg Megafunction User Guide August 2006Design Example: Configurable 8-Bit SIPO or PISO Shift Register
Design Example:
Configurable
8-Bit SIPO or
PISO Shift
Register This design example uses the lpm_shiftreg megafunction to implement a configurable 8-bit serial in parallel out (SIPO) or parallel in serial out (PISO) shift register.Design Files The design files are available in the Quartus II Projects section on the
Design Examples page of the Altera web site:
https://www.wendangku.net/doc/e81441986.html,/support/examples/quartus/quartus.html Select the “Examples for lpm_shiftreg Megafunction User Guide” link from the examples page to download the design files.
Example 1In this example, you perform the following tasks:
■
Create an 8-bit shift register using the lpm_shiftreg megafunction and the MegaWizard Plug-in Manager ■
Implement design and assign the EP1S10F780C6 device to the project ■Compile and simulate the design
Generate a Configurable 8-Bit SIPO or PISO Shift Register
1.In the Quartus II software, open the
lpm_shiftreg_DesignExample_ex1.qar project.
2.
On the Tools menu, click MegaWizard Plug-In Manager . Page 1 of the MegaWizard Plug-In Manager appears (Figure 2–6).