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LTC2242IUP-12中文资料

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LTC2242-12

224212f

CO VERTER CHARACTERISTICS

ORDER PART NUMBER UP PART MARKING*LTC2242CUP-12LTC2242IUP-12

PACKAGE/ORDER I FOR ATIO

W The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T A = 25°C. (Note 4)

*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.

Supply Voltage (V DD )..............................................2.8V Digital Output Ground Voltage (OGND).......–0.3V to 1V Analog Input Voltage (Note 3).....–0.3V to (V DD + 0.3V)Digital Input Voltage ....................–0.3V to (V DD + 0.3V)Digital Output Voltage...............–0.3V to (OV DD + 0.3V)

ABSOLUTE AXI U RATI GS

W W W

U OV DD = V DD (Notes 1, 2)

TOP VIEW

UP PACKAGE

64-LEAD (9mm × 9mm) PLASTIC QFN

EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB

T JMAX = 150°C, θJA = 20°C/W

A IN + 1A IN + 2A IN – 3A IN – 4REFHA 5REFHA 6REFL

B 7REFLB 8REFHB 9REFHB 10REFLA 11REFLA 12V DD 13V DD 14V DD 15GND 16

48 D9+/DA6 47 D9–/DA5 46 D8+/DA4 45 D8–/DA344 D7+/DA2 43 D7–/DA142 OV DD 41 OGND 40 D6+/DA0 39 D6–/CLKOUTA 38 D5+/CLKOUTB 37 D5–/OFB

36 CLKOUT +/DB1135 CLKOUT –/DB1034 OV DD 33 OGND

64 G N D 63 V D D

62 V D D

61 G N D 60 V C M

59 S E N S E 58 M O D E 57 L V D S 56 O F +/O F A 55 O F –/D A 1154 D 11+/D A 1053 D 11–/D A 952 D 10+/D A 851 D 10–/D A 7

50 O G N D 49 O V D D

E N C + 17E N C – 18

S H D N 19O E 20D O –/D B 0 21D O +/D B 1 22D 1–/D B 2 23D 1+/D B 3 24

O G N D 25O V D D 26D 2–/D B 4 27D 2+/D B 5 28D 3–/D B 6 29D 3+/D B 7 30D 4–/D B 8 31D 4+/D B 9 32

Power Dissipation............................................1500mW Operating Temperature Range

LTC2242C-12..........................................0°C to 70°C LTC2242I-12.......................................–40°C to 85°C Storage Temperature Range..................–65°C to 150°C

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: https://www.wendangku.net/doc/ea2043812.html,/leadfree/

LTC2242UP-12LTC2242UP-12

PARAMETER

CONDITIONS

MIN TYP MAX UNITS Resolution (No Missing Codes)●

12Bits Integral Linearity Error Differential Analog Input (Note 5)●–2.7±1 2.7LSB Differential Linearity Error Differential Analog Input ●–1±0.41LSB Offset Error (Note 6)●–17±517mV Gain Error External Reference ●

–3.2

±0.7 3.2

%FS Offset Drift ±10μV/C Full-Scale Drift Internal Reference ±60ppm/C External Reference ±45ppm/C Transition Noise

SENSE = 1V

0.74

LSB RMS

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LTC2242-12

224212f

SYMBOL PARAMETER

CONDITIONS MIN TYP MAX UNITS SNR

Signal-to-Noise Ratio (Note 10)

10MHz Input 65.4dB 70MHz Input ●

63.4

65.3dB 140MHz Input 65.3dB 240MHz Input

65.1dB SFDR

Spurious Free Dynamic Range 10MHz Input 78

dB 2nd or 3rd Harmonic 70MHz Input ●6575dB (Note 11)

140MHz Input 74dB 240MHz Input

73dB Spurious Free Dynamic Range 10MHz Input 87

dB 4th Harmonic or Higher 70MHz Input ●7387dB (Note 11)

140MHz Input 87dB 240MHz Input

87dB S/(N+D)

Signal-to-Noise Plus 10MHz Input 65.3

dB Distortion Ratio 70MHz Input ●61.865.1dB (Note 12)

140MHz Input 64.8dB 240MHz Input

64.5dB IMD

Intermodulation Distortion

f IN1 = 135MHz, f IN2 = 140MHz

dBc

A ALOG I PUT

The ● denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T A = 25°C. (Note 4)

DY A IC ACCURACY

W The ● denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T A = 25°C. A IN = –1dBFS. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

V IN Analog Input Range (A IN + – A IN –)

2.375V < V DD < 2.625V (Note 7)●±0.5 to ±1V V IN, CM Analog Input Common Mode (A IN + + A IN –)/2Differential Input (Note 7)● 1.2 1.25

1.3V I IN Analog Input Leakage Current 0 < A IN +, A IN – < V DD ●–11μA I SENSE SENSE Input Leakage

0V < SENSE < 1V

●

–1

μA I MODE MODE Pin Pull-Down Current to GND 7μA I LVDS LVDS Pin Pull-Down Current to GND 7μA t AP Sample and Hold Acquisition Delay Time 0.4ns t JITTER

Sample and Hold Acquisition Delay Time Jitter 95

fs RMS Full Power Bandwidth

Figure 8 Test Circuit

1200

MHz

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LTC2242-12

224212f

TYPICAL PERFOR A CE CHARACTERISTICS

U W

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V DD , they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V DD without latchup.Note 4: V DD = 2.5V, f SAMPLE = 250MHz, LVDS outputs, differential ENC +/ENC – = 2V P-P sine wave, input range = 2V P-P with differential drive, unless otherwise noted.

Note 5: Integral nonlinearity is defined as the deviation of a code from a “best straight line” fit to the transfer curve. The deviation is measured from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s complement output mode.

Note 7: Guaranteed by design, not subject to test.Note 8: Recommended operating conditions.

Note 9: V DD = 2.5V, f SAMPLE = 250MHz, differential ENC +/ENC – = 2V P-P sine wave, input range = 1V P-P with differential drive, output C LOAD = 5pF.Note 10: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.3dB lower.

Note 11: SFDR minimum values are for LVDS mode. Typical values are for both LVDS and CMOS modes.

Note 12: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.3dB lower.

ELECTRICAL CHARACTERISTICS

Integral Nonlinearity

Differential Nonlinearity

8192 Point FFT, f IN = 5MHz,–1dB, 2V Range, LVDS Mode

(T A = 25°C unless otherwise noted, Note 4)

OUTPUT CODE

I N L (L S B )

00.51.04096

224212 G01

–0.5–1.0–2.0

1024

20483072

–1.52.01.5OUTPUT CODE

0–1.0

D N L (L S B )

–0.8

–0.4–0.201.00.41024

2048224212 G02

–0.60.60.80.230724096

FREQUENCY (MHz)

0A M P L I T U D E (d B )

–80–20–10020

406080100224212 G03

–100–40–60–90–30–110

–50–70120

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LTC2242-12

8192 Point FFT, f IN = 500MHz,–1dB, 1V Range, LVDS Mode

8192 Point FFT, f IN = 1GHz,–1dB, 1V Range, LVDS Mode

8192 Point 2-Tone FFT,f IN = 135MHz and 140MHz,–1dB, 2V Range, LVDS Mode

SNR vs Input Frequency, –1dB,LVDS Mode

SFDR (HD2 and HD3) vs Input Frequency, –1dB, LVDS Mode

SFDR (HD4+) vs Input Frequency,–1dB, LVDS Mode

INPUT FREQUENCY (MHz)

0600700800900224212 G10

1002003004005001000

1V RANGE

2V RANGE

INPUT FREQUENCY (MHz)

800224212 G11

2001004003006007009005001000

1V RANGE

2V RANGE

INPUT FREQUENCY (MHz)

100500700224212 G12

4009001000

2003006008001V RANGE

2V RANGE

FREQUENCY (MHz)

406080100

224212 G04

120

FREQUENCY (MHz)

406080100

224212 G05

120

FREQUENCY (MHz)

406080100

224212 G06

120

FREQUENCY (MHz)

406080100

224212 G07

120

FREQUENCY (MHz)

406080100

224212 G08

120

FREQUENCY (MHz)

406080100

224212 G09

120

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LTC2242-12

SAMPLE RATE (Msps)

0150

SFDR

SNR

250

224212 G13

50100200300

I VDD vs Sample Rate, 5MHz Sine

Wave Input, –1dB

I OVDD vs Sample Rate, 5MHz Sine

Wave Input, –1dB

SAMPLE RATE (Msps)

(

)

250

260

270

150

240

230

220

50100

280

290

300

2V RANGE

INPUT LEVEL (dBFS)

–60–40–20–10

224212 G14

–50–30

dBFS

dBc

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LTC2242-12

224212f

(CMOS Mode)

A IN + (Pins 1, 2): Positive Differential Analog Input.A IN – (Pins 3, 4): Negative Differential Analog Input.REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.

REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,6 with 0.1μF ceramic chip capacitor. Do not connect to Pins 11, 12.

REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not connect to Pins 5, 6.

REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.

V DD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1μF ceramic chip capacitors.GND (Pins 16, 61, 64): ADC Power Ground.

ENC + (Pin 17): Encode Input. Conversion starts on the positive edge.

ENC – (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1μF ceramic for single-ended ENCODE signal.

SHDN (Pin 19): Shutdown Mode Selection Pin. Connect-ing SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to V DD results in normal operation with the outputs at high impedance. Connecting SHDN to V DD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to V DD and OE to V DD results in sleep mode with the outputs at high impedance.OE (Pin 20): Output E nable Pin. Refer to SHDN pin function.

DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32,35, 36): Digital Outputs, B Bus. DB11 is the MSB. At high impedance in full rate CMOS mode.

OGND (Pins 25, 33, 41, 50): Output Driver Ground.OV DD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.

U U U

PI FU CTIO S

OFB (Pin 37): Over/Under Flow Output for B Bus. High when an over or under flow has occurred. At high imped-ance in full rate CMOS mode.

CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux mode with interleaved update, latch B bus data on the falling edge of CLKOUTB. In demux mode with simulta-neous update, latch B bus data on the rising edge of CLKOUTB. This pin does not become high impedance in full rate CMOS mode.

CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A bus data on the falling edge of CLKOUTA.

DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53,54, 55): Digital Outputs, A Bus. DA11 is the MSB.

OFA (Pin 56): Over/Under Flow Output for A Bus. High when an over or under flow has occurred.

LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3V DD selects demux CMOS mode with simulta-neous update. Connecting LVDS to 2/3V DD selects demux CMOS mode with interleaved update. Connecting LVDS to V DD selects LVDS mode.

MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3V DD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3V DD selects 2’s complement output format and turns the clock duty cycle stabilizer on.Connecting MODE to V DD selects 2’s complement output format and turns the clock duty cycle stabilizer off.

SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to V CM selects the internal reference and a ±0.5V input range. Connecting SENSE to V DD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SE NSE selects an input range of ±V SENSE . ±1V is the largest valid input range.

V CM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor.GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.

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LTC2242-12

224212f

U U U

PI FU CTIO S

(LVDS Mode)

AIN + (Pins 1, 2): Positive Differential Analog Input.AIN – (Pins 3, 4): Negative Differential Analog Input.REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.

REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,6 with 0.1μF ceramic chip capacitor. Do not connect to Pins 11, 12.

REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not connect to Pins 5, 6.

REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.

V DD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1μF ceramic chip capacitors.GND (Pins 16, 61, 64): ADC Power Ground.

ENC + (Pin 17): Encode Input. Conversion starts on the positive edge.

ENC – (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1μF ceramic for single-ended ENCODE signal.

D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29,30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52,53, 54): LVDS Digital Outputs. All LVDS outputs require differential 100? termination resistors at the LVDS re-ceiver. D11–/D11+ is the MSB.

OGND (Pins 25, 33, 41, 50): Output Driver Ground.OV DD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.

CLKOUT –/CLKOUT + (Pins 35 to 36): LVDS Data Valid Output. Latch data on rising edge of CLKOUT –, falling edge of CLKOUT +.

OF –/OF + (Pins 55 to 56): LVDS Over/Under Flow Output.High when an over or under flow has occurred.

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LTC2242-12

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LTC2242-12

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LTC2242-12

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LTC2242-12

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LTC2242-12

224212f

Digital Output Modes

The LTC2242-12 can operate in several digital output modes: LVDS, CMOS running at full speed, and CMOS demultiplexed onto two buses, each of which runs at half speed. In the demultiplexed CMOS modes the two buses (referred to as bus A and bus B) can either be updated on alternate clock cycles (interleaved mode) or simultaneously (simultaneous mode). For details on the clock timing, refer to the timing diagrams.

The LVDS pin selects which digital output mode the part uses. This pin has a four-level logic input which should be connected to GND, 1/3V DD , 2/3V DD or V DD . An external resistor divider can be used to set the 1/3V DD or 2/3V DD logic values. Table 2 shows the logic states for the LVDS pin.

APPLICATIO S I FOR ATIO

W U

U Digital Output Buffers (CMOS Modes)

Figure 13a shows an equivalent circuit for a single output buffer in the CMOS output mode. Each buffer is powered by OV DD and OGND, which are isolated from the ADC power and ground. The additional N-channel transis-tor in the output driver allows operation down to voltages as low as 0.5V. The internal resistor in series with the output makes the output appear as 50? to external circuitry and may eliminate the need for external damping resistors.

As with all high speed/high resolution converters, the digi-tal output loading can affect the performance. The digital outputs of the LTC2242-12 should drive a minimal capaci-tive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an 74VCX245 CMOS latch.For full speed operation the capacitive load should be kept under 10pF.

Lower OV DD voltages will also help reduce interference from the digital outputs.

Digital Output Buffers (LVDS Mode)

Figure 13b shows an equivalent circuit for a differential output pair in the LVDS output mode. A 3.5mA current is steered from OUT + to OUT – or vice versa which creates a ±350mV differential voltage across the 100? termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.25V. For proper operation each LVDS output pair needs an external 100?termination resistor, even if the signal is not used (such as OF +/OF – or CLKOUT +/CLKOUT –). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length.

Table 1. Output Codes vs Input Voltage

A IN + – A IN –D11 – D0D11 – D0

(2V RANGE)OF (OFFSET BINARY)(2’s COMPLEMENT)>+1.000000V 11111 1111 11110111 1111 1111+0.999512V 01111 1111 11110111 1111 1111+0.999024V 01111 1111 11100111 1111 1110+0.000488V 01000 0000 00010000 0000 0001 0.000000V 01000 0000 00000000 0000 0000–0.000488V 00111 1111 11111111 1111 1111–0.000976V 00111 1111 11101111 1111 1110–0.999512V 00000 0000 00011000 0000 0001–1.000000V 00000 0000 00001000 0000 0000<–1.000000V

0000 0000 0000

1000 0000 0000

Table 2. LVDS Pin Function

LVDS DIGITAL OUTPUT MODE GND Full-Rate CMOS

1/3V DD Demultiplexed CMOS, Simultaneous Update 2/3V DD Demultiplexed CMOS, Interleaved Update V DD

LVDS

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