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CALVC164245IDLREP中文资料

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FEATURES

DGG OR DL PACKAGE

(TOP VIEW)

123456789101112131415161718192021222324

4847464544434241403938373635343332313029282726251DIR 1B11B2GND 1B31B4

(3.3 V, 5 V) V CCB

1B51B6GND 1B71B82B12B2GND 2B32B4

(3.3 V, 5 V) V CCB

2B52B6GND 2B72B82DIR

1OE 1A11A2GND 1A31A4

V CCA (2.5 V, 3.3 V)1A51A6GND 1A71A82A12A2GND 2A32A4

V CCA (2.5 V, 3.3 V)2A52A6GND 2A72A82OE

DESCRIPTION/ORDERING INFORMATION

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

Controlled Baseline

–One Assembly/Test Site,One Fabrication Site

?Enhanced Diminishing Manufacturing Sources (DMS)Support

?Enhanced Product-Change Notification ?Qualification Pedigree (1)

?Member of the Texas Instruments Widebus?Family

?Max t pd of 5.8ns at 3.3V

?±24-mA Output Drive at 3.3V

?Control Inputs V IH /V IL Levels Are Referenced to V CCA Voltage

Latch-Up Performance Exceeds 250mA Per JESD 17

(1)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an

extended temperature range.This includes,but is not limited to,Highly Accelerated Stress Test (HAST)or biased 85/85,temperature cycle,autoclave or unbiased HAST,

electromigration,bond intermetallic life,and mold compound life.Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

This 16-bit (dual-octal)noninverting bus transceiver contains two separate supply rails.B port has V CCB ,which is set to operate at 3.3V and 5V.A port has V CCA ,which is set to operate at 2.5V and 3.3V.This allows for translation from a 2.5-V to a 3.3-V environment,and vice versa,or from a 3.3-V to a 5-V environment,and vice versa.

The SN74ALVC164245is designed for asynchronous communication between data buses.The control circuitry (1DIR,2DIR,1OE,and 2OE)is powered by V CCA .

To ensure the high-impedance state during power up or power down,the output-enable (OE)input should be tied to V CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

T A

PACKAGE (1)

ORDERABLE PART NUMBER TOP-SIDE MARKING SSOP –DL

Reel of 1000CALVC164245IDLREP ALVC164245TSSOP –DGG Reel of 2000CALVC164245IDGGREP ALVC164245–40°C to 85°C

VFBGA –GQL

CALVC164245IGQLREP Reel of 1000VC4245EP VFBGA –ZQL (Pb-free)

CALVC164245IZQLREP –55°C to 125°C TSSOP –DGG

Reel of 2000

CALVC164245MDGGREP

C164245MEP

(1)

Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at https://www.wendangku.net/doc/e33179011.html,/sc/package.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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GQL OR ZQL PACKAGE

(TOP VIEW)J H G F E D C B A 2

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

TERMINAL ASSIGNMENTS (1)

23456A 1DIR NC NC NC NC 1OE B 1B21B1GND GND 1A11A2C 1B41B3V CCB V CCA 1A31A4D 1B61B5GND

GND

1A51A6E 1B81B71A71A8F 2B12B22A22A1G 2B32B4GND GND 2A42A3H 2B52B6V CCB V CCA 2A62A5J 2B72B8GND GND 2A82A7K

2DIR

2OE

(1)NC –No internal connection

FUNCTION TABLE (EACH 8-BIT SECTION)

INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus

Isolation

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To Seven Other Channels

1DIR

1A1

1B1

1OE

To Seven Other Channels

2DIR

2A1

2B1

2OE

Pin numbers shown are for the DGG and DL packages.

Absolute Maximum Ratings (1)

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

LOGIC DIAGRAM (POSITIVE LOGIC)

over operating free-air temperature range for V CCB at 5V and V CCA at 3.3V (unless otherwise noted)

MIN

MAX UNIT V CCA –0.5 4.6Supply voltage range

V CCB –0.56Except I/O ports (2)

–0.5

V I Input voltage range I/O port A (3)–0.5V CCA +0.5V I/O port B (2)–0.5V CCB +0.5

I IK Input clamp current V I <0–50mA I OK Output clamp current V O <0

–50mA I O

Continuous output current

±50mA Continuous current through each V CC or GND

±100mA DGG package

70θJA Package thermal impedance (4)DL package 63°C/W GQL/ZQL package

42T stg Storage temperature range

–65

150

°C (1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)This value is limited to 6V maximum.(3)This value is limited to 4.6V maximum.

(4)

The package thermal impedance is calculated in accordance with JESD 51-7.

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Recommended Operating Conditions (1)

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

for V CCB at 3.3V and 5V

MIN

MAX UNIT V CCB Supply voltage 3 5.5

V V IH High-level input voltage 2

V V CCB =3V to 3.6V 0.7V IL Low-level input voltage V V CCB =4.5V to 5.5V

0.8V IB Input voltage 0V CCB V V OB Output voltage

0V CCB V I OH High-level output current –24mA I OL Low-level output current 24mA ?t/?v Input transition rise or fall rate 10ns/V CALVC16245I –4085T A Operating free-air temperature

°C

CALVC16245M

–55

125(1)

All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.

for V CCA at 2.5V and 3.3V

MIN

MAX UNIT V CCA Supply voltage 2.3 3.6

V V CCA =2.3V to 2.7V 1.7V IH High-level input voltage V V CCA =3V to 3.6V 2

V CCA =2.3V to 2.7V 0.7V IL Low-level input voltage V V CCA =3V to 3.6V

0.8V IA Input voltage 0V CCA V V OA Output voltage

0V CCA V V CCA =2.3V –18I OH High-level output current mA V CCA =3V –24V CCA =2.3V 18I OL Low-level output current mA V CCA =3V

24?t/?v Input transition rise or fall rate 10ns/V CALVC16245I –4085T A Operating free-air temperature

°C

CALVC16245M

–55

125(1)

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Electrical Characteristics

SN74ALVC164245-EP 16-BIT2.5-V TO3.3-V/3.3-V TO5-V LEVEL-SHIFTING TRANSCEIVER

WITH3-STATE OUTPUTS

SCAS774A–JUNE2004–REVISED SEPTEMBER2005

over recommended operating free-air temperature range for V

CCA =2.7V to3.6V and V

CCB

=4.5V to5.5V

(unless otherwise noted)

CALVC164245I CALVC164245M PARAMETER TEST CONDITIONS V CCA V CCB UNIT

MIN TYP(1)MAX MIN TYP(1)MAX

2.7V to

I OH=–100μA V CC–0.2V CC–0.2

3.6V

2.7V 2.2 2.2

B to A

I OH=–12mA

3V 2.4 2.4

I OH=–24mA3V22

V OH V

4.5V 4.3 4.3

I OL=100μA

5.5V 5.3 5.3

A to B

4.5V 3.7 3.7

I OL=24mA

5.5V 4.7 4.7

2.7V to

I OL=100μA0.20.2

3.6V

B to A

I OL=12mA 2.7V0.40.4

I OL=24mA3V0.550.55

V OL V

4.5V to

I OL=100μA0.20.2

5.5V

A to B

4.5V to

I OL=24mA0.550.55

5.5V

Control

I I V I=V CCA/V CCB or GND 3.6V 5.5V±5±5μA

inputs

A or B

I OZ(2)V O=V CCA/V CCB or GND 3.6V 5.5V±10±10μA

port

V I=V CCA/V CCB or GND,

I CC 5.5V 5.5V4040μA

I O=0

One input at V CCA/V CCB–0.6V,3V to 4.5V to

?I CC(3)750750μA Other inputs at V CCA/V CCB or GND 3.6V 5.5V

Control

C i V I=V CCA/V CCB or GN

D 3.3V5V 6.5 6.5pF

inputs

A or B

C io V O=V CCA/V CCB or GN

D 3.3V 3.3V8.58.5pF

port

(1)All typical values are at V CCA=3.3V and V CCB=5V,T A=25°C.

(2)For I/O ports,the parameter I OZ includes the input leakage current.

(3)This is the increase in supply current for each input that is at one of the specified TTL voltage levels,rather than at0or the associated

V CC.

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Electrical Characteristics

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

over recommended operating free-air temperature range for V CCA =2.3V to 2.7V and V CCB =3V to 3.6V (unless otherwise noted)

CALVC164245I

CALVC164245M

PARAMETER

TEST CONDITIONS

V CCA V CCB UNIT

MIN MAX MIN MAX

I OH =–100μA

2.3V to 2.7V

3V to 3.6V V CCA –0.2

V CCA –0.2

B to A

I OH =–8mA 2.3V 3V to 3.6V 1.7 1.7V OH

I OH =–12mA 2.7V 3V to 3.6V 1.8

1.8

I OL =100μA 2.3V to 2.7V 3V to 3.6V

V CCB –0.2

A to

B I OL =18mA 2.3V to 2.7V 3V 2.2

2.2

I OL =100μA 2.3V to 2.7V

3V to 3.6V 0.20.2B to A

I OL =12mA 2.3V 3V to 3.6V 0.60.6V OL

V I OL =100μA 2.3V to 2.7V

3V to 3.6V

0.20.2A to B

I OL =18mA

2.3V 3V 0.550.55I I

Control V I =V CCA /V CCB or GND 2.3V to 2.7V 3V to 3.6V ±5±5μA inputs

I OZ (1)A or B

V O =V CCA /V CCB or GND 2.3V to 2.7V 3V to 3.6V ±10±10μA port V I =V CCA /V CCB or GND,I CC 2.3V to 2.7V 3V to 3.6V 2040μA I O =0

One input at V CCA /V CCB –0.6V,?I CC (2) 2.3V to 2.7V

3V to 3.6V

750

μA Other inputs at V CCA /V CCB or GND

(1)For I/O ports,the parameter I OZ includes the input leakage current.

(2)

This is the increase in supply current for each input that is at one of the specified TTL voltage levels,rather than at 0or the associated V CC .

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Switching Characteristics

Operating Characteristics

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1through Figure 4)

CALVC16245I

V CCB =3.3V V CCB =5V ±0.5V ±0.3V FROM TO PARAMETER

UNIT

(INPUT)

(OUTPUT)

V CCA =2.5V V CCA =3.3V V CCA =2.7V ±0.2V ±0.3V MIN

MAX MIN

MAX MIN MAX A B 7.6 5.91 5.8t pd ns B A 7.6 6.7 1.2 5.8t en OE B 11.59.318.9ns t dis OE B 10.59.2 2.19.5ns t en OE A 12.310.229.1ns t dis

9.3

2.9

8.6

ns over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1through Figure 4)

CALVC16245M

V CCB =3.3V V CCB =5V ±0.5V ±0.3V FROM TO PARAMETER

UNIT

(INPUT)

(OUTPUT)

V CCA =2.5V V CCA =3.3V V CCA =2.7V ±0.2V ±0.3V MIN

MAX MIN

MAX MIN MAX A B 8.6 6.91 6.8t pd ns B A 8.67.7 1.2 6.8t en OE B 12.510.319.9ns t dis OE B 11.510.2 2.110.5ns t en OE A 14.511.2210.1ns t dis

11.3

2.9

10.6

ns T A =25°C

V CCB =3.3V

V CCB =5V PARAMETER

TEST CONDITIONS

V CCA =2.5V

V CCA =3.3V

UNIT

TYP

TYP Outputs enabled (B)

5556C L =50pF,f =10MHz Outputs disabled (B)276C pd

Power dissipation capacitance

pF Outputs enabled (A)11856C L =50pF,

f =10MHz

Outputs disabled (A)

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Power-Up Considerations (1)

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

TI level-translation devices offer an opportunity for successful mixed-voltage signal design.A proper power-up sequence always should be followed to avoid excessive supply current,bus contention,oscillations,or other anomalies caused by improperly biased device pins.To guard against such power-up problems,take these precautions:

1.Connect ground before any supply voltage is applied.

2.Power up the control side of the device (V CCA for all four of these devices).

3.Tie OE to V CCA with a pullup resistor so that it ramps with V CCA .

4.Depending on the direction of the data path,DIR can be high or low.If DIR high is needed (A data to B bus),ramp it with V CCA .Otherwise,keep DIR low.

(1)

Refer to the TI application report,Texas Instruments Voltage-Level-Translation Devices ,literature number SCEA021.

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PARAMETER MEASUREMENT INFORMATION V OHB V OLB

C L LOA

D CIRCUIT

CCB = 6 V

Open

Output Control (low-level enabling)

Output Waveform 1S1 at 6 V (see Note B)Output Waveform 2S1 at GND (see Note B)

0 V

V CCA

V CCB

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES

t pd t PLZ /t PZL t PHZ /t PZH

Open V CCB = 6 V GND

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z O = 50 ?, t r ≤2 ns, t f ≤2 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

V CCA =2.5V ±0.2V to V CCB =3.3V ±0.3V

Figure 1.Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION

V OHA

V OLA From Output Under Test

C L LOA

D CIRCUIT

Open Output Control (low-level enabling)

Output Waveform 1S1 at 2 × V CCA (see Note B)

Output Waveform 2S1 at GND (see Note B)0 V

0 V

2.7 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES

t pd t PLZ /t PZL t PHZ /t PZH

Open 2 × V CCA GND

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Input

Output

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

× V CCA

V CCA

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

V CCB =3.3V ±0.3V to V CCA =2.5V ±0.2V

Figure 2.Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION

V OH V OL

C L LOA

D CIRCUIT

V CCB

Open

Output Control (low-level enabling)

Output Waveform 1S1 at 2 V CCB

(see Note B)

Output Waveform 2S1 at GND (see Note B)0 V

0 V

2.7 V

≈V CCB

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES

t pd t PLZ /t PZL t PHZ /t PZH

Open 2 V CCB GND

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2.5 ns, t f ≤ 2.5 ns.

D.The outputs are measured one at a time, with one transition per measurement.

E.t PLZ and t PHZ are the same as t dis .

F.t PZL and t PZH are the same as t en .

G.t PLH and t PHL are the same as t pd .

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

V CCA =3.3V ±0.3V to V CCB =5V ±0.5V

Figure 3.Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION V OHA V OLA

C L LOA

D CIRCUIT

= 6 V

Open

Output Control (low-level enabling)

Output Waveform 1S1 at 6 V (see Note B)

Output Waveform 2S1 at GND (see Note B)

0 V

3 V

≈3 V

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES

t pd t PLZ /t PZL t PHZ /t PZH

Open V CCA = 6 V GND

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2.5 ns, t f ≤ 2.5 ns.

D.The outputs are measured one at a time, with one transition per measurement.

E.t PLZ and t PHZ are the same as t dis .

F.t PZL and t PZH are the same as t en .

G.t PLH and t PHL are the same as t pd .

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

V CCB =5V ±0.5V to V CCA =2.7V and 3.3V ±0.3V

Figure 4.Load Circuit and Voltage Waveforms

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Tj ? Continuous – °C

02468101214120

125130135140145150155160

Y e a r s E s t i m a t e d L I f e

SN74ALVC164245-EP

16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS774A–JUNE 2004–REVISED SEPTEMBER 2005

74ALVC164245MDGG*EP

Estimated Device Life at Elevated Temperatures Electromigration

and Wirebond Voiding Fail Modes

A.Silicon operating life design goal is 10years at 105°C junction temperature.

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PACKAGING INFORMATION

Orderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)

Lead/Ball Finish MSL Peak Temp (3)CALVC164245IDGGREP ACTIVE TSSOP DGG 482000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CALVC164245IDLREP ACTIVE SSOP DL 481000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CALVC164245MDGGREP

ACTIVE TSSOP DGG 482000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM V62/05612-01XE ACTIVE SSOP DL 481000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM V62/05612-01YE ACTIVE TSSOP DGG 482000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM V62/05612-02YE

ACTIVE

TSSOP

DGG

2000Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

(1)

The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.

(2)

Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check https://www.wendangku.net/doc/e33179011.html,/productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.

Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)

(3)

MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information

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OTHER QUALIFIED VERSIONS OF SN74ALVC164245-EP :?Catalog:SN74ALVC164245

NOTE:Qualified Version Definitions:

?Catalog -TI's standard catalog product

PACKAGE OPTION ADDENDUM

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18-Sep-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Type Package Drawing

Pins SPQ

Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)

P1(mm)W (mm)Pin1Quadrant CALVC164245IDGGREP TSSOP DGG 482000330.024.48.615.8 1.812.024.0Q1CALVC164245IDLREP

SSOP

DL 481000330.032.411.3516.2 3.116.032.0Q1CALVC164245MDGGREP TSSOP

DGG

2000

330.0

24.4

8.6

15.8

1.8

12.0

24.0

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CALVC164245IDGGREP TSSOP DGG482000346.0346.041.0 CALVC164245IDLREP SSOP DL481000346.0346.049.0 CALVC164245MDGGREP TSSOP DGG482000346.0346.041.0

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