文档库 最新最全的文档下载
当前位置:文档库 › CAT25C256Y20A-1.8T3中文资料

CAT25C256Y20A-1.8T3中文资料

CAT25C256Y20A-1.8T3中文资料
CAT25C256Y20A-1.8T3中文资料

? 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1

Document No. 1018, Rev. I

2

Document No. 1018, Rev. I

3Document No. 1018, Rev. I

4

Document No. 1018, Rev. I

5Document No. 1018, Rev. I

6

Document No. 1018, Rev. I

Protected Unprotected Status WPEN WP WEL Blocks Blocks Register 0X 0Protected Protected Protected 0X 1Protected Writable Writable 1Low 0Protected Protected Protected 1Low 1Protected Writable Protected X High 0Protected Protected Protected X

High

1

Protected

Writable

Writable

WRITE PROTECT ENABLE OPERATION

WP : Write Protect

WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high.When WP is tied low and the WPEN bit in the status register is set to “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPE N bit is set to 0.

HOLD : Hold

The HOLD pin is used to pause transmission to the CAT25C128/256 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to V cc or tied to V cc through a resistor. Figure 9 illustrates hold timing sequence.

STATUS REGISTER

The Status Register indicates the status of the device.The RDY (Ready) bit indicates whether the CAT25C128/256 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only.

The WEL (Write Enable) bit indicates the status of the write enable latch . When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WE L bit can only be set by the WRE N instruction and can be reset by the WRDI instruction.The BP0 and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected the user may only read from the protected portion of the array. These bits are non-volatile.

Status Register Bits Array Address

Protection BP1BP0Protected

00None

No Protection 0125C128: 3000-3FFF Quarter Array Protection 25C256: 6000-7FFF 1025C128: 2000-3FFF Half Array Protection 25C256: 4000-7FFF 1

1

25C128: 0000-3FFF Full Array Protection

25C256: 0000-7FFF

BLOCK PROTECTION BITS

76543210WPEN

X

X

X

BP1

BP0

WEL

RDY

STATUS REGISTER

The WPE N (Write Protect E nable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect fea-ture. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register (including the block protect bits and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write pro-tected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero.

DEVICE OPERATION

Write Enable and Disable

The CAT25C128/256 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when V cc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes.

READ Sequence

The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C128/256, followed by the 16-bit address(the three Most Significant Bit is don’t care for 25C256 and four most significant bits are don't care for 25C128).

After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address (7FFFh for 25C256 and 3FFFh for 25C128) is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The readoperation is terminated by pulling the CS high.

SK

SI CS SO 00000110

HIGH IMPEDANCE

Figure 2. WREN Instruction Timing SK

SI CS SO 00000100

HIGH IMPEDANCE

Note: Dashed Line= mode (1, 1) — ———

Figure 3. WRDI Instruction Timing

7Document No. 1018, Rev. I

8

Document No. 1018, Rev. I

9Document No. 1018, Rev. I

address counter reaches the end of the page and clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. The CAT25C128/256 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence.To write to the status register, the WRSR instruction should be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be written using the WRSR instruction.Figure 7 illustrates the sequence of writing to status register.

The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction.

Page Write

The CAT25C128/256 features page write capability.After the first initial byte the host may continue to write up to 64 bytes of data to the CAT25C128/256. After each byte of data is received, six lower order address bits are internally incremented by one; the high order bits of address will remain constant. The only restriction is that the 64 bytes must reside on the same page. If the SK

SI SO

00000010ADDRESS D7D6D5D4D3D2D1D0

12345678212223242526272829303

CS

OPCODE

DATA IN

HIGH IMPEDANCE

Note: Dashed Line= mode (1, 1) — ———

Figure 6. Write Instruction Timing

Figure 7. WRSR Timing

1234567810911121314SCK

SI MSB

HIGH IMPEDANCE

DATA IN

15

SO

CS

7

6543210

00000001OPCODE

Note: Dashed Line= mode (1, 1) — ———

Figure 8. Page Write Instruction Timing

SK

SI SO

00000010ADDRESS

Data Byte 10

1234567821222324-3132-39

Data Byte 2Data Byte 3Data Byte N

CS

OPCODE

7..1

024+(N-1)x8-1..24+(N-1)x824+Nx8-1

DATA IN

HIGH IMPEDANCE

Note: Dashed Line= mode (1, 1) — ———

10

Document No. 1018, Rev. I

11Document No. 1018, Rev. I

相关文档