R8C-11中文资料
R8C/11 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0034-0160
Rev.1.60
Jan 27, 2006
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing instructions at high speed.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.
1.2 Performance Overview
Table 1.1. lists the performance outline of this MCU.
Table 1.1 Performance outline
Item Performance
CPU Number of basic instructions89 instructions
Minimum instruction execution time50 ns (f(X IN) = 20 MH Z, V CC = 3.0 to 5.5 V)
100 ns (f(X IN) = 10 MH Z, V CC = 2.7 to 5.5 V)
Operating mode Single-chip
Address space1M bytes
Memory capacity See Table 1.2.
Peripheral Port Input/Output: 22 (including LED drive port), Input: 2 function LED drive port I/O port: 8
Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,
Timer Z: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits x 1 channel
(Circuits of input capture and output compare)
Serial Interface?1 channel
Clock synchronous, UART
?1 channel
UART
A/D converter10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer15 bits x 1 (with prescaler)
Interrupt Internal: 11 factors, External: 5 factors,
Software: 4 factors, Priority level: 7 levels
Clock generation circuit 2 circuits
?Main clock generation circuit (Equipped with a built-in
feedback resistor)
?On-chip oscillator (high speed, low speed)
On High-speed on-chip oscillator the frequency adjust-
ment function is usable.
Oscillation stop detection function Main clock oscillation stop detection function
Voltage detection circuit Included
Power on reset circuit Included
Electrical Supply voltage V CC = 3.0 to 5.5 V (f(X IN) = 20 MH Z)
characteristics V CC = 2.7 to 5.5 V (f(X IN) = 10 MH Z)
Power consumption Typ. 9 mA (V CC = 5.0 V, (f(X IN) = 20 MH Z)
Typ. 5 mA (V CC = 3.0 V, (f(X IN) = 10 MH Z)
Typ. 35 μA (V CC = 3.0 V, Wait mode, Peripheral clock off)
Typ. 0.7 μA (V CC = 3.0 V, Stop mode)
Flash memory Program/erase supply voltage V CC = 2.7 to 5.5 V
Program/erase endurance100 times
Operating ambient temperature-20 to 85 °C
-40 to 85 °C (D-version)
Package32-pin plastic mold LQFP
Signal name Pin name I/O type Power supply Vcc,I
input Vss
IVcc IVcc O
Analog power AVcc, AVss I
supply input
Reset input___________
RESET I
CNVss CNVss I
MODE MODE I
Main clock input X IN I
Main clock output X OUT O
_____
INT interrupt input______________
INT0 to INT3I
Key input interrupt__________
KI0 to KI3I
Timer X CNTR0I/O
____________
CNTR0O
Timer Y CNTR1I/O
Timer Z TZ OUT O
Timer C TC IN I
CMP00 to CMP02,O
CMP10 to CMP12
Serial interface CLK0I/O
RxD0, RxD1I
TxD0, TxD10,O
TxD11
Reference voltage V REF I
input
A/D converter AN0 to AN11I
I/O port P00 to P07,I/O
P10 to P17,
P30 to P33, P37,
P45
Input port P46, P47I
Function
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the Vss pin.
This pin is to stabilize internal power supply. Connect this pin to Vss via a capacitor (0.1 μF).
Do not connect to Vcc.
Power supply input pins for A/D converter. Connect the AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a capacitor between pins AVcc and AVss.
Input “L” on this pin resets the MCU.
Connect this pin to Vss via a resistor.
Connect this pin to Vcc via a resistor.
These pins are provided for the main clock generat-ing circuit I/O. Connect a ceramic resonator or a crys-tal oscillator between the X IN and X OUT pins. To use an externally derived clock, input it to the X IN pin and leave the X OUT pin open.
______
INT interrupt input pins.
Key input interrupt pins.
Timer X I/O pin
Timer X output pin
Timer Y I/O pin
Timer Z output pin
Timer C input pin
Timer C output pins
Transfer clock I/O pin.
Serial data input pins.
Serial data output pins.
Reference voltage input pin for A/D converter. Con-nect the V REF pin to Vcc.
Analog input pins for A/D converter
These are 8-bit CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in that port to be directed for input or output individually.
Any port set to input can select whether to use a pull-up resistor or not by program.
P10 to P17 also function as LED drive ports.
Port for input-only
1.6 Pin Description
Table 1.3 shows the pin description Table 1.3 Pin description
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided.
Figure 2.1 CPU Register
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.
The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each.
The U flag of FLG is used to switch between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to “0”.
2.8.3 Zero Flag (Z)
The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.
2.8.4 Sign Flag (S)
The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is set to “1”.
2.8.6 Overflow Flag (O)
The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The
I flag is set to “0” when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
When write to this bit, set to “0”. When read, its content is indeterminate.
R8C/11 Group 3. Memory
3. Memory
Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses 0000016 to FFFFF16.
The internal ROM is allocated lower addresses beginning with address 0FFFF16. For example, a 16-Kbyte internal ROM is allocated addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting address of each interrupt routine.
The internal RAM is allocated higher addresses beginning with address 0040016. For example, a 1-Kbyte internal RAM is allocated addresses 0040016 to 007FF16. The internal RAM is used not only for storing data, but for calling subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 0000016 to 002FF16. The peripheral function control registers are located them. All addresses, which have nothing allocated within the SFR, are re-served area and cannot be accessed by users.
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information
(1)
N O T E S:
1.B l a n k s p a c e s a r e r e s e r v e d.N o a c c e s s i s a l l o w e d.
2.S o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r.
3.O w i n g t o R e s e t i n p u t.
4.I n t h e c a s e o f R E S E T p i n=H r e t a i n i n g.
Table 4.2 SFR Information(2)(1)
X:U n d e f i n e d
N O T E S:
1. B l a n k s p a c e s a r e r e s e r v e d.N o a c c e s s i s a l l o w e d.
Table 4.3 SFR Information(3)(1)
X:U n d e f i n e d
N O T E S:
1.B l a n k s p a c e s a r e r e s e r v e d.N o a c c e s s i s a l l o w e d.
2.W h e n o u t p u t c o m p a r e m o d e(t h e T C C13b i t i n t h e T C C1r e g i s t e r=1)i s s e l e c t e d,t h e v a l u e a f t e r r e s e t i s s e t t o“F F F F16”.
Table 4.4 SFR Information(4)(1)
X:U n d e f i n e d
N O T E S:
1. B l a n k c o l u m n s,010016t o01B216a n d01B816t o02F F16a r e a l l r e s e r v e d.N o a c c e s s i s a l l o w e d.
5. Electrical Characteristics
Table 5.2 Recommended Operating Conditions
1. V CC = AV CC =
2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. The typical values when average output current is 100ms.
3. Hold Vcc=AVcc.
Table 5.3 A/D Conversion Characteristics
1. V CC=AV CC=
2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. If f AD exceeds 10 MHz more, divide the f AD and hold A/D operating clock frequency (?AD) 10 MHz or below.
3. If the AVcc is less than
4.2V, divide the f AD and hold A/D operating clock frequency (?AD) f AD/2 or below.
4. Hold Vcc=Vref.
Figure 5.1 Port P0 to P4 measurement circuit
Table 5.4 Flash Memory Version Electrical Characteristics
N O T E S:
1.R e f e r e n c e d t o V C C1=A V c c=
2.7t o5.5V a t T o p r=0t o60°C u n l e s s o t h e r w i s e s p e c i f i e d.
2.T h e d a t a h o l d t i m e i n c l u d e s t i m e t h a t t h e p o w e r s u p p l y i s o f f o r t h e c l o c k i s n o t s u p p l i e d.
N O T E S:
1.T h e m e a s u r i n g c o n d i t i o n i s V c c=A V c c=
2.7V t o5.5V a n d T o p r=-40°C t o85°C.
2.T h i s s h o w s t h e t i m e u n t i l t h e v o l t a g e d e t e c t i o n i n t e r r u p t r e q u e s t i s g e n e r a t e d s i n c e t h e v o l t a g e p a s s e s V d e t.
3.T h i s s h o w s t h e r e q u i r e d t i m e u n t i l t h e v o l t a g e d e t e c t i o n c i r c u i t o p e r a t e s w h e n s e t t i n g t o"1"a g a i n a f t e r s e t t i n g t h e V C27b i t i n
t h e V C R2r e g i s t e r t o“0”.
Figure 5.2 Time delay from Suspend Request until Erase Suspend
Table 5.6 Reset Circuit Electrical Characteristics (When Using Hardware Reset 2(1, 3))
N O T E S:
1.T h e v o l t a g e d e t e c t i o n c i r c u i t w h i c h i s e m b e d d e d i n a m i c r o c o m p u t e r i s a f a c t o r t o g e n e r a t e t h e h a r d w a r e r e s e t
2.R e f e r t o5.1.2H a r d w a r e
R e s e t2o f H a r d w a r e M a n u a l f o r d e t a i l s.
2.T h i s c o n d i t i o n i s n o t a p p l i c a b l e w h e n u s i n g w i t h V c c≥1.0V.
3.W h e n t u r n i n g p o w e r o n a f t e r t h e e x t e r n a l p o w e r h a s b e e n h e l d b e l o w t h e v a l i d v o l t a g e(V p o r1)f o r g r e a t e r t h a n10s e c o n d s,r e f e r t o T a b l e5.7
R e s e t C i r c u i t E l e c t r i c a l C h a r a c t e r i s t i c s(W h e n N o t U s i n g H a r d w a r e R e s e t2).
4.t w(p o r2)i s t i m e t o h o l d t h e e x t e r n a l p o w e r b e l o w e f f e c t i v e v o l t a g e(V p o r2).
Table 5.7 Reset Circuit Electrical Characteristics (When Not Using Hardware Reset 2)
N O T E S:
1.W h e n n o t u s i n g h a r d w a r e r e s e t2,u s e w i t h V c c≥
2.7V.
2.t w(p o r1)i s t i m e t o h o l d t h e e x t e r n a l p o w e r b e l o w e f f e c t i v e v o l t a g e(V p o r1).
Figure 5.3 Reset Circuit Electrical Characteristics
Table 5.8 High-speed On-Chip Oscillator Circuit Electrical Characteristics
1.T h e m e a s u r i n g c o n d i t i o n i s V c c=A V c c=5.0V a n d T o p r=25°C.
Table 5.9 Power Circuit Timing Characteristics
1.T h e m e a s u r i n g c o n d i t i o n i s V c c=A V c c=
2.7t o5.5V a n d T o p r=25°C.
2.T h i s s h o w s t h e w a i t t i m e u nt i l t h e i n t e r n a l p o w e r s u p p l y g e n e r a t i n g c i r c u i t i s s t a b i l i z e d d u r i n g p o w e r-o n.
3.T h i s s h o w s t h e t i m e u n t i l B C L K s t a r t s f r o m t h e i n t e r r u p t a c k n o w l e d g e m e n t t o c a n c e l s t o p m o d e.
Table 5.10 Electrical Characteristics (1) [Vcc=5V]
N O T E S:
1.R e f e r e n c e d t o V C C=A V C C= 4.2 t o5.5V a t T o p r=-20t o85°C/-40t o85°C,f(X I N)=20M H z u n l e s s o t h e r w i s e s p e c i f i e d.
1. Timer Y is operated with timer mode.
2. Referenced to V CC = AV CC = 4.2 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, f(X IN)=20MHz unless otherwise specified.
Timing requirements (Unless otherwise noted: V CC = 5V, V SS = 0V at Topr = 25 °C) [V CC =5V]
Table 5.12 X IN input ________
Table 5.13 CNTR0 input, CNTR1 input, INT2 input ________
Table 5.14 TCIN input, INT3 input Table 5.15 Serial Interface ________
Table 5.16 External interrupt INT0 input Symbol t C (X IN )t WH (X IN )t WL (X IN )
Parameter
X IN input cycle time
X IN input HIGH pulse width X IN input LOW pulse width
Min.502525Max.–––
Unit ns
ns ns
Standard Symbol t C (CNTR0)t WH (CNTR0)t WL (CNTR0)
Parameter CNTR0 input cycle time
CNTR0 input HIGH pulse width CNTR0 input LOW pulse width
Min.1004040Max.–––
Unit ns
ns ns
Standard Symbol t C (TCIN )t WH (TCIN )t WL (TCIN )
Parameter
TCIN input cycle time
TCIN input HIGH pulse width TCIN input LOW pulse width
Min.400(1)200(2)200(2)Max.–––
Unit ns
ns ns
Standard NOTES:
1. When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source
frequency x 3).
2. When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source
frequency x 1.5).NOTES:________________
1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width
to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.________________
2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width
to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
Symbol t C (CK )t W (CKH )t W (CKL )t d (C-Q )t h (C-Q )t su (D-C )t h (C-D )
Parameter
CLKi input cycle time
CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time
RxDi input setup time RxDi input hold time
Min.200100100–
35
90
Max.–––
Unit ns
ns ns ns ns ns ns
Standard 80–––Symbol t W (INH )t W (INL )
Parameter
________
INT0 input HIGH pulse width ________
INT0 input LOW pulse width
Min.250(1)250(2)Max.––
Unit ns
ns
Standard