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ADUC834

REV. P rC (12 March 2002)

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Preliminary Technical Data ADuC834

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/https://www.wendangku.net/doc/ec5822435.html, Fax: 781/326-8703? Analog Devices, Inc., 2002

PRELIMINARY TECHNICAL DATA

MicroConverter ?, Dual 16-/24- Bit ADCs

with Embedded 62KB FLASH MCU

FEATURES

High Resolution Sigma-Delta ADCs

Two Independent ADCs (16- and 24-Bit Resolution)24-Bit No Missing Codes, Primary ADC

13-Bit p-p Resolution @ 20Hz, 20mV Range 18-Bit p-p Resolution @ 20Hz, 2.56V Range Memory

62Kbytes On-Chip Flash/EE Program Memory 4 KBytes On-Chip Flash/EE Data Memory

Flash/EE, 100Yr Retention, 100Kcycles Endurance In Circuit Serial Download

High Speed User Bootload (5s Download)2304 Bytes On-Chip Data RAM 8051 Based Core

8051-Compatible Instruction Set (12.58MHz Max)32kHz External Crystal, On-Chip Programmable PLL 11 Interrupt Sources, Two Priority Levels Dual Data Pointer

Extended 11-bit Stack Pointer On-Chip Peripherals

12-Bit Voltage Output DAC Dual 16-Bit Σ? DACs/PWMs On-Chip Temperature Sensor Dual Excitation Current Sources

Time Interval Counter (Real Time Clock/WakeUp Cct)UART and SPI ? Serial I/O

Timer 3 for high speed UART baud rates (incl 115,200)Watchdog Timer (WDT), Power Supply Monitor (PSM)Power

Specified for 3V and 5V Operation

Normal: 3mA @ 3V (Core CLK = 1.5MHz)

Power-Down: 20μA max with wake-up cct running MicroConverter is a registered trademark of Analog Devices, Inc.SPI is a registered trademark of Motorola Inc.

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The ADuC834 is a complete smart transducer front-end, inte-grating two high-resolution sigma delta ADCs, an 8-bit MCU,and program/data Flash/EE Memory on a single chip.The two independent ADCs (Primary and Auxiliary) include a temperature sensor and a PGA (allowing direct measurement of low-level signals). The ADCs with on-chip digital filtering and programmable output data rates are intended for the measure-ment of wide dynamic range, low frequency signals, such as those in weigh scale, strain-gauge, pressure transducer, or temperature measurement applications.

The device operates from a 32 kHz crystal with an on-chip PLL generating a high-frequency clock of 12.58 MHz. This clock is,routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The micro-controller core is an 8052 and therefore 8051 instruction set compatible with 12 core clock periods per machine cycle.62 Kbytes of nonvolatile Flash/EE program memory are provided on-chip. 4 Kbytes of nonvolatile Flash/EE data memory, 256bytes RAM and 2 KBytes of extended RAM are also integrated on-chip.The program memory can be configured as data memory in datalogging applications.

The ADuC834 also incorporates additional analog functionality with a 12-bit DAC, dual current sources, power supply monitor,and a bandgap reference. On-chip digital peripherals include two 16-bit Σ? DACs/PWM, watchdog timer, real time clock (time interval counter), four timers/counters, and two serial I/O ports (UART and SPI).

On-chip factory firmware supports in-circuit serial download (via UART), as well as single-pin emulation mode via the EA pin. A functional block diagram of the ADuC834 is shown above with a more detailed block diagram shown in figure 11 (page 18).The part operates from a 3V or a 5V supply. When operating from 3V the power dissipation for the part is below 10mW. The ADuC834 is housed in a 52-lead MQFP package.

APPLICATIONS

Intelligent Sensors (IEEE1451.2-Compatible)Weigh Scales

Portable Instrumentation Pressure Transducers 4–20mA Transmitters

62 KBY TE S FLA SH/EE PROG RAM ME MO RY

4 K BY TES FLAS H/EE DA TA ME MO RY

2304 BY TES USE R R AM 3 × 16 B IT T IME RS 1 × RE AL TIME CLOCK

4 × PA RA LLE L

PO RTS

8051-BASED M CU W ITH A DD ITION AL

PER IP HE RA LS

POW ER SU PPL Y M ON W ATCH DO G TIME R

UAR T AND SP I SERIAL I/O

ADuC834

PROG.CL OC K DIVIDE R

XTAL2

XTAL1BUF

AG ND

MU X

TE MP SEN SO R

RE FIN+RE FIN ?EX TE RN AL VRE F DE TECT INTE RN AL BAN DG AP VRE F

AIN1AIN2

AIN3AIN4AIN5

AUX ILIA RY 16-BIT Σ? AD C

PRIM ARY 24-BIT Σ? AD C

MU X

OSC &PLL

AV DD

MU X

16-BI T P W M PGA

16-BI T

Σ? DAC

16-BI T

Σ? DAC

16-BI T P W M

12-BI T D A C BUF DA C

CU R RE N T SO UR CE

AVDD

IEX C1IEX C2

PW M0

PW M1

(12 March 2002) REV. P rC

ADuC834

–2–

PRELIMINARY TECHNICAL DATA

OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 8ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 18MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . 21SPECIAL FUNCTION REGISTERS (SFRS) . . . . . . . . . . 22Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22B SFR (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . 23Power Control (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . 23ADuC834 Configuration SFR (CFG834) . . . . . . . . . . . .23Complete SFR Map . . . . . . . . . . . . . . . . . . . . . . . . . . . .24PRIMARY AND AUXILIARY ADCs . . . . . . . . . . . . . . . . 25ADCSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ADCMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26ADC0CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27ADC1CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27ADC0H/M/L / ADC1H/L . . . . . . . . . . . . . . . . . . . . . . . . 28OF0H/M/L / OF1H/L . . . . . . . . . . . . . . . . . . . . . . . . . . . 28GN0H/M/L / GN1H/L . . . . . . . . . . . . . . . . . . . . . . . . . .28SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29ICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29PRIMARY AND AUX ADC NOISE PERFORMANCE . .30PRIMARY AND AUXILIARY ADC DESCRIPTION . . . 31Primary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 33Primary and Auxiliary ADC Inputs . . . . . . . . . . . . . . . . . 33Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 33Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 33Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . 34Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ADC Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36NONVOLATILE FLASH/EE MEMORY . . . . . . . . . . . . . 37Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . 37Flash/EE Memory and the ADuC834 . . . . . . . . . . . . . . . 37ADuC834 Flash/EE Memory Reliability . . . . . . . . . . . . . 37USING THE FLASH/EE PROGRAM MEMORY . . . . . . 38Serial/Parallel Downloading . . . . . . . . . . . . . . . . . . . . . . . 38User Download Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Flash/EE Program Memory Security . . . . . . . . . . . . . . . . 38

USING THE FLASH/EE DATA MEMORY . . . . . . . . . . . 39ECON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Programming the Flash/EE Data Memory . . . . . . . . . . . 40FLASH/EE MEMORY TIMING . . . . . . . . . . . . . . . . . . . . 40DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41DACCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Using the DAC Converter . . . . . . . . . . . . . . . . . . . . . . . . 41PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43PWMCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44ON-CHIP PLL (PLLCON) . . . . . . . . . . . . . . . . . . . . . . . . 46TIME INTERVAL COUNTER (TIMECON) . . . . . . . . . . 47WATCHDOG TIMER (WDCON) . . . . . . . . . . . . . . . . . . 49POWER SUPPLY MONITOR (PSMCON) . . . . . . . . . . . 50SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . 51Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51SPICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Using the SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 52DUAL DATA POINTER (DPCON) . . . . . . . . . . . . . . . . . 538051-COMPATIBLE PERIPHERALS . . . . . . . . . . . . . . . . 54Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Additional High Current Digital Output Pins . . . . . . . . . 54TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . 55TMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Timer/Counter 0/1 Modes of Operation . . . . . . . . . . . 57Timer 2 Operating Modes . . . . . . . . . . . . . . . . . . . . . .58T2CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59UART Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 60SCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60UART Operating Modes . . . . . . . . . . . . . . . . . . . . . . . 61Baud Rate Generation using Timer 1 and Timer 2 . . .62Baud Rate Generation using Timer 3 . . . . . . . . . . . . .63INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . 64HARDWARE DESIGN CONSIDERATIONS . . . . . . . . . . 66External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . 66Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . 67Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Power-Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Grounding and Board Layout Recommendations . . . . . . 68System Self-Identification . . . . . . . . . . . . . . . . . . . . . . . . 68Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68OTHER HARDWARE CONSIDERATIONS . . . . . . . . . . 69In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . 69Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . 69Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . 69Enhanced-Hooks Emulation Mode . . . . . . . . . . . . . . . . . 69Typical System Configuration . . . . . . . . . . . . . . . . . . . . . 69QUICKSTART DEVELOPMENT SYSTEM . . . . . . . . . . 71OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 72

TABLE OF CONTENTS

REV. P rC (12 March 2002)

–3–

ADuC834

PRELIMINARY TECHNICAL DATA

Parameter

ADuC834BS Test Conditions/Comments

Unit ADC SPECIFICATIONS Conversion Rate 5.4On Both Channels

Hz min 105

Programmable in 0.732ms Increments Hz max Primary ADC

No Missing Codes 22420Hz Update Rate

Bits min Resolution 13Range = ±20mV, 20Hz Update Rate Bits p-p typ 18

Range = ±2.56V, 20Hz Update Rate Bits p-p typ

Output Noise

See Table X and XI Output Noise Varies with Selected in ADuC834 ADC Update Rate and Gain Range Description (pg 30)Integral Nonlinearity ±15 1 LSB 16

ppm of FSR max Offset Error 3

±3μV typ Offset Error Drift ±10nV/°C typ Full-Scale Error 4±10μV typ

Gain Error Drift 5

±0.5ppm/°C typ ADC Range Matching

±2AIN = 18mV

μV typ Power Supply Rejection (PSR)

113AIN = 7.8mV, Range = ±20mV dBs typ 80AIN = 1V, Range = ±2.56V

dBs min Common-Mode DC Rejection On AIN 95At DC, AIN = 7.8mV, Range = ±20mV dBs min On AIN 113At DC, AIN = 1V, Range = ±2.56V dBs typ On REFIN

125At DC, AIN = 1V, Range = ±2.56V dBs typ Common-Mode 50Hz/60Hz Rejection 220Hz Update Rate

On AIN

9550Hz/60Hz ±1Hz, AIN = 7.8mV,dBs min Range = ±20mV

50Hz/60Hz ±1Hz, AIN = 1V,dBs min Range = ±2.56V

On REFIN

9050Hz/60Hz ±1Hz, AIN = 1V,dBs min Range = ±2.56V

Normal Mode 50Hz/60Hz Rejection 2On AIN 6050Hz/60Hz ±1Hz, 20Hz Update Rate dBs min On REFIN 60

50Hz/60Hz ±1Hz, 20Hz Update Rate dBs min Auxiliary ADC

No Missing Codes 216Bits min Resolution 16

Range = ±2.5V, 20Hz Update Rate Bits p-p typ

Output Noise

See Table XII in Output Noise Varies with Selected ADuC834 ADC Update Rate

Description (pg 30)Integral Nonlinearity ±15ppm of FSR max Offset Error 3

–2LSB typ Offset Error Drift 1μV/°C typ Full-Scale Error 6–2.5LSB typ Gain Error Drift 5

±0.5ppm/°C typ Power Supply Rejection (PSR)

80AIN = 1V, 20Hz Update Rate dBs min Normal Mode 50Hz/60Hz Rejection 2On AIN 6050Hz/60Hz ±1Hz

dBs min On REFIN 60

50Hz/60Hz ±1Hz, 20Hz Update Rate

dBs min

DAC PERFORMANCE DC Specifications 7Resolution

12Bits Relative Accuracy

±3LSB typ Differential Nonlinearity –1Guaranteed 12-Bit Monotonic LSB max Offset Error ±50mV max Gain Error 8

±1AV DD Range % max ±1V REF Range

% typ AC Specifications 2, 7

Voltage Output Settling Time 15Settling Time to 1 LSB of Final Value μs typ Digital-to-Analog Glitch Energy

1 LSB Change at Major Carry

nVs typ

(AV DD = 2.7V to 3.6V or 4.75V to 5.25V, DV DD = 2.7V to 3.6V or 4.75V to 5.25V,

REFIN(+) = 2.5V, REFIN(–) = AGND; AGND = DGND = 0V; XTAL1/XTAL2 = 32.768kHz Crystal; all specifications T MIN to T MAX unless otherwise noted.)

SPECIFICATIONS

PRELIMINARY TECHNICAL DAT A

ADuC834–SPECIFICATIONS1

Parameter ADuC834BS Test Conditions/Comments Unit

INTERNAL REFERENCE

ADC Reference

Reference Voltage 1.25 ± 1%Initial Tolerance @ 25°C, V DD = 5V V min/max

Power Supply Rejection45dBs typ

Reference Tempco100ppm/°C typ

DAC Reference

Reference Voltage 2.5 ± 1%Initial Tolerance @ 25°C, V DD = 5V V min/max

Power Supply Rejection50dBs typ

Reference Tempco±100ppm/°C typ ANALOG INPUTS/REFERENCE INPUTS

Primary ADC

Differential Input Voltage Ranges9, 10External Reference Voltage = 2.5V

RN2, RN1, RN0 of ADC0CON Set to Bipolar Mode (ADC0CON3 = 0)±20000(Unipolar Mode 0 to 20mV)mV

±40001(Unipolar Mode 0 to 40mV)mV

±80010(Unipolar Mode 0 to 80mV)mV

±160011(Unipolar Mode 0 to 160mV)mV

±320100(Unipolar Mode 0 to 320mV)mV

±640101(Unipolar Mode 0 to 640mV)mV

±1.28110(Unipolar Mode 0 to 1.28V)V

±2.56111(Unipolar Mode 0 to 2.56V)V Analog Input Current2±1nA max

Analog Input Current Drift±5pA/°C typ

Absolute AIN Voltage Limits AGND + 100mV V min

AV DD – 100mV V max

Auxiliary ADC

Input Voltage Range9, 100 to V REF Unipolar Mode, for Bipolar Mode V

See Note 11

Average Analog Input Current125Input Current Will Vary with Input nA/V typ

Average Analog Input Current Drift2±2Voltage on the Unbuffered Auxiliary ADC pA/V/°C typ Absolute AIN Voltage Limits11AGND – 30mV V min

AV DD + 30mV V max

External Reference Inputs

REFIN(+) to REFIN(–) Range21V min

AV DD V max Average Reference Input Current1Both ADCs EnabledμA/V typ

Average Reference Input Current Drift±0.1nA/V/°C typ ‘NO Ext. REF’ Trigger Voltage0.3NOXREF Bit Active if V REF < 0.3V V min

0.65NOXREF Bit Inactive if V REF > 0.65V V max

ADC SYSTEM CALIBRATION

Full-Scale Calibration Limit+1.05 × FS V max

Zero-Scale Calibration Limit–1.05 × FS V min

Input Span0.8 × FS V min

2.1 × FS V max

ANALOG (DAC) OUTPUTS

Voltage Range0 to V REF DACRN = 0 in DACCON SFR V typ

0 to AV DD DACRN = 1 in DACCON SFR V typ

Resistive Load10From DAC Output to AGND? typ

Capacitive Load100From DAC Output to AGND pF typ

Output Impedance0.5? typ

I SINK50μA typ TEMPERATURE SENSOR

Accuracy±2°C typ

Thermal Impedance (θJA)90°C/? typ

(12 March 2002) REV. P rC

–4–

PRELIMINARY TECHNICAL DATA

ADuC834 Parameter ADuC834BS Test Conditions/Comments Unit TRANSDUCER BURNOUT CURRENT SOURCES

AIN+ Current–100AIN+ is the Selected Positive Input to nA typ

the Primary ADC

AIN– Current+100AIN– is the Selected Negative Input to nA typ

the Auxiliary ADC

Initial Tolerance @ 25°C±10% typ

Drift0.03%/°C typ EXCITATION CURRENT SOURCES

Output Current–200Available from Each Current SourceμA typ

Initial Tolerance @ 25°C±10% typ

Drift200ppm/°C typ Initial Current Matching @ 25°C±1Matching Between Both Current Sources% typ

Drift Matching20ppm/°C typ Line Regulation (AV DD)1AV DD = 5V + 5%μA/V typ

Load Regulation0.1μA/V typ

Output Compliance AV DD – 0.6V max

AGND Min

LOGIC INPUTS

All Inputs Except SCLOCK, RESET,

and XTAL1

V INL, Input Low Voltage0.8DV DD = 5V V max

0.4DV DD = 3V V max

V INH, Input High Voltage 2.0V min

SCLOCK and RESET Only

(Schmitt-Triggered Inputs)2

V T+ 1.3/3DV DD = 5V V min/V max

0.95/2.5DV DD = 3V V min/V max

V T–0.8/1.4DV DD = 5V V min/V max

0.4/1.1DV DD = 3V V min/V max

V T+ – V T–0.3/0.85DV DD = 5V V min/V max

0.3/0.85DV DD = 3V V min/V max

Input Currents

Port 0, P1.2–P1.7, EA±10V IN = 0V or V DDμA max

SCLOCK, MOSI, MISO, SS12–10 min, –40 max V IN = 0V, DV DD = 5V, Internal Pull-UpμA min/μA max

±10V IN = V DD, DV DD = 5VμA max RESET±10V IN = 0V, DV DD = 5VμA max

35 min, 105 max V IN = V DD, DV DD = 5V,μA min/μA max

Internal Pull-Down

P1.0, P1.1, Ports 2 and 3±10V IN = V DD, DV DD = 5VμA max

–180V IN = 2V, DV DD = 5VμA min

–660μA max

–20V IN = 450mV, DV DD = 5VμA min

–75μA max Input Capacitance5All Digital Inputs pF typ CRYSTAL OSCILLATOR (XTAL1 AND XTAL2)

Logic Inputs, XTAL1 Only

V INL, Input Low Voltage0.8DV DD = 5V V max

0.4DV DD = 3V V max

V INH, Input High Voltage 3.5DV DD = 5V V min

2.5DV DD = 3V V min

XTAL1 Input Capacitance18pF typ

XTAL2 Output Capacitance18pF typ

REV. P rC (12 March 2002)–5–

PRELIMINARY TECHNICAL DAT A

ADuC834–SPECIFICATIONS1

Parameter ADuC834BS Test Conditions/Comments Unit

LOGIC OUTPUTS (Not Including XTAL2)2

V OH, Output High Voltage 2.4V DD = 5V, I SOURCE = 80μA V min

2.4V DD = 3V, I SOURCE = 20μA V min

V OL, Output Low Voltage130.4I SINK = 8mA, SCLOCK/D0,V max

MOSI/D1

0.4I SINK = 10mA, P1.0 and P1.1V max

0.4I SINK = 1.6mA, All Other Outputs V max

Floating State Leakage Current±10μA max

Floating State Output Capacitance5pF typ

POWER SUPPLY MONITOR (PSM)

AV DD Trip Point Selection Range 2.63Four Trip Points Selectable in This Range V min

4.63Programmed via TPA1–0 in PSMCON V max

AV DD Power Supply Trip Point Accuracy±3.5% max

DV DD Trip Point Selection Range 2.63Four Trip Points Selectable in This Range V min

4.63Programmed via TPD1–0 in PSMCON V max

DV DD Power Supply Trip Point Accuracy±3.5% max WATCHDOG TIMER (WDT)

Timeout Period0Nine Timeout Periods in This Range ms min

2000Programmed via PRE3–0 in WDCON ms max

MCU CORE CLOCK RATE Clock Rate Generated via On-Chip PLL MCU Clock Rate298.3Programmable via CD2–0 Bits in kHz min

PLLCON SFR

12.58MHz max START-UP TIME

At Power-On300ms typ

From Idle Mode1ms typ

From Power-Down Mode

Oscillator Running OSC_PD Bit = 0 in PLLCON SFR

Wakeup with INT0 Interrupt1ms typ

Wakeup with SPI Interrupt1ms typ

Wakeup with TIC Interrupt1ms typ

Wakeup with External RESET 3.4ms typ

Oscillator Powered Down OSC_PD Bit = 1 in PLLCON SFR

Wakeup with External RESET0.9sec typ After External RESET in Normal Mode 3.3ms typ

After WDT Reset in Normal Mode 3.3Controlled via WDCON SFR ms typ

FLASH/EE MEMORY RELIABILITY CHARACTERISTICS14

Endurance15100,000Cycles min Data Retention16100Years min POWER REQUIREMENTS DV DD and AV DD Can Be Set

Independently

Power Supply Voltages

AV DD, 3V Nominal Operation 2.7V min

3.6V max

AV DD, 5V Nominal Operation 4.75V min

5.25V max

DV DD, 3V Nominal Operation 2.7V min

3.6V max

DV DD, 5 V Nominal Operation 4.75V min

5.25V max

(12 March 2002) REV. P rC

–6–

ADuC834 PRELIMINARY TECHNICAL DATA

Parameter ADuC834BS Test Conditions/Comments Unit POWER REQUIREMENTS (continued)

Power Supply Currents Normal Mode17, 18

DV DD Current4DV DD = 4.75V to 5.25V, Core CLK = 1.57MHz mA max

2.1DV DD = 2.7V to

3.6V, Core CLK = 1.57MHz mA max

AV DD Current170AV DD = 5.25V, Core CLK = 1.57MHzμA max DV DD Current15DV DD = 4.75V to 5.25V, Core CLK = 12.58MHz mA max

8DV DD = 2.7V to 3.6V, Core CLK = 12.58MHz mA max AV DD Current170AV DD = 5.25V, Core CLK = 12.58MHzμA max Power Supply Currents Idle Mode17, 18

DV DD Current 1.2DV DD = 4.75V to 5.25V, Core CLK = 1.57MHz mA max

750DV DD = 2.7V to 3.6V, Core CLK = 1.57MHzμA typ AV DD Current140Measured @ AV DD = 5.25V, Core CLK = 1.57MHzμA typ DV DD Current2DV DD = 4.75V to 5.25V, Core CLK = 12.58MHz mA typ

1DV DD = 2.7V to 3.6V, Core CLK = 12.58MHz mA typ AV DD Current140Measured at AV DD = 5.25V, Core CLK = 12.58MHzμA typ Power Supply Currents Power-Down Mode17, 18Core CLK = 1.57MHz or 12.58MHz

DV DD Current50DV DD = 4.75V to 5.25V, Osc. On, TIC OnμA max

20DV DD = 2.7V to 3.6V, Osc. On, TIC OnμA max AV DD Current1Measured at AV DD = 5.25V, Osc. On or Osc. OffμA max DV DD Current20DV DD = 4.75V to 5.25V, Osc. OffμA max

5DV DD = 2.7V to 3.6V, Osc. OffμA typ Typical Additional Power Supply Currents Core CLK = 1.57MHz, AV DD = DV DD = 5V

(AI DD and DI DD)

PSM Peripheral50μA typ Primary ADC1mA typ Auxiliary ADC500μA typ DAC150μA typ Dual Current Sources400μA typ NOTES

1Temperature Range –40°C to +85°C.

2These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release.

3System Zero-Scale Calibration can remove this error.

4The primary ADC is factory calibrated at 25°C with AV

= DV DD = 5 V yielding this full-scale error of 10 μV. If user power supply or temperature conditions are significantly different than these, an Internal Full-Scale Calibration will restore this error to 10 μV. A system zero-scale and full-scale calibration will remove this error altogether.

5Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.

6The auxiliary ADC is factory calibrated at 25°C with AV

= DV DD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration will remove this error altogether.

7DAC linearity and AC Specifications are calculated using:

reduced code range of 48 to 4095, 0 to V REF,

reduced code range of 48 to 3995, 0 to V DD.

8Gain Error is a measure of the span error of the DAC.

9In general terms, the bipolar input voltage range to the primary ADC is given by Range

ADC

= ±(V REF 2RN)/125, where:

V REF = REFIN(+) to REFIN(–) voltage and V REF = 1.25 V when internal ADC V REF is selected.

RN = decimal equivalent of RN2, RN1, RN0,

e.g., V REF = 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the Range ADC = ±1.28 V.

In unipolar mode the effective range is 0V to 1.28 V in our example.

101.25 V is used as the reference voltage to the ADC when internal V

REF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON respectively.

11In bipolar mode, the Auxiliary ADC can only be driven to a minimum of A

GND

– 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar range is still –V REF to +V REF; however, the negative voltage is limited to –30 mV.

12Pins configured in SPI mode, pins configured as digital inputs during this test.

13Pins configured in High Current Output mode only.

14Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.

15Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C and +85°C, typical endurance at 25°C is 700 Kcycles.

16Retention lifetime equivalent at junction temperature (T

) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of

0.6eV will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this data sheet.

17Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:

Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.

Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode.

Power-Down Mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in

PLLCON SFR.

18DV

power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. Specifications subject to change without notice

REV. P rC (12 March 2002)–7–

(12 March 2002) REV. P rC

ADuC834

–8–PRELIMINARY TECHNICAL DATA

TIMING SPECIFICATIONS

1, 2, 3(AV DD = 2.7V to 3.6V or 4.75V to 5.25V, DV DD = 2.7V to 3.6V or 4.75V to 5.25V; all

specifications T MIN to T MAX unless otherwise noted.)

32.768kHz External Crystal

Parameter

Min Typ Max

Unit Figure CLOCK INPUT (External Clock Driven XTAL1)t CK XTAL1 Period

30.52

μs 1t CKL

XTAL1 Width Low 15.16μs 1t CKH XTAL1 Width High 15.16μs 1t CKR XTAL1 Rise Time

20ns 1t CKF

XTAL1 Fall Time 20

ns 1

1/t CORE ADuC834 Core Clock Frequency 40.09812.58MHz t CORE ADuC834 Core Clock Period 50.636μs t CYC ADuC834 Machine Cycle Time 6

0.95

7.6

122.45

μs

NOTES 1

AC inputs during testing are driven at DV DD – 0.5V for a Logic 1, and 0.45V for a Logic 0. Timing measurements are made at V IH min for a Logic 1, and V IL max for a Logic 0 as shown in Figure 2.2

For timing purposes, a port pin is no longer floating when a 100mV change from load voltage occurs. A port pin begins to float when a 100mV change from the loaded V OH /V OL level occurs as shown in Figure 2.3

C LOA

D for Port0, ALE, PSEN outputs = 100pF; C LOAD for all other outputs = 80pF unless otherwise noted.4

ADuC834 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a Stable 12.583

MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.5

This number is measured at the default Core_Clk operating frequency of 1.57MHz.6

ADuC834 Machine Cycle Time is nominally defined as 12/Core_CLK.

t C HK

t CK L

t CK

t CKF

t C KR

Figure 1.XTAL1 Input

DV DD ?V LOA D

LOA D

Figure 2.Timing Waveform Characteristics

REV. P rC (12 March 2002)ADuC834

–9–

PRELIMINARY TECHNICAL DATA

12.58MHz Core_Clk

Variable Core_Clk Parameter

Min Max Min Max Unit Figure EXTERNAL PROGRAM MEMORY

t LHLL

ALE Pulsewidth 1192t CORE – 40ns 3t AVLL

Address Valid to ALE Low 39t CORE – 40ns 3t LLAX

Address Hold after ALE Low 49

t CORE – 30ns 3t LLIV ALE Low to Valid Instruction In 218

4t CORE – 100ns 3t LLPL ALE Low to PSEN Low

49t CORE – 30ns 3t PLPH

PSEN Pulsewidth 193

3t CORE – 45ns 3t PLIV PSEN Low to Valid Instruction In 133

3t CORE – 105

ns 3t PXIX Input Instruction Hold after PSEN

ns 3t PXIZ

Input Instruction Float after PSEN 54t CORE – 25ns 3t AVIV Address to Valid Instruction In 2925t CORE – 105ns 3t PLAZ PSEN Low to Address Float 25

ns 3t PHAX Address Hold after PSEN High

CORE_C LK

ALE (O)

P S E N (O)

PORT 0 (I/O)

PORT 2 (O)Figure 3.External Program Memory Read Cycle

(12 March 2002) REV. P rC

ADuC834

–10–PRELIMINARY TECHNICAL DATA

12.58MHz Core_Clk

Variable Core_Clk Parameter

Min Max Min Max Unit Figure EXTERNAL DATA MEMORY READ CYCLE t RLRH RD Pulsewidth 3776t CORE – 100ns 4t AVLL Address Valid after ALE Low 39t CORE – 40ns 4t LLAX Address Hold after ALE Low

t CORE – 35ns 4t RLDV

RD Low to Valid Data In 232

5t CORE – 165ns 4t RHDX Data and Address Hold after RD 0

ns 4t RHDZ Data Float after RD

892t CORE – 70ns 4t LLDV

ALE Low to Valid Data In 4868t CORE – 150ns 4t AVDV Address to Valid Data In 5509t CORE – 165ns 4t LLWL ALE Low to RD Low

1882883t CORE – 503t CORE + 50ns 4t AVWL

Address Valid to RD Low 1884t CORE – 130ns 4t RLAZ RD Low to Address Float 00

ns 4t WHLH RD High to ALE High

119

t CORE – 40

t CORE + 40

CORE_C LK

ALE (O)

PSEN (O)

PORT 0 (I/O)

PORT 2 (O)R D (O)

Figure 4. External Data Memory Read Cycle

REV. P rC (12 March 2002)ADuC834

–11–

PRELIMINARY TECHNICAL DATA

12.58MHz Core_Clk

Variable Core_Clk Parameter

Min Max Min Max Unit Figure EXTERNAL DATA MEMORY WRITE CYCLE

t WLWH

WR Pulsewidth 3776t CORE – 100ns 5t AVLL Address Valid after ALE Low 39t CORE – 40ns 5t LLAX Address Hold after ALE Low

44t CORE – 35ns 5t LLWL

ALE Low to WR Low 188288

3t CORE – 503t CORE + 50

ns 5t AVWL Address Valid to WR Low 1884t CORE – 130ns 5t QVWX Data Valid to WR Transition

29t CORE – 50ns 5t QVWH

Data Setup before WR 4067t CORE – 150ns 5t WHQX Data and Address Hold after WR 29t CORE – 50ns 5t WHLH WR High to ALE High

119t CORE – 40

t CORE + 40

CORE_C LK

ALE (O)

PSEN (O)

PORT 0 (O)

PORT 2 (O)W R (O)

Figure 5.External Data Memory Write Cycle

(12 March 2002) REV. P rC

ADuC834

–12–PRELIMINARY TECHNICAL DATA

12.58MHz Core_Clk

Variable Core_Clk Parameter

Min Typ Max

Min Typ

Max

Unit Figure UART TIMING (Shift Register Mode)t XLXL Serial Port Clock Cycle Time 0.95

12t CORE

μs

6t QVXH Output Data Setup to Clock 66210t CORE – 133ns 6t DVXH Input Data Setup to Clock

2922t CORE + 133ns 6t XHDX

Input Data Hold after Clock 00

ns 6t XHQX Output Data Hold after Clock

2t CORE – 117

ALE (O)

TXD

(OUTPUT CLOCK)

RXD

(OUTPUT DATA)

RXD

(INPUT DATA)

Figure 6.UART Timing in Shift Register Mode

REV. P rC (12 March 2002)ADuC834

–13–

PRELIMINARY TECHNICAL DATA

Parameter

Min

Typ Max

Unit Figure SPI MASTER MODE TIMING (CPHA = 1)t SL SCLOCK Low Pulsewidth *630

ns 7t SH SCLOCK High Pulsewidth *

630

ns 7t DAV

Data Output Valid after SCLOCK Edge 50

ns 7t DSU

Data Input Setup Time before SCLOCK Edge 100ns 7t DHD Data Input Hold Time after SCLOCK Edge 100

ns 7t DF Data Output Fall Time

1025ns 7t DR

Data Output Rise Time 1025ns 7t SR SCLOCK Rise Time 1025ns 7t SF SCLOCK Fall Time

25ns

NOTE

*Characterized under the following conditions:

a.Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57MHz and

b.SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively.

SCLOCK (CPOL = 0)t SH SCLOCK (CPOL = 1)

M OSI

M ISO M SB IN B ITS 6 ? 1B IT S 6 ? 1

LSB IN

LSB

M SB

t SL

t DAV

t D F t DR

t SR

t SF

t D HD

t DS U Figure 7.SPI Master Mode Timing (CPHA = 1)

(12 March 2002) REV. P rC

ADuC834

–14–PRELIMINARY TECHNICAL DATA

Parameter

Min

Typ Max

Unit Figure SPI MASTER MODE TIMING (CPHA = 0)t SL SCLOCK Low Pulsewidth *630

ns 8t SH SCLOCK High Pulsewidth *

630

ns 8t DAV

Data Output Valid after SCLOCK Edge 50ns 8t DOSU

Data Output Setup before SCLOCK Edge 150

ns 8t DSU Data Input Setup Time before SCLOCK Edge 100ns 8t DHD Data Input Hold Time after SCLOCK Edge

100

ns 8t DF

Data Output Fall Time 1025ns 8t DR Data Output Rise Time 1025ns 8t SR SCLOCK Rise Time 1025ns 8t SF SCLOCK Fall Time

25ns

NOTE

*Characterized under the following conditions:

a.Core clock divider bits CD2, CD1 and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57MHz and

b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively.

SCLOCK (CPOL = 0)

t DSU SCLOCK (CPOL = 1)

M OSI

M ISO M SB

LSB

LSB IN

B IT S 6 ? 1B ITS 6 ? 1

M SB IN t D HD

t D R

t DA V

t D F t DO SU

t S H t SL

t S R

t S F

Figure 8.SPI Master Mode Timing (CPHA = 0)

REV. P rC (12 March 2002)ADuC834

–15–

PRELIMINARY TECHNICAL DATA

Parameter

Min Typ Max Unit Figure SPI SLAVE MODE TIMING (CPHA = 1)

t SS

SS to SCLOCK Edge 0

ns 9t SL

SCLOCK Low Pulsewidth 330

ns 9t SH

SCLOCK High Pulsewidth 330

ns 9t DAV Data Output Valid after SCLOCK Edge 50

ns 9t DSU Data Input Setup Time before SCLOCK Edge

100ns 9t DHD

Data Input Hold Time after SCLOCK Edge 100

ns 9t DF Data Output Fall Time 1025ns 9t DR Data Output Rise Time

1025

ns 9t SR

SCLOCK Rise Time 1025ns 9t SF SCLOCK Fall Time 1025

ns 9t SFS SS High after SCLOCK Edge

SCLOCK (CPOL = 0)

t S S SCLOCK (CPOL = 1)

M ISO

M OSI SS

M SB IN B ITS 6 ?

1LSB

LSB

B ITS 6 ? 1

M SB

t D H D

t DSU

t D F t D R

t SL

t S H

t DA V

t D F

t S R

t S F

t SFS

Figure 9.SPI Slave Mode Timing (CPHA = 1)

(12 March 2002) REV. P rC

ADuC834

–16–PRELIMINARY TECHNICAL DATA

Parameter

Min Typ

Max

Unit Figure SPI SLAVE MODE TIMING (CPHA = 0)t SS SS to SCLOCK Edge 0

ns 10t SL SCLOCK Low Pulsewidth

330

ns 10t SH

SCLOCK High Pulsewidth 330

ns 10t DAV

Data Output Valid after SCLOCK Edge 50

ns 10t DSU Data Input Setup Time before SCLOCK Edge 100ns 10t DHD Data Input Hold Time after SCLOCK Edge

100

ns 10t DF

Data Output Fall Time 1025ns 10t DR Data Output Rise Time 1025ns 10t SR SCLOCK Rise Time

1025ns 10t SF

SCLOCK Fall Time 10

25ns 10t SSR SS to SCLOCK Edge 50ns 10t DOSS Data Output Valid after SS Edge 20

ns 10t SFS SS High after SCLOCK Edge

M ISO

M OSI SCLOCK (CPOL = 1)

SCLOCK (CPOL = 0)

M SB

B IT S 6 ? 1

LSB

B ITS 6 ? 1LSB IN

M SB IN t D H D

t D SU t DR

t DF

t DA V

t DO SS

t S H t SL

t SS

t S R

t S F

t SFS

Figure 10.SPI Slave Mode Timing (CPHA = 0)

REV. P rC (12 March 2002)ADuC834

–17–

PRELIMINARY TECHNICAL DATA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC834 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS 1

(T A = 25°C unless otherwise noted)

AV DD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V AV DD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V DV DD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V DV DD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V AGND to DGND 2 . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AV DD to DV DD . . . . . . . . . . . . . . . . . . . . . . . . . –2V to +5V Analog Input Voltage to AGND 3 . . . –0.3V to AV DD +0.3V Reference Input Voltage to AGND . . –0.3V to AV DD +0.3V AIN/REFIN Current (Indefinite) . . . . . . . . . . . . . . . . 30mA Digital Input Voltage to DGND . . . . –0.3V to DV DD +0.3V Digital Output Voltage to DGND . . . –0.3V to DV DD +0.3V Operating Temperature Range . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 53.2°C/W Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.2

AGND and DGND are shorted internally on the ADuC834.3

Applies to P1.2 to P1.7 pins operating in analog or digital input modes.

PIN CONFIGURATION

52-Lead MQFP

ORDERING GUIDE

Model

Temperature Package Package Range

Description

Option ADuC834BS

–40°C to +85°C

52-Lead Plastic Quad Flatpack

S-52

QuickStart Development System Description

Model

EVAL-ADUC834QS

Development System for the ADuC834 MicroConverter, Containing:Evaluation Board Serial Port Cable

Windows ? Serial Downloader (WSD)

Windows Debugger/Emulator (with C source DeBug)Windows ADuC834 Simulator (ADSIM)

Windows ADC Analysis Software Program (WASP)8051 Assembler (Metalink)Example Code Documentation

Windows is a registered trademark of Microsoft Corporation.

(12 March 2002) REV. P rC

ADuC834

–18–PRELIMINARY TECHNICAL DATA

Pin No.Mnemonic Type *Description

1, 2

P1.0/P1.1I/O P1.0 and P1.1 can function as a digital inputs or digital outputs and have a pull-up configuration as described below for Port 3. P1.0 and P1.1 have an increased current drive sink capability of 10mA.

P1.0/T2/PWM0

I/O

P1.0 and P1.1 also have various secondary functions as described below.

P1.0 can also be used to provide a clock input to Timer 2. When Enabled, counter 2 is incremented in response to a negative transition on the T2 input pin.If the PWM is enabled then the PWM0 output will appear at this pin.

P1.1/T2EX/PWM1I/O

P1.1 can also be used to provide a control input to Timer 2. When Enabled, a negative transition on the T2EX input pin will cause a Timer 2 capture or reload event.

If the PWM is enabled then the PWM1 output will appear at this pin.

ADuC834 DETAILED BLOCK DIAGRAM

Figure 11.ADuC834 Detailed Block Diagram

ADuC834 PIN BY PIN FUNCTION DESCRIPTION

PRO G. CLO CK

DIVIDER

W ATCH DO G

TIM ER 256 BYTES USER

RAM

POW ER SUPPLY

M ONITOR

AIN3AIN4AIN5

AIN1AIN2

REFIN ?REFIN ?

IEXC 2IEXC 1AIN M UX

TEMP SENSO R AIN M UX

BAND G AP REFERENCE

V R E F DETECT

CURR ENT SOURCE M UX

200?A

5A V D D

6A G N D

20D V D D

D V D D

21D G N D

35D G N D

26S C L O C K /D 0

27M O S I /D 1

14M I S O

13S S

X T A L 1

BUF

AD uC834

AUXILIARY A DC

16-BIT ?? A DC

ADC CO NTROL

AN D

CALIBRATION

PGA

PRIM ARY A DC

24-BIT ?? A DC

AD C CO NTROL

AN D

CALIBRA TION

322T023T12

T2EX

T2118IN T 019

IN T 1

DA C

40E A

41P S E N

17T X D

16R X D

4 KBYTES DATA

FLASH/EE

62 KBYTES PRO GRAM FLASH/EE INCLUDING USER DO W NLOAD M ODE

UAR T

SERIAL PORT

8052

M CU CO RE

DO W NLO ADER DEBUG G ER

DA C CO NTROL

BUF

S I N G L E -P I N E M U L A T O R

SPI SERIAL INTERFACE

16-BIT CO UNT ER TIM ERS

TIM E INTERVAL

CO UNT ER (W AKEUP CCT)

X T A L 2

O SC

43P 0.0 (A D 0)

44P 0.1 (A D 1)

45P 0.2 (A D 2)

46P 0.3 (A D 3)

49P 0.4 (A D 4)

50P 0.5 (A D 5)

51P 0.6 (A D 6)

52P 0.7 (A D 7)

1P 1.0 (T 2)

2P 1.1 (T 2E X )

3P 1.2 (D A C /I E X C 1)

49P 1.4 (A I N 1)

10P 1.5 (A I N 2)

11P 1.6 (A I N 3)

12P 1.7 (A I N 4/D A C )

28P 2.0 (A 8

29P 2.1 (A 9/A 17)

30P 2.2 (A 10/A 18)

31P 2.3 (A 11/A 19)

36P 2.4 (A 1

37P 2.5 (A 1

38P 2.6 (A 1

39P 2.7 (A 1

16P 3.0 (R X D )

17P 3.1 (T X D )

18P 3.2 (I N T 0)

19P 3.3 (I N T 1)

22P 3.4 (T 0)

23P 3.5 (T 1)

P 3.6 (W R )

P 3.7 (R D )

12-BIT VOLTAG E O UTPUT D AC P 1.3 (A I N 5/I E X C 2)2 KBytes USER XRAM

PLL

2 X DATA POINTERS 11-BIT STACK PO INTER

M UX

16-BIT SD DA C PW M 0

PW M 1

16-BIT PWM

16-BIT PWM PW M CO NTROL

16-BIT SD DA C

3242A L E

POR

15R E S E T

48D V D D

3447D G N D

UAR T TIM ER * SHADED AREAS REPRESENT THE NEW FEATURES OF THE ADUC834 OVER THE ADUC824

REV. P rC (12 March 2002)ADuC834

–19–

PRELIMINARY TECHNICAL DATA

Pin No.Mnemonic Type *Description

3-4, 9-12

P1.2-P1.7

Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital input for which ‘0’ must be written to the port bit. As a digital input, these pins must be driven high or low externally.

These pins also have the following analog functionality:

P1.2/DAC/IEXC1I/O The voltage output from the DAC or one or both current sources (200μA or 2 x 200μA) can be configured to appear at this pin.

P1.3/AIN5/IEXC2I/O Auxiliary ADC Input or one or both current sources can be configured at this pin.P1.4/AIN1I Primary ADC, Positive Analog Input P1.5/AIN2I Primary ADC, Negative Analog Input

P1.6/AIN3

I Auxiliary ADC Input or muxed Primary ADC, Positive Analog Input

P1.7/AIN4/DAC

I/O Auxiliary ADC Input or muxed Primary ADC, Negative Analog Input. The voltage output from the DAC can also be configured to appear at this pin.5AV DD S Analog Supply Voltage, 3V or 5V

6AGND S Analog Ground. Ground reference pin for the analog circuitry.7REFIN(–)I Reference input, negative terminal.8REFIN(+)I Reference input, positive terminal.

13SS I Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.14MISO I/O Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this input pin.

RESET

Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is running resets the device. There is an internal weak pull-down and a Schmitt trigger input stage on this pin.

16–19,P3.0–P3.7I/O

P3.0–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins 22-25

that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. When driving a 0-to-1 output transition, a strong pull-up is active for two core clock periods of the instruction cycle.

Port 3 pins also have various secondary functions described below.P3.0/RXD I/O Receiver Data for UART serial Port P3.1/TXD I/O Transmitter Data for UART serial Port

P3.2/INT0I/O External Interrupt 0. This pin can also be used as a gate control input to Timer0.P3.3/INT1I/O External Interrupt 1. This pin can also be used as a gate control input to Timer1.P3.4/T0I/O Timer/Counter 0 External Input P3.5/T1I/O Timer/Counter 1 External Input

P3.6/WR I/O External Data Memory Write Strobe. Latches the data byte from Port 0 into an external data memory.

P3.7/RD

I/O External Data Memory Read Strobe. Enables the data from an external data memory to Port 0.

20, 34, 48DV DD S Digital supply, 3V or 5V.

21, 35, 47DGND S Digital ground, ground reference point for the digital circuitry.

SCLOCK/D0

I/O

Serial interface clock for the SPI interface. As an input this pin is a Schmitt triggered input and a weak internal pull-up is present on this pin unless it is outputting logic low.

This pin can also be controlled directly in software as a digital output pin.27MOSI/D1I/O

Serial master output/slave input data for the SPI interface. A weak internal pull-up is present on this pin unless it is outputting logic low.

This pin can also be controlled directly in software as a digital output pin.

(12 March 2002) REV. P rC

ADuC834

–20–PRELIMINARY TECHNICAL DATA

Pin No.Mnemonic Type *Description

28–31P2.0–P2.7I/O

Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s 36-39

(A8–A15)written to them are pulled high by the internal pull-up resistors, and in that state can (A16–A23)

be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors.

Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space.

32XTAL1I Input to the crystal oscillator inverter.

33XTAL2O Output from the crystal oscillator inverter. (see page 68 for description)

I/O

External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000h to F800h. When held low this input enables the device to fetch all instructions from external program memory. To determine the mode of code execution, i.e., internal or external, the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle.

EA may also be used as an external emulation I/O pin and therefore the voltage level at this pin must not be changed during normal mode operation as it may cause an emulation interrupt that will halt code execution.

41PSEN O

Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses.This pin remains high during internal program execution.

PSEN can also be used to enable serial download mode when pulled low through a resistor at the end of an external RESET assertion or as part of a device power cycle.42ALE O

Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit data address space accesses) of the address to external memory during external code or data memory access cycles. It is activated every six oscillator periods except during an external data memory access. It can be disabled by setting the PCON.4 bit in the PCON SFR.

43–46P0.0–P0.7I/O

P0.0–P0.7, these pins are part of Port0 which is an 8-bit open-drain bidirectional 49–52

(AD0–AD3)I/O port. Port 0 pins that have 1s written to them float and in that state can be used (AD4–AD7)

as high impedance inputs. An external pull-up resistor will be required on P0outputs to force a valid logic high level externally. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory.In this application it uses strong internal pull-ups when emitting 1s.

*I = Input, O = Output, S = Supply.NOTES

1.In the following descriptions, SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless otherwise stated.

2.In the following descriptions, SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC834 hardware unless otherwise stated.

https://www.wendangku.net/doc/ec5822435.html,er software should not write 1s to reserved or unimplemented bits as they may be used in future products.