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AD8147ACPZ-R2中文资料

Triple Differential Driver

for Wideband Video

AD8146/AD8147/AD8148 Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 https://www.wendangku.net/doc/ea6630121.html, Fax: 781.461.3113 ?2007 Analog Devices, Inc. All rights reserved.

FEATURES

Triple high speed fully differential driver

700 MHz, ?3 dB, 2 V p-p bandwidth (AD8146/AD8148) 600 MHz, ?3 dB, 2 V p-p bandwidth (AD8147)

200 MHz, 0.1 dB, 2 V p-p bandwidth

3000 V/μs slew rate

Fixed gain (AD8146/AD8147: G = 2, AD8148: G = 4) Differential or single-ended input to differential output Can be used as differential-to-differential receiver Drives one or two 100 Ω UTP cables

Adjustable output common-mode voltage (AD8146) Internal common-mode feedback network

Output balance error ?50 dB @ 50 MHz

On-chip, sync-on common-mode encoding (AD8147/AD8148) Output pull-down feature for line isolation

Low power: 57 mA @ 5 V for 3 drivers (AD8146)

Wide supply voltage range: +5 V to ±5 V

Available in a small 4 mm × 4 mm LFCSP

APPLICATIONS

QXGA or 1080p video transmission

KVM networking

Video over unshielded twisted pair (UTP)

Differential signal multiplexing

FUNCTIONAL BLOCK DIAGRAMS

V OCM C

V S+

–IN C

+IN C

V S–

–OUT C

–

T V

–

T V

Figure 1.

OPD

V S–

–IN R

+IN R

V S–

SYNC LEVEL

V S+ (SYNC)

–IN B

+IN B

V S–

–OUT R–OUT B

–

(

)

–

Figure 2.

GENERAL DESCRIPTION

The AD8146/AD8147/AD8148 are high speed triple, differential or single-ended input to differential output drivers. The AD8146 and AD8147 have a fixed gain of 2, and the AD8148 has a fixed gain of 4. They are all specifically designed for the highest resolution component video signals but can be used for any type of analog signals or high speed data transmission over either Category 5 UTP cable or differential printed circuit board (PCB) transmission lines.

These drivers can be used with the AD8145 triple differential-to-singled-ended receiver, and the AD8117 crosspoint switch to produce a video distribution system capable of supporting UXGA or 1080p signals.

Manufactured on the Analog Devices, Inc. second generation XFCB bipolar process, the drivers have large signal bandwidths of 700 MHz and fast slew rates. They have an internal common-mode feedback feature that provides output amplitude and phase matching that is balanced to ?60 dB at 50 MHz, suppressing even-order harmonics and minimizing radiated electromagnetic interference (EMI).

The common-mode voltage of each AD8146 output can be set to any level, allowing transmission of signals over the common-mode voltages. The AD8147 and AD8148 encode the vertical and horizontal sync signals on the common-mode voltages of the outputs. All outputs can be independently set to low voltage states to be used with series diodes for line isolation, allowing easy differential multiplexing over the same twisted pair cable. The AD8146/AD8147/AD8148 are available in a 24-lead LFCSP and operate over a temperature range of ?40°C to +85°C.

AD8146/AD8147/AD8148

Rev. 0 | Page 2 of 24

TABLE OF CONTENTS

Features..............................................................................................1 Applications.......................................................................................1 Functional Block Diagrams.............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Absolute Maximum Ratings............................................................7 Thermal Resistance......................................................................7 ESD Caution..................................................................................7 Pin Configuration and Function Descriptions.............................8 Typical Performance Characteristics...........................................10 Theory of Operation......................................................................14 Definition of Terms....................................................................14 Analyzing an Application Circuit.............................................14 Closed-Loop Gain......................................................................14 Calculating the Input Impedance.............................................15 Input Common-Mode Voltage Range in Single-Supply

Applications................................................................................15 Output Common-Mode Control.............................................15 Sync-On Common-Mode.........................................................15 Applications.....................................................................................16 Driving RGB Video Signals Over Category-5 UTP Cable....16 Video Sync-On Common-Mode..............................................16 Driving Two UTP Cables With One Driver...........................18 Using the AD8146 as a Receiver...............................................18 Output Pull-Down (OPD)........................................................19 Layout and Power Supply Decoupling Considerations.........19 Driving a Capacitive Load.........................................................19 Adding Pre-Emphasis to the AD8148.....................................20 Exposed Paddle (EP)..................................................................21 Outline Dimensions.......................................................................22 Ordering Guide.. (22)

REVISION HISTORY

5/07—Revision 0: Initial Version

AD8146/AD8147/AD8148

Rev. 0 | Page 3 of 24

SPECIFICATIONS

V S = ±5V , V OCM = 0 V (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R L , dm = 200 Ω, unless otherwise noted. T MIN to T MAX = ?40°C to +85°C. Table 1.

Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT AC Dynamic Performance

?3 dB Small Signal Bandwidth V O = 0.2 V p-p,

AD8146 and AD8148/AD8147

900/780 MHz ?3 dB Large Signal Bandwidth V O = 2 V p-p,

AD8146 and AD8148/AD8147

700/600 MHz Bandwidth for 0.1 dB Flatness V O = 2 V p-p,

AD8146 and AD8147/AD8148

200/235 MHz Slew Rate V O = 2 V p-p, 25% to 75% 3000 V/μs Isolation Between Amplifiers f = 10 MHz, between amplifiers,

AD8146 and AD8147/AD8148

?86/?80 dB DIFFERENTIAL INPUT DC Input Common-Mode Voltage Range ?5 to +5 V Input Resistance Differential 1.0 kΩ Single-ended input 1.13 kΩ Input Capacitance Differential 2 pF DC CMRR ΔV OUT, dm /ΔV IN, cm , ΔV IN, cm = ±1 V,

AD8146/AD8147/AD8148

?53/?49/?55 dB DIFFERENTIAL OUTPUT Differential Signal Gain ΔV OUT, dm /ΔV IN, dm ; ΔV IN, dm = ±1 V,

AD8146 and AD8147

1.95

2.00 V/V ΔV OUT, dm /ΔV IN, dm ; ΔV IN, dm = ±1 V, AD8148 ?

3.42 +3.5 V/V Output Voltage Swing Each single-ended output,

AD8146/AD8147/AD8148

?3/?2.25/?3.42 +3.4/+3.4/+3.5 V Output Offset Voltage ?19 +19 mV Output Offset Drift T MIN to T MAX ±8 μV/°C

Output Balance Error ΔV OUT, cm /ΔV IN, dm , ΔV OUT, dm = 2 V p-p,

f = 50 MHz,

AD8146 and AD8147/AD8148

?52/?49 dB DC, AD8146 and AD8148/AD8147 ?41/?44 dB Output Voltage Noise (RTO) f = 1 MHz, AD8146 and AD8147/AD8148 25/42 nV/√Hz Output Short-Circuit Current Short to GND, source/sink +87/?67 mA

V OCM DYNAMIC PERFORMANCE

(AD8146 ONLY) ?3 dB Bandwidth ΔV OCM = 100 mV p-p 340 MHz Slew Rate V OCM = ?1 V to +1 V, 25% to 75% 800 V/μs DC Gain ΔV OCM = ±1 V 0.986 1.000 V/V

V OCM INPUT CHARACTERISTICS

(AD8146 ONLY)

Input Voltage Range ±3 V Input Resistance 12.5 kΩ Input Offset Voltage ?20 +20 mV DC CMRR ΔV OUT, dm /ΔV OCM , ΔV OCM = ±1 V ?48 dB

SYNC DYNAMIC PERFORMANCE

(AD8147/AD8148 ONLY) Slew Rate V OUT, cm = ?1 V to +1 V; 25% to 75% 1000 V/μs

AD8146/AD8147/AD8148

Rev. 0 | Page 4 of 24

Parameter Conditions Min Typ Max Unit

H SYNC AND V SYNC INPUTS

(AD8147/AD8148 ONLY) Input Low Voltage 1.5 to 1.7 V Input High Voltage 1.5 to 1.7 V

SYNC LEVEL INPUT

(AD8147/AD8148 ONLY) Setting to 0.5 V Pulse Levels 0.5 V Gain to Red Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL (AD8147/AD8148) 0.93/0.965 1.08/1.04 V/V Gain to Green Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL (AD8147/AD8148) 1.91/1.935 2.11/2.05 V/V Gain to Blue Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL (AD8147/AD8148) ?1.08/?1.035 ?0.93/?0.965 V/V POWER SUPPLY Operating Range +4.5 ±5.5 V Quiescent Current, Positive Supply AD8146 57 mA AD8147/AD8148 61.5/62.5 mA Disabled, AD8146/AD8147 and AD8148 6/21.5 mA Quiescent Current, Negative Supply AD8146 ?57 mA AD8147/AD8148 ?60.5/?62 mA Disabled ?37 mA PSRR ΔV OUT, dm /ΔV S ; ΔV S = ±1 V

(AD8146/AD8147/AD8148)

?66/?52/?55 dB OUTPUT PULL-DOWN OPD Input Low Voltage 1.1 V OPD Input High Voltage 2.1 V OPD Input Bias Current 520 μA OPD Assert Time 1 μs OPD Deassert Time 10 ns

Output Voltage When OPD Asserted Each output, OPD input @ V S + ?4.2 ?3.8 V

AD8146/AD8147/AD8148

Rev. 0 | Page 5 of 24

V S = +5 V or ±2.5 V; V OCM = midsupply (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R L, dm = 200 Ω, unless otherwise noted. T MIN to T MAX = ?40°C to +85°C. Table 2.

Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT AC Dynamic Performance ?3 dB Small Signal Bandwidth V O = 0.2 V p-p,

AD8146/AD8147 and AD8148

870/680 MHz ?3 dB Large Signal Bandwidth V O = 2 V p-p,

AD8147/AD8146 and AD8148

590/620 MHz Bandwidth for 0.1 dB Flatness V O = 2 V p-p,

AD8146 and AD8147/AD8148

165/200 MHz DIFFERENTIAL INPUT DC Input Common-Mode Voltage Range 0 to 5 V Input Resistance Differential 1.0 kΩ Single-ended input 1.13 kΩ Input Capacitance Differential 2 pF DC CMRR ΔV OUT, dm /ΔV IN, cm ; ΔV IN, cm = ±1 V,

AD8146/AD8147/AD8148

?53/?49/?55 dB DIFFERENTIAL OUTPUT Differential Signal Gain ΔV OUT, dm /ΔV IN, dm ; ΔV IN, dm = ±1 V,

AD8146 and AD8147

1.95

2.013 V/V ΔV OUT, dm /ΔV IN, dm ; ΔV IN, dm = ±1 V, AD8148

3.87

4.00 V/V Output Voltage Swing Each single-ended output

AD8146 and AD8147/AD8148

?1.17/?1.23 +1.24/+1.26 V Output Offset Voltage ?17 +17 mV Output Offset Drift T MIN to T MAX ±8 μV/°C

Output Balance Error ΔV OUT, cm /ΔV IN, dm , ΔV OUT, dm = 2 V p-p,

f = 50 MHz,

AD8146 and AD8147/AD8148

?53/?49 dB DC, AD8146 and AD8148/AD8147 ?41/?44 dB Output Voltage Noise (RTO) f = 1 MHz, AD8146, AD8147/AD8148 25/42 nV/√Hz Output Short-Circuit Current Short to GND, source/sink +63/?48 mA

V OCM DYNAMIC PERFORMANCE

(AD8146 ONLY) ?3 dB Bandwidth ΔV OCM = 100 mV p-p 310 MHz Slew Rate V OCM = ?1 V to +1 V, 25% to 75% 800 V/μs DC Gain ΔV OCM = ±1 V, T MIN to T MAX 0.99 1.00 V/V

V OCM INPUT CHARACTERISTICS

(AD8146 ONLY) Input Voltage Range ±1.2 V Input Resistance 12.5 kΩ Input Offset Voltage ?20 +20 mV DC CMRR ΔV O, dm /ΔV OCM ; ΔV OCM = ±1 V ?42 dB

SYNC DYNAMIC PERFORMANCE

(AD8147/AD8148 ONLY) Slew Rate V OUT, cm = ?1 V to +1 V; 25% to 75% 800 V/μs

H SYNC AND V SYNC INPUTS

(AD8147/AD8148 ONLY) Input Low Voltage 1.3 to 1.5 V Input High Voltage 1.3 to 1.5 V

AD8146/AD8147/AD8148

Rev. 0 | Page 6 of 24

Parameter Conditions Min Typ Max Unit

SYNC LEVEL INPUT

(AD8147/AD8148 ONLY) Setting to 0.5 V Pulse Levels 0.5 V Gain to Red Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL , AD8147/AD8148 0.88/0.925 1.07/1.00 V/V Gain to Green Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL , AD8147/AD8148 1.83/1.85 2.05/2.00 V/V Gain to Blue Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL , AD8147/AD8148 ?1.07/?1 ?0.88/?0.925 V/V POWER SUPPLY Operating Range +4.5 ±5.5 V Quiescent Current Positive Supply AD8146 50 mA AD8147/AD8148 55.5/52 mA Disabled, AD8146/AD8147 and AD8148 4/12 mA Quiescent Current Negative Supply AD8146 ?50 mA AD8147/AD8148 ?55/?51 mA Disabled, AD8146/AD8147/AD8148 ?14/?18.2/?15 mA PSRR ΔV OUT, dm /ΔV S ; ΔV S = ±1 V,

AD8146/AD8147/AD8148

?70/?54/?60 dB OUTPUT PULL-DOWN OPD Input Low Voltage 1.0 V OPD Input High Voltage 2.0 V OPD Input Bias Current 160 μA OPD Assert Time 600 ns OPD Deassert Time 10 ns Output Voltage When OPD Asserted Each output, OPD input @ V S + ?1.71 ?1.6 V

AD8146/AD8147/AD8148

Rev. 0 | Page 7 of 24

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating Supply Voltage 11 V All V OCM ±V S Power Dissipation See Figure 3Input Common-Mode Voltage ±V S Storage Temperature Range ?65°C to +125°C Operating Temperature Range

?40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature

150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is specified for the device soldered in a circuit board in still air. Table 4. Thermal Resistance with the Underside Pad Connected to the Plane

Package Type/PCB Type θJA Unit 24-Lead LFCSP/4-Layer

°C/W

Maximum Power Dissipation

The maximum safe power dissipation in the AD8146/

AD8147/AD8148 package is limited by the associated rise in junction temperature (T J ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the

AD8146/AD8147/AD8148. Exceeding a junction temperature of 175°C for an extended time can result in changes in the silicon devices, potentially causing failure.

The power dissipated in the package (P D ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V S ) times the quiescent current (I S ). The load current consists of differential

and common-mode currents flowing to the loads, as well as currents flowing through the internal differential and common-mode feedback loops. The internal resistor tap used in the common-mode feedback loop places a 4 kΩ differential load on the output. Differential feedback, network resistor values are given in the Theory of Operation section and Applications section. RMS output voltages should be considered when dealing with ac signals. Airflow reduces θJA . In addition, more metal directly in contact with the package leads from metal traces, through holes,

ground, and power planes reduces the θJA . The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a ground plane to achieve the specified θJA .

Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 24-lead LFCSP (57°C/W) package on a JEDEC standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a ground plane. θJA values are approximations.

3.50–40

–20020406080

AMBIENT TEMPERATURE (°C)

M A X I M U M P O W E R D I S S I P A T I O N (W )

3.02.52.01.51.00.506655-021

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

AD8146/AD8147/AD8148

Rev. 0 | Page 8 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1OPD 2V S–3–IN A 4+IN A 5V S–6

–OUT A 15+IN C 16–IN C 17V S+18V OCM C 14V S–

13–OUT C

7+O U T A 8V S +9+O U T B 11V S +12

+O U T C 10–O U T B 1V S –2+I N B 3–I N B 4V S +0V O C M A 9

V O C M B 06655-004

Figure 4. AD8146 Pin Configuration

Table 5. AD8146 Pin Function Descriptions

Pin No. Mnemonic Description 1 OPD Output Pull-Down. 2, 5, 14, 21 V S?Negative Power Supply Voltage. 3 ?IN A Inverting Input, Amplifier A. 4 +IN A Noninverting Input, Amplifier A. 6 ?OUT A Negative Output, Amplifier A. 7 +OUT A Positive Output, Amplifier A. 8, 11, 17, 24 V S+Positive Power Supply Voltage. 9 +OUT B Positive Output, Amplifier B. 10 ?OUT B Negative Output, Amplifier B. 12 +OUT C Positive Output, Amplifier C. 13 ?OUT C Negative Output, Amplifier C. 15 +IN C Noninverting Input, Amplifier C. 16 ?IN C Inverting Input, Amplifier C. 18 V OCM C The voltage applied to this pin controls output common-mode voltage, Amplifier C. 19 V OCM B The voltage applied to this pin controls output common-mode voltage, Amplifier B. 20 V OCM A The voltage applied to this pin controls output common-mode voltage, Amplifier A. 22 +IN B Noninverting Input, Amplifier B. 23 ?IN B Inverting Input, Amplifier B.

AD8146/AD8147/AD8148

Rev. 0 | Page 9 of 24

1OPD 2V S–3–IN R 4+IN R 5V S–6

–OUT R

+IN B –IN B V S+ (SYNC)SYNC LEVEL V S–

–OUT B

7+O U T R 8V S +9+O U T G 11V S +12

+O U T B 10–O U T G 1V S – (S Y N C )2+I N G 3–I N G 4V S +0V S Y N C 9

H S Y N C

06655-005

Figure 5. AD8147/AD8148 Pin Configuration

Table 6. AD8147/AD8148 Pin Function Descriptions

Pin No. Mnemonic Description 1 OPD Output Pull-Down. 2, 5, 14 V S?Negative Power Supply Voltage. 3 ?IN R Inverting Input, Red Amplifier. 4 +IN R Noninverting Input, Red Amplifier. 6 ?OUT R Negative Output, Red Amplifier. 7 +OUT R Positive Output, Red Amplifier. 8, 11, 24 V S+Positive Power Supply Voltage. 9 +OUT G Positive Output, Green Amplifier. 10 ?OUT G Negative Output, Green Amplifier. 12 +OUT B Positive Output, Blue Amplifier. 13 ?OUT B Negative Output, Blue Amplifier. 15 +IN B Noninverting Input, Blue Amplifier. 16 ?IN B Inverting Input, Blue Amplifier. 17 V S+ (SYNC) Positive Power Supply Voltage for Sync. 18 SYNC LEVEL The voltage applied to this pin controls the amplitude of the sync pulses that are applied to

the common-mode voltages.

19 H SYNC Horizontal Sync Pulse Input. 20 V SYNC Vertical Sync Pulse Input. 21 V S? (SYNC) Negative Power Supply Voltage for Sync. 22 +IN G Noninverting Input, Green Amplifier. 23 ?IN G Inverting Input, Green Amplifier. Exposed Paddle GND Signal Ground Reference.

AD8146/AD8147/AD8148

Rev. 0 | Page 10 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

V S = ±5V; V OCM = 0 V (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R L , dm = 200 Ω; C L, dm = 0 pF, unless otherwise noted. T MIN to T MAX = ?40°C to +85°C.

9–110

1000

FREQUENCY (MHz)

G A I N (d B )

100

876

543210

06655-010

Figure 6. AD8146/AD8147 Large Signal Frequency Response for Various Supplies

1000

FREQUENCY (MHz)

G A I N (d B )

100

06655-011

Figure 7. AD8146/AD8147 Small Signal Frequency Response for Various Supplies

6.55.5

11000

FREQUENCY (MHz)

G A I N (d B )

101006.46.36.2

6.16.05.95.85.75.6

06655-012

Figure 8. AD8146/AD8147 Large Signal 0.1 dB Flatness for Various Supplies

510

1000

FREQUENCY (MHz)

G A I N (d B )

100

14131211109876

06655-013

Figure 9. AD8148 Large Signal Frequency Response for Various Supplies

15510

1000

FREQUENCY (MHz)

G A I N (d B )

100

141312

11109

876

06655-014

Figure 10. AD8148 Small Signal Frequency Response for Various Supplies

12.5

11.5

1000

FREQUENCY (MHz)

G A I N (d B )

100

12.412.312.2

12.112.011.9

11.811.711.6

06655-015

Figure 11. AD8148 Large Signal 0.1 dB Flatness for Various Supplies

AD8146/AD8147/AD8148

Rev. 0 | Page 11 of 24

TIME (ns)

V O L T A G E (V )

–1.5020–0.5–1.02468101214161806655-016

TIME (ns)

V O L T A G E (m V )

Figure 12. AD8146/AD8147 Large Signal Transient Response for Various Supplies

150

–150020100

–50–1002468101214161806655-017

Figure 13. AD8146/AD8147 Small Signal Transient Response for Various Supplies

–20–70

106655-024

1.5

–1.5

020

TIME (ns)

V O L T A G E (V )

000

FREQUENCY (MHz)

O U T P U T B A L A N C E E R R O R (d B )

100

–25

–30–35–40–45–50–55

–60–65

Figure 14. Output Balance vs. Frequency

1.00.5

–0.5

–1.0

2468101214161806655-019

150

–150

020

TIME (ns)

V O L T A G E (m V )

Figure 15. AD8148 Large Signal Transient Response for Various Supplies

100

–50

–100

06655-020

24681012141618

Figure 16. AD8148 Small Signal Transient Response for Various Supplies

–20

–80

11000

FREQUENCY (MHz)

C O M M O N -M O

E R E J E C T I O N (d B

)

10100–30

–40

–50

–60

–70

Figure 17. CMRR vs. Frequency

AD8146/AD8147/AD8148

Rev. 0 | Page 12 of 24

–20–100

0.1

1000

FREQUENCY (MHz)

P O W E R S U P P L Y R E J E C T I O N (d B )

110

100–30

–40–50

–60–70–80

–90

06655-028

Figure 18. Positive Power Supply Rejection vs. Frequency

1000

100.01

100000FREQUENCY (kHz)

N O I S E (n H z )

0.1110100100010000100

Figure 19. Output-Referred Voltage Noise vs. Frequency

1000TIME (ns)

V O L T A G E (V )

100

200

300

400

500

600

700

800

900

Figure 20. AD8146/AD8147 Output Overdrive Recovery

–20–110

0.1

1000

FREQUENCY (MHz)

P O W E R S U

P P L Y R E J E C T I O N (d B )

110

100–30

–40

–50–60–70

–80–90

–100

Figure 21. Negative Power Supply Rejection vs. Frequency

–20–120

0.1

1000

FREQUENCY (MHz)

I S O L A T I O N (d B )

100

–30–40

–50

–60–70

–80–90

–100–110

Figure 22. Amplifier-to-Amplifier Isolation vs. Frequency

1000

TIME (ns)

V O L T A G E (V )

100

200

300

400

500

600

700

800

900

Figure 23. AD8148 Output Overdrive Recovery

AD8146/AD8147/AD8148

Rev. 0 | Page 13 of 24

5945–60

120TEMPERATURE (°C)

S U P P L Y C U R R E N T (m A )

5553

514947–40–20020406080

10006655-054

6248–60

120

TEMPERATURE (°C)

S U P P L Y C U R R E N T (m A )

565452

50–40–20020406080

100

Figure 24. AD8146 Supply Current vs. Temperature

Figure 26. AD8147/AD8148 Supply Current vs. Temperature

–35

–65

11000

FREQUENCY (MHz)

V O C M C M R R (d B )

100–40

–45

–50

–55

–60

1.5

–1.5

04TIME (ns)

V O L T A G E (V )

1.0

0.5

–0.5

–1.0

5101520253035

Figure 27. AD8146 Large Signal V OCM Transient Response for Various Supplies

Figure 25. V OCM Common-Mode Rejection Ratio

AD8146/AD8147/AD8148

Rev. 0 | Page 14 of 24

THEORY OF OPERATION

Each differential driver differs from a conventional op amp in that it has two outputs whose voltages move in opposite directions. Like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. The drivers make it easy to perform single-ended-to-differential conversion, common-mode level shifting, and amplification of differential signals.

Previous differential drivers, both discrete and integrated designs, were based on using two independent amplifiers and two independent feedback loops, one to control each of the outputs. When these circuits are driven from a single-ended source, the resulting outputs are typically not well balanced. Achieving a balanced output has typically required exceptional matching of the amplifiers and feedback networks.

DC common-mode level shifting has also been difficult with previous differential drivers. Level shifting has required the use of a third amplifier and feedback loop to control the output common-mode level. Sometimes, the third amplifier was also used to attempt to correct an inherently unbalanced circuit. Excellent performance over a wide frequency range has proven difficult with this approach.

Each of the drivers uses two feedback loops to separately control the differential and common-mode output voltages. The differential feedback, set by the internal resistors, controls only the differential output voltage. The internal common-mode feedback loop controls only the common-mode output voltage. This architecture makes it easy to transmit signals over the common-mode voltage channels by simply applying the signal voltages to the V OCM inputs. The output common-mode voltage is forced, by internal common-mode feedback, to equal the voltage applied to the V OCM input, without affecting the differential output voltage.

The driver architecture results in outputs that are highly balanced over a wide frequency range without requiring external components or adjustments. The common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. The result is nearly perfectly balanced differential outputs of identical amplitude that are exactly 180° apart in phase.

DEFINITION OF TERMS

Differential Voltage

Differential voltage refers to the difference between two node voltages that are balanced with respect to each other. For example, in Figure 28 the output differential voltage (or equivalently output differential mode voltage) is defined as

V OUT, dm = (V OP ? V ON )

Common-Mode Voltage

Common-mode voltage refers to the average of two node voltages with respect to a common reference. The output common-mode voltage is defined as

V OUT, cm = (V OP + V ON )/2 Output Balance

Output balance is a measure of how well the differential output signals are matched in amplitude and how close they are to exactly 180° apart in phase. Balance is most easily determined by placing a well-matched resistor divider between the differential output voltage nodes and comparing the magnitude of the signal at the divider’s midpoint with the magnitude of the differential signal. By this definition, output balance error is the magnitude of the change in output common-mode voltage divided by the magnitude of the change in output differential mode voltage in response to a differential input signal.

OUT cm OUT V V Error Balance Output ,,ΔΔ=

ANALYZING AN APPLICATION CIRCUIT

The drivers use high open-loop gain and negative feedback to force their differential and common-mode output voltages to minimize the differential and common-mode input error voltages. The differential input error voltage is defined as the voltage between the differential inputs labeled V AP and V AN in Figure 28. For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to V OCM can also be assumed to be zero. Starting from these two assumptions, any application circuit can be analyzed.

CLOSED-LOOP GAIN

The differential mode gain of the circuit in Figure 28 can be described by

IN,dm OUT,R R V V =

where:

R F is 1.0 kΩ and R G is 500 Ω nominally for the AD8146 and AD8147.

R F is 2.0 kΩ and R G is 500 Ω nominally for the AD8148.

V V +

V IN, dm –V ON

OUT, dm 06655-006

Figure 28. Internal Architecture and Signal Name Definitions

AD8146/AD8147/AD8148

Rev. 0 | Page 15 of 24

CALCULATING THE INPUT IMPEDANCE

OUTPUT COMMON-MODE CONTROL

The AD8146 allows the user to control each of the three

common-mode output levels independently through the three V OCM input pins. The V OCM pins pass a signal to the common-mode output level of each of their respective amplifiers with 330 MHz of small signal bandwidth and an internally fixed gain of 1. In this way, additional control and communication signals can be embedded on the common-mode levels as users see fit. The effective input impedance of a circuit such as that in Figure 28 at V IP and V IN depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, the differential input impedance, R IN, dm , between the inputs V IP and V IN for all devices is

R IN, dm = 2 × R G

In the case of a single-ended input signal (for example, if V IN is grounded and the input signal is applied to V IP ), the input impedance becomes

With no external circuitry, the level at the V OCM input of each amplifier defaults to approximately midsupply. An internal resistive divider with an impedance of approximately 12.5 kΩ sets this level. To limit common-mode noise in dc common-mode applications, external bypass capacitors should be connected from each of the V OCM input pins to ground.

()?

?????????

+×?=

F G F

IN,R R R R R 21 SYNC-ON COMMON-MODE

The single-ended input impedance of the AD8146 and the AD8147 is therefore 750 Ω, and the single-ended input impedance of the AD8148 is 833 Ω.

The AD8147 and AD8148 are specifically targeted at driving

RGB video signals over UTP cable using a sync-on common-mode technique. The common-mode outputs of each of the R, G, and B differential outputs are set using circuitry contained within the device. This circuitry embeds the horizontal and vertical sync pulses on the three common-mode outputs in a way that also results in low radiated energy. For a more detailed description of the sync scheme, see the Applications section. The input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor R G .

The sync-on common-mode circuit generates a current based on the SYNC LEVEL input pin (Pin 18). With the SYNC LEVEL input tied to GND, the common-mode output of all drivers is set at (V S+ + V S?)/2. Using a resistor divider, a voltage can be applied between GND and SYNC LEVEL that determines the maximum deviation of the common-mode outputs from their midsupply level. If, for instance, SYNC LEVEL = 0.5 V and the supply voltage is 5 V , the common-mode outputs fall within an envelope of 2.5 V ± 0.5 V . The state of each V OUT, cm output based on the H SYNC and V SYNC inputs is determined by the equations defined in the Applications section.

INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE-SUPPLY APPLICATIONS

The driver inputs are designed to facilitate level-shifting of ground-referenced input signals on a single power supply. For a single-ended input, this implies, for example, that the voltage at V IN in Figure 28 would be 0 V when the negative power supply voltage of the amplifier is also set to 0 V .

It is important to ensure that the common-mode voltage at the amplifier inputs, V AP and V AN , stays within its specified range. Because voltages V AP and V AN are driven to be essentially equal by negative feedback, the input common-mode voltage of the amplifier can be expressed as a single term, V ACM . V ACM can be calculated as

In most cases, the sync-on common-mode circuit can be used by directly applying the H SYNC and V SYNC signals to their respective AD8147 or AD8148 inputs. The logic thresholds of the H SYNC and V SYNC inputs are set to nominally 1.4 V with respect to GND, and the exposed paddles of the AD8147 and AD8148 are used as the GND references for the incoming sync pulses. When ±2.5 V supplies are used, however, external protection is required to limit the positive excursion to less than 2.5 V . For more details, see the Applications section.

2ICM

OCM ACM V V V +=

where V ICM is the common-mode voltage of the input signal, that is, V ICM = (V IP + V IN )/2.

The input paths from the H SYNC and V SYNC inputs to the switches in the current mode level-shifting circuit are well matched to eliminate false switching transients, maximizing common-mode balance and minimizing radiated energy.

AD8146/AD8147/AD8148

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APPLICATIONS

DRIVING RGB VIDEO SIGNALS OVER CATEGORY-5 UTP CABLE

The foremost application of the drivers is the transmission of RGB video signals over UTP cable in KVM networks. The

excellent balance of the differential outputs ensures low radiated energy from each of the twisted pairs. Single-ended video signals are easily converted to differential signals for transmission over the cable, and the internally fixed gain of 2 or 4 automatically compensates for the losses incurred by the source and load terminations. The common topologies used in KVM networks, such as daisy-chained, star, and point-to-point, are supported by the drivers. Figure 29 shows the AD8146 in a triple single-ended-to-differential application when driven from a 75 Ω source, which is typical of how RGB video is driven over an UTP cable.

–+

06655-007

Figure 29. AD8146 in Single-Ended-to-Differential Application

VIDEO SYNC-ON COMMON-MODE

In computer video applications, the horizontal and vertical sync signals are often separate from the video information signals. For example, in typical computer monitor applications, the red, green, and blue (RGB) color signals are transmitted over separate cables, as are the vertical and horizontal sync signals. When transmitting these types of video signals over long distances on UTP cable, it is desirable to reduce the required number of physical channels. One way to do this is to encode the vertical and horizontal sync signals as weighted sums and differences of the output common-mode signals. The RGB color signals are each transmitted differentially over separate physical channels. The fact that the differential and common-mode signals are orthogonal allows the RGB color and sync signals to be separated at the channel’s receiver.

Cat-5 cable contains four balanced twisted-pair physical

channels that can support both differential and common-mode signals. Transmitting typical computer monitor video over this cable can be accomplished by using three of the twisted pairs for the RGB and sync signals and one wire of the fourth pair as a return path for the Schottky diode bias currents. Each color is transmitted differentially, one on each of the three pairs, and the encoded sync signals are transmitted among the common-mode signals of each of the three pairs. To minimize EMI from the sync signals, the common-mode signals on each of the three pairs produced by the sync encoding scheme induce electric and magnetic fields that for the most part cancel each other. A conceptual block diagram of the sync encoding scheme is presented in Figure 30. Because the AD8147/AD8148 have the sync encoding scheme implemented internally, the user simply applies the horizontal and vertical sync signals to the appropriate inputs. (See the Specifications tables for the high and low levels of the horizontal and vertical sync pulse voltages).

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Rev. 0 | Page 17 of 24

–OUT R

+OUT R

–OUT G

+OUT G

–OUT B

+OUT B

V OCM WEIGHTING EQUATIONS:

RED V OCM =K (V SYNC – H SYNC ) + V MIDSUPPLY

GREEN V OCM =K (–2V SYNC ) + V MIDSUPPLY

BLUE V OCM =K (V SYNC + H SYNC ) + V MIDSUPPLY

+IN R

–IN R V SYNC

H SYNC

SYNC LEVEL

+IN G

–IN G

+IN B

–IN B

OPD

06655-008

Figure 30. AD8147/AD8148 Sync-On Common-Mode Encoding Scheme

00.5

1.01.5

2.04.0

3.5

4.52.53.0

5.0

TIME (μs)

2.02.1

2.22.3

2.4

2.92.8

3.0

2.52.62.7

3.1

V O L T S

Figure 31. AD8147 Sync-On Common-Mode Signals in Single 5 V Application

The transmitted common-mode sync signal magnitudes are scaled by applying a dc voltage to the SYNC LEVEL input, referenced to GND. The difference between the voltage applied to the SYNC LEVEL input and GND sets the peak deviation of the encoded sync signals about the midsupply, common-mode voltage. For example, with the SYNC LEVEL input set at 500 mV , the deviation of the encoded sync pulses about the nominal midsupply, common-mode voltage is typically ±500 mV . The equations in Figure 30 describe how the V SYNC and H SYNC signals are encoded on each color’s midsupply common-mode signal. In these equations, the weights of the V SYNC and H SYNC signals are ±1 (+1 for high and ?1 for low), and the constant K is equal to the peak deviation of the encoded sync signals.

Figure 31 shows how the sync signals appear on each common-mode voltage in a single 5 V supply application when the voltage applied to the SYNC LEVEL input is 500 mV , which is the typical setting for most applications.

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Sync pulse amplitudes applied to the AD8147 and AD8148 must be less than or equal to the positive supply voltage. In low positive supply applications, such as those that use ±2.5 V supplies, external limiting may be required because many logic families produce amplitudes up to 5 V . Figure 32 illustrates how to use a monolithic triple diode to limit a sync pulse with 5 V amplitude to an amplitude of approximately 2 V .

Driver bandwidth is affected to a small degree when driving the 100 Ω load presented by the two cables, as compared with driving a typical 200 Ω load. Figure 34 illustrates the AD8146/ AD8147/AD8148 bandwidths when driving a 100 Ω load.

–3FREQUENCY (MHz)

G A I N (d B )

1000

100

+5V

INCOMING SYNC PULSE 0V

+2V

LIMITED SYNC PULSE 06655-036

Figure 32. Limiting Sync Pulse Amplitude in Low Positive Supply Applications

DRIVING TWO UTP CABLES WITH ONE DRIVER

Some applications require driving two UTP cables with a single driver. Each individual driver of the AD8146/AD8147/AD8148 is capable of driving two doubly terminated cables, which places a differential load of 100 Ω across the outputs of the driver. Figure 33 illustrates how to drive two cables.

Figure 34. Large Signal Frequency Response Driving 100 Ω Loads

USING THE AD8146 AS A RECEIVER

While the AD8146 excels as a differential driver, it can also be used as a differential-to-differential receiver applied as an

input buffer that protects a more sophisticated device, such as a differential crosspoint switch. See Figure 35 for an illustration of this type of application.

06655-034

Because the AD8146 V OCM input pins are uncommitted, any incoming common-mode signal, such as encoded sync pulses, can be reproduced at the AD8146 outputs by stripping it from the received signal and applying it directly to the V OCM pin. The two series 54.9 Ω resistors form a differential termination resistor of 109.8 Ω, which when loaded with the 1 kΩ differential input resistance of the AD8146, provides an overall termination of approximately 100 Ω. The received common-mode voltages are available at the center taps between the two resistors. Figure 33. Driving Two UTP Cables With One Driver

AD8146/AD8147/AD8148

Rev. 0 | Page 19 of 24

RED CHANNEL GREEN CHANNEL BLUE CHANNEL V = +2.5V

VNEG = –2.5V

S–06655-035

Figure 35. Using the AD8146 as a Differential Receiver

Terminations are not required between the AD8146 and the switch if the interconnection lengths are kept short (less than two inches). The 10 Ω series resistors buffer the input

capacitance of the switch (typically 2 pF) and produce a low-pass rolloff that is down by only 0.025 dB at 600 MHz.

OUTPUT PULL-DOWN (OPD)

The output pull-down feature, when used in conjunction with series Schottky diodes, offers a convenient means to multiplex a number of driver outputs together to form a video network. The OPD pin is a binary input that controls the state of the outputs. Its binary input level is referenced to GND (see the Specifications section for the logic levels). When the OPD input is driven to its low state, the output is enabled and operates in normal fashion. In this state, the V OCM input can be used to provide a positive bias on the series diodes, allowing the drivers to transmit signals over the network. When the OPD input is driven to its high state, the outputs of the drivers are forced to a low voltage, irrespective of the level on the V OCM input, reverse-biasing the series diodes and thus presenting high impedance to the

network. This feature allows a three-state output to be realized that maintains its high impedance state even when the drivers are not powered.

It is recommended that the output pull-down feature only be used in conjunction with series diodes in such a way as to ensure that the diodes are reverse-biased when the output pull-down feature is asserted, because some loading conditions can prevent the output voltage from being pulled all the way down.

LAYOUT AND POWER SUPPLY DECOUPLING CONSIDERATIONS

Standard high speed PCB layout practices should be adhered to when designing with the drivers. A solid ground plane is required and good wideband power supply decoupling networks should be placed as close as possible to the supply pins. Small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling.

Source termination resistors on the differential outputs must be placed as close as possible to the output pins to minimize load capacitance due to the PCB traces.

DRIVING A CAPACITIVE LOAD

A purely capacitive load can react with the output impedance of any amplifier to produce an undesirable phase shift, which reduces phase margin and results in high frequency ringing in the pulse response. The best way to minimize this effect is to place a small resistor in series with each of the outputs of the amplifier to buffer the load capacitance. Most applications include 49.9 Ω source termination resistors, which effectively buffer any stray load capacitance.

AD8146/AD8147/AD8148

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Under no circumstances should capacitance be intentionally added to an output to introduce frequency domain peaking. Figure 36 and Figure 37 illustrate how adding just 5 pF of excessive load capacitance influences time and frequency domain responses.

–2.0

0TIME (ns)

V O L T A G E (V )

–0.5–1.0–1.52468101214161806

655-031

Figure 36. Large Signal Transient Responses at Various Capacitive Loads

12210

1000

FREQUENCY (MHz)

G A I N (d B )

100

11109

876543

06655-032

Figure 37. Large Signal Frequency Responses at Various Capacitive Loads

While high frequency peaking is desirable in some cable equalization applications, it should be implemented using

methods that do not compromise the stability of the driver and that do not depend on amplifier parasitic elements. The parasitic elements are affected by process variations and cannot be depended upon for circuit designs. The amplifier may break into oscillation when excess load capacitance is intentionally added. For more information on this topic, see the Adding Pre-Emphasis to the AD8148 section for a description on how to introduce a controlled amount of pre-emphasis for 30 meters of UTP using the AD8148.

ADDING PRE-EMPHASIS TO THE AD8148

UTP cables exhibit loss characteristics that are low pass in nature and are exponential functions of the square root of the frequency. Over wideband video bandwidths, the losses are predominantly due to the skin effect, which causes the resistance of the cable to increase with frequency. Even though the loss characteristics are nonlinear, suitable linear networks can be designed to approximately compensate for the losses.

Placing the compensation network at the transmitting end of the cable is referred to as pre-emphasis, because the higher frequencies are emphasized, or boosted, before they are sent, to compensate for the low-pass response of the cable. Because the higher frequencies experience more loss than the lower frequencies as they pass through the cable, the high and low frequencies arrive at approximately the same level and at the end of the cable when a properly designed pre-emphasis network is used at the transmitter. The ideal cascaded frequency response of the pre-emphasis network and the cable is therefore nominally flat. Because the AD8148 has an internally set, closed-loop gain of 4 (12 dB), it is possible to reduce the gain at low frequencies using external frequency selective components, then use these components to provide increasing gain with increasing

frequency, back to a value close to 12 dB. These components, along with the AD8148, form the pre-emphasis network. When properly designed, the combined frequency response of the pre-emphasis network and cable is approximately flat with a gain of 2 (6 dB). Figure 38 illustrates how to construct a pre-emphasis network using the AD8148 that compensates for 30 meters of UTP cable. The network in the lower leg is required to match the transfer function of the two feedback loops.

At dc, the capacitors are open circuits, and the network has a gain of approximately 6.5 dB. (The additional 0.5 dB is added to compensate for the cable flat loss that occurs at frequencies below where the skin effect begins to take effect.) Moving up in frequency, the 30 pF capacitor begins to take effect and introduces a zero into the frequency response, causing the gain to increase with frequency. Continuing to move up in frequency, the 30 pF capacitor becomes an effective short, and the 487 Ω resistor goes in parallel with the 442 Ω resistor, forming a pole in the response. Continuing to move up in frequency, the 15 pF capacitor takes effect, introducing another zero, and causes the gain to further increase with frequency until it becomes an effective short, and the gain starts to flatten out until the amplifier response begins to roll off. The gain does not reach 12 dB before the amplifier begins to roll off because the 12 dB value is a high frequency asymptote. The pole and zero locations cited in the previous discussion are qualitative, but the discussion describes the basic principles involved with the operation of the pre-emphasis network.