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March 2004s
HIGH SPEED :
f MAX =67MHz (TYP.)at V CC =6V s
LOW POWER DISSIPATION:I CC =2μA(MAX.)at T A =25°C s
HIGH NOISE IMMUNITY:
V NIH =V NIL =28%V CC (MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:|I OH |=I OL =4mA (MIN)
s
BALANCED PROPAGATION DELAYS:t PLH ?t PHL
s
WIDE OPERATING VOLTAGE RANGE:V CC (OPR)=2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH 54SERIES 109
s SPACE GRADE-1:ESA SCC QUALIFIED s
50krad QUALIFIED,100krad AVAILABLE ON REQUEST
s
NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION
s
DEVICE FULLY COMPLIANT WITH SCC-9306-048
DESCRIPTION
The M54HC109is an high speed CMOS DUAL J-K FLIP FLOP WITH PRESET AND CLEAR fabricated with silicon gate C 2MOS technology.In accordance with the logic level on the J and K
input this device changes state on positive going transition of the clock pulse.CLEAR and PRESET are independent of the clock and are accomplished by a logic low on the corresponding input.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
M54HC109
RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND
CLEAR
PIN CONNECTION
ORDER CODES
PACKAGE FM EM DILC M54HC109D M54HC109D1FPC
M54HC109K
M54HC109K1
M54HC109
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IEC LOGIC SYMBOLS
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
PIN N°SYMBOL NAME AND FUNCTION 1,151CLR,2CLR Asynchronous Reset Direct Input
2,14,3,131J,2J,1K,
2K Synchronous Inputs;Flip-Flops 1and 24,121CK,2CK Clock Input
5,111PR,2PR Asynchronous Set Direct Input (Active Low)6,101Q,2Q True Flip-Flop Outputs 7,91Q,2Q Complement Flip-Flop Outputs
8GND Ground (0V)
16
Vcc
Positive Supply Voltage
M54HC109
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LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur.Functional operation under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter
Value Unit V CC Supply Voltage -0.5to +7V V I DC Input Voltage
-0.5to V CC +0.5V V O DC Output Voltage -0.5to V CC +0.5
V I IK DC Input Diode Current ±20mA I OK DC Output Diode Current ±20mA I O
DC Output Current
±25mA I CC or I GND DC V CC or Ground Current
±50mA P D Power Dissipation
300mW T stg Storage Temperature -65to +150
°C T L
Lead Temperature (10sec)
265
°C
Symbol Parameter
Value Unit V CC Supply Voltage 2to 6V V I Input Voltage 0to V CC V V O Output Voltage 0to V CC V T op Operating Temperature -55to 125°C t r ,t f
Input Rise and Fall Time
V CC =2.0V 0to 1000ns V CC =4.5V 0to 500ns V CC =6.0V
0to 400
ns
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DC SPECIFICATIONS
Symbol
Parameter
Test Condition
Value Unit
V CC (V)T A =25°C -40to 85°C -55to 125°C Min.Typ.
Max.
Min.Max.
Min.Max.
V IH
High Level Input Voltage 2.0 1.5 1.5 1.5V 4.5 3.15 3.15 3.156.0 4.2
4.2
4.2
V IL
Low Level Input Voltage
2.00.50.50.5V
4.5 1.35 1.35 1.356.0 1.8
1.8
1.8V OH
High Level Output Voltage
2.0I O =-20μA 1.9 2.0 1.9 1.9V
4.5I O =-20μA 4.4 4.5 4.4 4.46.0I O =-20μA
5.9
6.0 5.9 5.94.5I O =-4.0mA 4.18 4.31 4.13 4.106.0
I O =-5.2mA 5.68
5.8 5.63
5.60
V OL
Low Level Output Voltage
2.0I O =20μA 0.00.10.10.1V 4.5I O =20μA 0.00.10.10.16.0I O =20μA 0.00.10.10.14.5I O =4.0mA 0.170.260.330.406.0
I O =5.2mA 0.18
0.260.330.40I I Input Leakage Current
6.0V I =V CC or GND ±0.1±1±1μA I CC
Quiescent Supply Current
6.0
V I =V CC or GND
2
20
40
μA
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AC ELECTRICAL CHARACTERISTICS (C L =50pF,Input t r =t f =6ns)
CAPACITIVE CHARACTERISTICS
1)C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.(Refer to Test Circuit).Average operating current can be obtained by the following equation.I CC(opr)=C PD x V CC x f IN +I CC /2(per FLIP/FLOP)
Symbol
Parameter
Test Condition
Value Unit
V CC (V)T A =25°C -40to 85°C -55to 125°C Min.
Typ.Max.Min.
Max.Min.
Max.t TLH t THL Output Transition
Time 2.0307595110ns 4.581519226.07131619t PLH t PHL Propagation Delay
Time (CK -Q,Q) 2.050150190225ns
4.5163038456.013263238t PLH t PHL Propagation Delay
Time (CLR,PR -Q,Q) 2.050150190225ns
4.5163038456.01326
32
38
f MAX
Maximum Clock Frequency 2.0 6.2175 4.2MHz
4.5315925216.037
6730
25
t W(H)t W(L)Minimum Pulse Width (CK) 2.0157595110ns
4.561519226.06131619t W(L)
Minimum Pulse Width (CLR,PR) 2.0157595110ns
4.561519226.06131619t s
Minimum Set-Up Time
2.0177595110ns
4.551519226.04
131619t h
Minimum Hold Time
2.0000ns
4.50006.0000t REM
Minimum Removal Time (CLR,PR)
2.013506575ns
4.541013156.0
3
9
11
13
Symbol
Parameter
Test Condition
Value Unit
V CC (V)T A =25°C -40to 85°C -55to 125°C Min.
Typ.Max.Min.
Max.Min.
Max.C IN Input Capacitance 5.0510
10
10
pF C PD
Power Dissipation Capacitance (note 1)
5.0
41
pF
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TEST CIRCUIT
L
R T =Z OUT of pulse generator (typically 50?)
WAVEFORM 1:PROPAGATION DELAY TIMES,SETUP AND HOLD TIMES,MINIMUM PULSE WIDTH (CK)(f=1MHz;50%duty cycle)
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WAVEFORM 2:PROPAGATION DELAY TIMES ,MINIMUM PULSE WITDTH (CLR),(PR)(f=1MHz;50%duty cycle)
WAVEFORM 3:MINIMUM REMOVAL TIME (CLR to CK)(f=1MHz;50%duty cycle)
WAVEFORM 4:MINIMUM REMOVAL TIME (PR to CK)(f=1MHz;50%duty
cycle)
M54HC109
DILC-16 MECHANICAL DATA
mm.inch DIM.
MIN.TYP MAX.MIN.TYP.MAX.
A 2.1 2.710.0830.107
a1 3.00 3.700.1180.146 a20.630.88 1.140.0250.0350.045
B 1.82 2.390.0720.094
b0.400.450.500.0160.0180.020 b10.200.2540.300.0080.0100.012 D20.0620.3220.580.7900.8000.810 e7.367.627.870.2900.3000.310 e1 2.540.100
e217.6517.7817.900.6950.7000.705 e37.627.878.120.3000.3100.320 F7.297.497.700.2870.2950.303
I 3.830.151
K10.9012.10.4290.476 L 1.14 1.50.0450.059
0056437F
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M54HC109
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