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LM1881M-X_1154165

LM1881M-X_1154165
LM1881M-X_1154165

LM1881,LM1881-X Video Sync Separator

General Description

The LM1881Video sync separator extracts timing informa-tion including composite and vertical sync,burst/back porch timing,and odd/even field information from standard nega-tive going sync NTSC,PAL*and SECAM video signals with amplitude from 0.5V to 2V p-p.The integrated circuit is also capable of providing sync separation for non-standard,faster horizontal rate video signals.The vertical output is produced on the rising edge of the first serration in the vertical sync period.A default vertical output is produced after a time delay if the rising edge mentioned above does not occur within the externally set delay period,such as might be the case for a non-standard video signal.

Features

n AC coupled composite input signal n >10k ?input resistance

n <10mA power supply drain current n Composite sync and vertical outputs n Odd/even field output

n Burst gate/back porch output n Horizontal scan rates to 150kHz n Edge triggered vertical output

n

Default triggered vertical output for non-standard video signal (video games-home computers)n -40?C to +85?C operation (LM1881-X)Connection Diagram

LM1881N

00915001

Order Number LM1881M or LM1881N (0?C to +70?C)Order Number LM1881M-X or LM1881N-X (-40?C to +85?C)

See NS Package Number M08A or N08E

*PAL in this datasheet refers to European broadcast TV standard “Phase Alternating Line”,and not to Programmable Array Logic.

June 2003

LM1881,LM1881-X Video Sync Separator

?2003National Semiconductor Corporation https://www.wendangku.net/doc/eb10358966.html,

Absolute Maximum Ratings

(Note 1)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage 13.2V

Input Voltage

3V P-P (V CC =5V)6V P-P (V CC ≥8V)

Output Sink Currents;Pins,1,3,55mA Output Sink Current;Pin 7

2mA

Package Dissipation (Note 2)1100mW

Storage Temperature Range ?65?C to +150?C

ESD Susceptibility (Note 3)2kV Soldering Information

Dual-In-Line Package (10sec.)260?C Small Outline Package Vapor Phase (60sec.)215?C Infrared (15sec.)

220?C

Electrical Characteristics LM1881

V CC =5V;R SET =680k ?;T A =0?C to +70?C by correlation with 100%electrical testing at T A =25?C

Parameter

Conditions

Min

Typ (Note 4)

Max Units Supply Current Outputs at Logic 1V CC =5V V CC =12V

5.25.51012mA DC Input Voltage Pin 2 1.3 1.5 1.8V Input Threshold Voltage (Note 5)557085mV Input Discharge Current Pin 2;V IN =2V 61116

μA Input Clamp Charge Current Pin 2;V IN =1V 0.20.8mA R SET Pin Reference Voltage Pin 6;(Note 6) 1.10 1.22 1.35V Composite Sync.&Vertical Outputs

I OUT =40μA;Logic 1V CC =5V V CC =12V 4.011.0 4.5V I OUT =1.6mA Logic 1

V CC =5V V CC =12V 2.410.0 3.6V Burst Gate &Odd/Even Outputs

I OUT =40μA;Logic 1

V CC =5V V CC =12V

4.011.0 4.5V Composite Sync.Output I OUT =?1.6mA;Logic 0;Pin 10.20.8V Vertical Sync.Output I OUT =?1.6mA;Logic 0;Pin 30.20.8V Burst Gate Output I OUT =?1.6mA;Logic 0;Pin 50.20.8V Odd/Even Output I OUT =?1.6mA;Logic 0;Pin 7

0.2

0.8V Vertical Sync Width 190230300μs Burst Gate Width 2.7k ?from Pin 5to V CC 2.54 4.7μs Vertical Default Time

(Note 7)32

65

90μs

L M 1881,L M 1881-X

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Electrical Characteristics LM1881–X

V CC=5V;R SET=680k?;T A=–40?C to+85?C by correlation with100%electrical testing at T A=25?C Parameter Conditions Min Typ Max Units

Supply Current Outputs at

Logic1V CC=5V

V CC=12V

5.2

5.5

10

12

mA

DC Input Voltage Pin2 1.3 1.5 1.8V Input Threshold Voltage557085mV Input Discharge Current Pin2;V IN=2V61116μA Input Clamp Charge Current Pin2;V IN=1V0.20.8mA R SET Pin Reference Voltage Pin6; 1.10 1.22 1.35V

Composite Sync.&Vertical Outputs I OUT=40μA;

Logic1

V CC=5V

V CC=12V

4.0

11.0

4.5

V I OUT=1.6mA

Logic1

V CC=5V

V CC=12V

2.4

10.0

3.6

V

Burst Gate&Odd/Even Outputs I OUT=40μA;

Logic1

V CC=5V

V CC=12V

4.0

11.0

4.5

V

Composite Sync.Output I OUT=?1.6mA;Logic0;Pin10.20.8V Vertical Sync.Output I OUT=?1.6mA;Logic0;Pin30.20.8V Burst Gate Output I OUT=?1.6mA;Logic0;Pin50.20.8V Odd/Even Output I OUT=?1.6mA;Logic0;Pin70.20.8V Vertical Sync Width140230588μs Burst Gate Width 2.7k?from Pin5to V CC 2.24 4.7μs Vertical Default Time326590μs

Note1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.

Note2:For operation in ambient temperatures above25?C,the device must be derated based on a150?C maximum junction temperature and a package thermal resistance of110?C/W,junction to ambient.

Note3:ESD susceptibility test uses the“human body model,100pF discharged through a1.5k?resistor”.

Note4:Typicals are at T J=25?C and represent the most likely parametric norm.

Note5:Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.

Note6:Careful attention should be made to prevent parasitic capacitance coupling from any output pin(Pins1,3,5and7)to the R SET pin(Pin6).

Note7:Delay time between the start of vertical sync(at input)and the vertical output pulse.

Typical Performance Characteristics

R SET Value Selection vs Vertical Serration Pulse Separation

Vertical Default

Sync Delay Time

vs R SET

0091500700915008

LM1881,

LM1881-X

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Typical Performance Characteristics

(Continued)

Burst/Black Level Gate Time vs R SET

Vertical Pulse Width vs R SET

00915009

00915010

Vertical Pulse Width vs Temperature Supply Current vs Supply Voltage

00915011

00915002

Application Notes

The LM1881is designed to strip the synchronization signals from composite video sources that are in,or similar to,the N.T.S.C.format.Input signals with positive polarity video (increasing signal voltage signifies increasing scene bright-ness)from 0.5V (p-p)to 2V (p-p)can be accommodated.The LM1881operates from a single supply voltage between 5V DC and 12V DC.The only required external components besides a power supply decoupling capacitor at pin 8and a set current decoupling capacitor at pin 6,are the composite input coupling capacitor at pin 2and one resistor at pin 6that sets internal current levels.The resistor on pin 6(i.e.R set )allows the LM1881to be adjusted for source signals with line scan frequencies differing from 15.734kHz.Four major sync signals are available from the I/C;composite sync including both horizontal and vertical scan timing information;a verti-cal sync pulse;a burst gate or back porch clamp pulse;and an odd/even output.The odd/even output level identifies which video field of an interlaced video source is present at the input.The outputs from the LM1881can be used to gen-lock video camera/VTR signals with graphics sources,provide identification of video fields for memory storage,recover suppressed or contaminated sync signals,and pro-vide timing references for the extraction of coded or uncoded data on specific video scan lines.

To better understand the LM1881timing information and the type of signals that are used,refer to Figure 1(a-e)which shows a portion of the composite video signal from the end of one field through the beginning of the next field.

L M 1881,L M 1881-X

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Application Notes(Continued)

COMPOSITE SYNC OUTPUT

The composite sync output,Figure1(b),is simply a repro-duction of the signal waveform below the composite video black level,with the video completely removed.This is ob-tained by clamping the video signal sync tips to1.5V DC at Pin2and using a comparator threshold set just above this voltage to strip the sync signal,which is then buffered out to Pin1.The threshold separation from the clamped sync tip is nominally70mV which means that for the minimum input level of0.5V(p-p),the clipping level is close to the halfway point on the sync pulse amplitude(shown by the dashed line on Figure1(a).This threshold separation is independent of the signal amplitude,therefore,for a2V(p-p)input the clipping level occurs at11%of the sync pulse amplitude.The charging current for the input coupling capacitor is0.8mA, Normally the signal source for the LM1881is assumed to be clean and relatively noise-free,but some sources may have excessive video peaking,causing high frequency video and chroma components to extend below the black level refer-ence.Some video discs keep the chroma burst pulse present throughout the vertical blanking period so that the burst actually appears on the sync tips for three line periods instead of at black level.A clean composite sync signal can be generated from these sources by filtering the input signal. When the source impedance is low,typically75?,a620?resistor in series with the source and a510pF capacitor to ground will form a low pass filter with a corner frequency of 500kHz.This bandwidth is more than sufficient to pass the sync pulse portion of the waveform;however,any subcarrier content in the signal will be attenuated by almost18dB, effectively taking it below the comparator threshold.Filtering will also help if the source is contaminated with thermal noise.The output waveforms will become delayed from be-tween40ns to as much as200ns due to this filter.This much delay will not usually be significant but it does contrib-ute to the sync delay produced by any additional signal processing.Since the original video may also undergo pro-cessing,the need for time delay correction will depend on the total system,not just the sync stripper.

VERTICAL SYNC OUTPUT

A vertical sync output is derived by internally integrating the composite sync waveform(Figure2).To understand the generation of the vertical sync pulse,refer to the lower left hand section Figure2.Note that there are two comparators in the section.One comparator has an internally generated voltage reference called V1going to one of its inputs.The other comparator has an internally generated voltage refer-ence called V2going to one of its inputs.Both comparators have a common input at their noninverting input coming from the internal integrator.The internal integrator is used for integrating the composite sync signal.This signal comes from the input side of the composite sync buffer and are positive going sync pulses.The capacitor to the integrator is internal to the LM1881.The capacitor charge current is set by the value of the external resistor R SET.The output of the integrator is going to be at a low voltage during the normal horizontal lines because the integrator has a very short time to charge the capacitor,which is during the horizontal sync period.The equalization pulses will keep the output voltage of the integrator at about the same level,below the V1. During the vertical sync period the narrow going positive pulses shown in Figure1is called the serration pulse.The wide negative portion of the vertical sync period is called the vertical sync pulse.At the start of the vertical sync period,

before the first Serration pulse occurs,the integrator now

charges the capacitor to a much higher voltage.At the first

serration pulse the integrator output should be between V1

and V2.This would give a high level at the output of the

comparator with V1as one of its inputs.This high is clocked

into the“D”flip-flop by the falling edge of the serration pulse

(remember the sync signal is inverted in this section of the

LM1881).The“Q”output of the“D”flip-flop goes through the

OR gate,and sets the R/S flip-flop.The output of the R/S

flip-flop enables the internal oscillator and also clocks the

ODD/EVEN“D”flip-flop.The ODD/EVEN field pulse opera-

tion is covered in the next section.The output of the oscilla-

tor goes to a divide by8circuit,thus resetting the R/S

flip-flop after8cycles of the oscillator.The frequency of the

oscillator is established by the internal capacitor going to the

oscillator and the external R SET.The“Q”output of the R/S

flip-flop goes to pin3and is the actual vertical sync output of

the LM1881.By clocking the“D”flip-flop at the start of the

first serration pulse means that the vertical sync output pulse

starts at this point in time and lasts for eight cycles of the

internal oscillator as shown in Figure1.

How R SET affects the integrator and the internal oscillator is

shown under the Typical Performance Characteristics.The

first graph is“R SET Value Selection vs Vertical Serration

Pulse Separation”.For this graph to be valid,the vertical

sync pulse should last for at least85%of the horizontal half

line(47%of a full horizontal line).A vertical sync pulse from

any standard should meet this requirement;both NTSC and

PAL do meet this requirement(the serration pulse is the

remainder of the period,10%to15%of the horizontal half

line).Remember this pulse is a positive pulse at the integra-

tor but negative in Figure1.This graph shows how long it

takes the integrator to charge its internal capacitor above V1.

With R SET too large the charging current of the integrator will

be too small to charge the capacitor above V1,thus there will

be no vertical synch output pulse.As mentioned above,R SET

also sets the frequency of the internal oscillator.If the oscil-

lator runs too fast its eight cycles will be shorter than the

vertical sync portion of the composite sync.Under this con-

dition another vertical sync pulse can be generated on one of

the later serration pulse after the divide by8circuit resets the

R/S flip-flop.The first graph also shows the minimum R SET

necessary to prevent a double vertical pulse,assuming that

the serration pulses last for only three full horizontal line

periods(six serration pulses for NTSC).The actual pulse

width of the vertical sync pulse is shown in the“Vertical

Pulse Width vs R SET”https://www.wendangku.net/doc/eb10358966.html,ing NTSC as an example,

lets see how these two graphs relate to each other.The

Horizontal line is64μs long,or32μs for a horizontal half

line.Now round this off to30μs.In the“R SET Value Selection

vs Vertical Serration Pulse Separation”graph the minimum

resistor value for30μs serration pulse separation is about

550k?.Going to the“Vertical Pulse Width vs R SET”graph

one can see that550k?gives a vertical pulse width of about

180μs,the total time for the vertical sync period of NTSC(3

horizontal lines).A550k?will set the internal oscillator to a

frequency such that eight cycles gives a time of180μs,just

long enough to prevent a double vertical sync pulse at the

vertical sync output of the LM1881.

The LM1881also generates a default vertical sync pulse

when the vertical sync period is unusually long and has no

serration pulses.With a very long vertical sync time the

integrator has time to charge its internal capacitor above the

voltage level V2.Since there is no falling edge at the end of

a serration pulse to clock the“D”flip-flop,the only high signal

going to the OR gate is from the default comparator when

output of the integrator reaches V2.At this time the R/S

LM1881,

LM1881-X

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Application Notes

(Continued)

flip-flop is toggled by the default comparator,starting the vertical sync pulse at pin 3of the LM1881.If the default vertical sync period ends before the end of the input vertical sync period,then the falling edge of the vertical sync (posi-tive pulse at the “D”flip-flop)will clock the high output from the comparator with V 1as a reference input.This will retrig-ger the oscillator,generating a second vertical sync output pulse.The “Vertical Default Sync Delay Time vs R SET ”graph shows the relationship between the R SET value and the delay time from the start of the vertical sync period before the default vertical sync pulse is https://www.wendangku.net/doc/eb10358966.html,ing the NTSC example again the smallest resistor for R SET is 500k ?.The vertical default time delay is about 50μs,much longer than the 30μs serration pulse spacing.

A common question is how can one calculate the required R SET with a video timing standard that has no serration pulses during the vertical blanking.If the default vertical sync is to be used this is a very easy https://www.wendangku.net/doc/eb10358966.html,e the “Vertical Default Sync Delay Time vs R SET ”graph to select the nec-essary R SET to give the desired delay time for the vertical sync output signal.If a second pulse is undesirable,then check the “Vertical Pulse Width vs R SET ”graph to make sure

the vertical output pulse will extend beyond the end of the input vertical sync period.In most systems the end of the vertical sync period may be very accurate.In this case the preferred design may be to start the vertical sync pulse at the end of the vertical sync period,similar to starting the vertical sync pulse after the first serration pulse.A VGA standard is to be used as an example to show how this is done.In this standard a horizontal line is 32μs long.The vertical sync period is two horizontal lines long,or 64μs.The vertical default sync delay time must be longer than the vertical sync period of 64μs.In this case R SET must be larger than 680k ?.R SET must still be small enough for the output of the integrator to reach V 1before the end of the vertical period of the input pulse.The first graph can be used to confirm that R SET is small enough for the integrator.Instead of using the vertical serration pulse separation,use the actual pulse width of the vertical sync period,or 64μs in this example.This graph is linear,meaning that a value as large as 2.7M ?can be used for R SET (twice the value as the maximum at 30μs).Due to leakage currents it is advisable to keep the value of R SET under 2.0M ?.In this example a value of 1.0M ?is selected,well above the minimum of 680k ?.With this value for R SET the pulse width of the vertical sync output pulse of the LM1881is about 340μs.

00915003

FIGURE 1.(a)Composite Video;(b)Composite Sync;(c)Vertical Output Pulse;

(d)Odd/Even Field Index;(e)Burst Gate/Back Porch Clamp

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Application Notes(Continued)

ODD/EVEN FIELD PULSE

An unusual feature of LM1881is an output level from Pin7 that identifies the video field present at the input to the LM1881.This can be useful in frame memory storage appli-cations or in extracting test signals that occur in alternate fields.For a composite video signal that is interlaced,one of the two fields that make up each video frame or picture must have a half horizontal scan line period at the end of the vertical scan—i.e.,at the bottom of the picture.This is called the“odd field”or“even field”.The“even field”or“field2”has a complete horizontal scan line at the end of the field.An odd field starts on the leading edge of the first equalizing pulse, whereas the even field starts on the leading edge of the second equalizing pulse of the vertical retrace interval.Fig-ure1(a)shows the end of the even field and the start of the odd field.

To detect the odd/even fields the LM1881again integrates the composite sync waveform(Figure2).A capacitor is charged during the period between sync pulses and dis-charged when the sync pulse is present.The period between normal horizontal sync pulses is enough to allow the capaci-tor voltage to reach a threshold level of a comparator that clears a flip-flop which is also being clocked by the sync waveform.When the vertical interval is reached,the shorter integration time between equalizing pulses prevents this threshold from being reached and the Q output of the flip-flop is toggled with each equalizing pulse.Since the half line period at the end of the odd field will have the same effect as an equalizing pulse period,the Q output will have a different polarity on successive fields.Thus by comparing the Q polarity with the vertical output pulse,an odd/even field index is generated.Pin7remains low during the even field and high during the odd field.

BURST/BACKPORCH OUTPUT PULSE

In a composite video signal,the chroma burst is located on the backporch of the horizontal blanking period.This period, approximately4.8μs long,is also the black level reference for the subsequent video scan line.The LM1881generates a pulse at Pin5that can be used either to retrieve the chroma burst from the composite video signal(thus providing a subcarrier synchronizing signal)or as a clamp for the DC restoration of the video waveform.This output is obtained simply by charging an internal capacitor starting on the trailing edge of the horizontal sync pulses.Simultaneously the output of Pin5is pulled low and held until the capacitor charge circuit times out—4μs later.A shorter output burst gate pulse can be derived by differentiating the burst output

00915004

*Components Optional,See Text

FIGURE2.

LM1881,

LM1881-X https://www.wendangku.net/doc/eb10358966.html,

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Application Notes

(Continued)

using a series C-R network.This may be necessary in applications which require high horizontal scan rates in com-bination with normal (60Hz–120Hz)vertical scan rates.APPLICATIONS

Apart from extracting a composite sync signal free of video information,the LM1881outputs allow a number of interest-ing applications to be developed.As mentioned above,the burst gate/backporch clamp pulse allows DC restoration of the original video waveform for display or remodulation on an R.F.carrier,and retrieval of the color burst for color synchronization and decoding into https://www.wendangku.net/doc/eb10358966.html,ponents.For frame memory storage applications,the odd/even field lever allows identification of the appropriate field ensuring the correct read or write sequence.The vertical pulse output is particularly useful since it begins at a precise time —the rising edge of the first vertical serration in the sync wave-form.This means that individual lines within the vertical blanking period (or anywhere in the active scan line period)can easily be extracted by counting the required number of transitions in the composite sync waveform following the start of the vertical output pulse.

The vertical blanking interval is proving popular as a means to transmit data which will not appear on a normal T.V.receiver screen.Data can be inserted beginning with line 10(the first horizontal scan line on which the color burst ap-pears)through to line https://www.wendangku.net/doc/eb10358966.html,ually lines 10through 13are not used which leaves lines 14through 21for inserting signals,which may be different from field to field.In the U.S.,line 19is normally reserved for a vertical interval reference signal (VIRS)and line 21is reserved for closed caption data for the hearing impaired.The remaining lines are used in a number of ways.Lines 17and 18are frequently used during studio processing to add and delete vertical interval test signals (VITS)while lines 14through 18and line 20can be used for Videotex/Teletext data.Several institutions are proposing to transmit financial data on line 17and cable systems use the available lines in the vertical interval to send decoding data for descrambler terminals.

Since the vertical output pulse from the LM1881coincides with the leading edge of the first vertical serration,sixteen

positive or negative transitions later will be the start of line 14in either field.At this point simple counters can be used to select the desired line(s)for insertion or deletion of data.VIDEO LINE SELECTOR

The circuit in Figure 3puts out a singe video line according to the binary coded information applied to line select bits b0–b7.A line is selected by adding two to the desired line number,converting to a binary equivalent and applying the result to the line select inputs.The falling edge of the LM1881’s vertical pulse is used to load the appropriate number into the counters (MM74C193N)and to set a start count latch using two NAND https://www.wendangku.net/doc/eb10358966.html,posite sync transi-tions are counted using the borrow out of the desired number of counters.The final borrow out pulse is used to turn on the analog switch (CD4066BC)during the desired line.The fall-ing edge of this signal also resets the start count latch,thereby terminating the counting.

The circuit,as shown,will provide a single line output for each field in an interlaced video system (television)or a single line output in each frame for a non-interlaced video system (computer monitor).When a particular line in only one field of an interlaced video signal is desired,the odd/even field index output must be used instead of the vertical output pulse (invert the field index output to select the odd field).A single counter is needed for selecting lines 3to 14;two counters are needed for selecting lines 15to 253;and three counters will work for up to 2046lines.An output buffer is required to drive low impedance loads.

MULTIPLE CONTIGUOUS VIDEO LINE

SELECTOR WITH BLACK LEVEL RESTORATION The circuit in Figure 4will select a number of adjoining lines starting with the line selected as in the previous example.Additional counters can be added as described previously for either higher starting line numbers or an increased num-ber of contiguous output lines.The back porch pulse output of the LM1881is used to gate the video input’s black level through a low pass filter (10k ?,10μF)providing black level restoration at the video output when the output selected line(s)is not being gated through.

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Typical Applications

00915005

FIGURE3.Video Line Selector LM1881, LM1881-X

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Typical Applications

(Continued)

00915006

FIGURE 4.Multiple Contiguous Video Line Selector with Black Level Restoration

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Physical Dimensions

inches (millimeters)unless otherwise noted

Molded Small Outline Package (M)Order Number LM1881M (0?C to +70?C)Order Number LM1881M-X (-40?C to +85?C)

NS Package Number M08A

Molded Dual-In-Line Package (N)Order Number LM1881N (0?C to +70?C),Order Number LM1881N-X (-40?C to +85?C)

NS Package Number N08E

LM1881,LM1881-X

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