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ISL59119IBZ中文资料

FN6319.1

ISL59119

Triple Channel Video Driver with LPF

The ISL59119 is a triple channel reconstruction filter with a -3dB roll-off frequency of 8MHz. Operating from single supplies ranging from +3.0V to +5.5V and sinking an

ultra-low 8mA quiescent current, the ISL59119 is ideally suited for low power, battery-operated applications.

The ISL59119 is designed to meet the needs for micropower and bandwidth required in battery-operated communication, instrumentation and modern industrial applications such as video on demand, cable set-top boxes, and MP3 players.

The ISL59119 is available in an 8 Ld SO package and is specified for operation over the full -40°C to +85°C temperature range.

Pinout

ISL59119

(8 LD SO)

TOP VIEW Features

?5th Order 8MHz Reconstruction Filter ?Low Supply Current (8mA typ)?Supplies from +3.0V to +5.5V

?Rail-to-Rail Output

?Pb-free (RoHS compliant) Applications

?Video Amplifiers

?Portable and Handheld Products ?Communications Devices

?Video on Demand

?Cable Set-top Boxes

?Satellite Set-top Boxes

?MP3 Players

?Personal Video Recorder

Block Diagram

Ordering Information PART

NUMBER (Note)

PART

MARKING

TEMP.

RANGE

(°C)

PACKAGE(

Pb-Free)

PKG.

DWG. #

ISL59119IBZ*59119 IBZ-40 to +85°C8 Ld SOIC MDP0027 *Add “-T13” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE:These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Y IN

C IN CVBS IN

V DD

Y OUT

C OUT

CVBS OUT

GND

Y IN Y OUT

CVBS IN CVBS OUT

C IN C OUT

8MHz

1μA

500mV

75mV

Data Sheet January 28, 2008

元器件交易网https://www.wendangku.net/doc/ed16483310.html,

IMPORTANT NOTE:All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A

Absolute Maximum Ratings (T A = +25°C)

Thermal Information

Supply Voltage from V DD to GND . . . . . . . . . . . . . . . . . . . . . . . 6.0V Input Voltage . . . . . . . . . . . . . . . . . . . . . . .V DD +0.3V to GND -0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below https://www.wendangku.net/doc/ed16483310.html,/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

Electrical Specifications

V DD = 3.3V, T A = +25°C, R L = 150Ω to GND, unless otherwise specified.

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CHARACTERISTICS V DD Supply Voltage Range 3.0

5.5V I DD

Quiescent Supply Current

V DD = 3.3V, V IN = 500mV, no load 8.411.5mA V DD = 5.5V, V IN = 500mV, no load

9.5

12.5mA V Y_CLAMP Y Input Clamp Voltage I Y = -100μA -400+40mV I Y_DOWN Y Input Pull-down Current V Y = 0.5V 0.5

12μA I Y_CLAMP Y Input Clamp Pull-up Current V Y = -0.2V -2.6-1.5

mA R Y

Y Input Resistance 0.5V < V Y < 1V 10

M Ω

V CVBS_CLAMP CVBS Input Clamp Voltage I CVBS = -100μA -40040mV I CVBS_DOWN CVBS Input Pull-down Current V CVBS = 0.5V 0.5

12μA I CVBS_CLAMP CVBS Input Clamp Pull-up Current V CVBS = -0.2V -2.6-1.5

mA R CVBS CVBS Input Resistance 0.5V < V CVBS < 1V 10

M Ω

V C_CLAMP C Input Clamp Voltage

V Y < 0.08V, I C = 0A 420550650mV I C_DOWN C Input Clamp Pull-down Current V C = 1V, V Y < 0.08V -60-40-25μA I C_UP C Input Clamp Pull-up Current V C = 0V, V Y < 0.08V

254060μA R C C Input Resistance V Y < 0.08V, 0.25V < V C < 0.75V 5710k ΩI C C Input Bias Current V Y > 0.2V

-1500+150nA V Y_SYNC Y Input Sync Detect Voltage 80

145200mV A V

Voltage Gain

R L = 150Ω

1.95

2.0

2.04V/V ΔA V

C-Y-CVBS Channel Mismatch -2

%PSRR

DC Power Supply Rejection

V DD = 3.3V 3544dB V DD = 5.0V

4548dB

V OS Output Level Shift Voltage V IN = 0V, no load

60150240mV V OH Output Voltage High Swing V IN = 2V, R L = 75Ω to GND (dual load) 2.6 3.1V I SC

Output Short-Circuit Current

V IN = 2V, to GND through 10Ω, sourcing 65mA V IN = 100mV, out short to V DD through 10Ω

AC PERFORMANCE PB Passband Flatness f = 4.2MHz relative to 1.1MHz, R L = 150Ω, C L = 5pF

-1

0+1

dB BW

-3dB Bandwidth

R L = 150Ω, C L = 5pF

MHz

Connection Diagram

SB Normalized Stopband Gain f = 27MHz relative to 1.1MHz -60

-50-40

dB dG Differential Gain NTSC and PAL 0.2%dP Differential Phase NTSC and PAL 0.5°D/DT Group Delay Variation f = 100kHz, 5MHz

5.4ns XTALK Crosstalk f = 1MHz, between any two channels -70dB R OUT_AC Output Impedance f = 4.2MHz

1.5Ω+SR Positive Slew Rate 10% to 90%, V IN = 1V step 152545V/μs -SR

Negative Slew Rate

90% to 10%, V IN = 1V step

1520

45V/μs

Electrical Specifications

V DD = 3.3V, T A = +25°C, R L = 150Ω to GND, unless otherwise specified. (Continued)

PARAMETER DESCRIPTION

CONDITIONS

MIN TYP MAX UNIT 75

CVBS OUT

Y IN Y OUT

CVBS IN

CVBS OUT

C IN C OUT

+- 8MHz

8MHz

1μA

+-1μA

500mV

-75mV

Y (LUMINANCE)

C (CHROMINANCE)

CVBS (COMPOSITE)

3.3V

V DD

0.1μF

75Y OUT

C OUT S-VIDEO CABLE

Pin Descriptions

PIN NUMBER

PIN NAME

DESCRIPTION

1Y IN Luminance Input 2C IN Chrominance input 3CVBS IN Composite Video input 4V DD Positive power supply 5GND Ground

6CVBS OUT Composite Video output 7C OUT Chrominance output 8

Y OUT

Luminance output

Typical Performance Curves

FIGURE 1.SMALL SIGNAL GAIN vs FREQUENCY -0.1dB FIGURE https://www.wendangku.net/doc/ed16483310.html,RGE SIGNAL GAIN vs FREQUENCY -0.1dB

FIGURE 3.GAIN vs FREQUENCY -3dB POINT

FIGURE 4.GAIN vs FREQUENCY FOR VARIOUS C LOAD

FIGURE 5.GROUP DELAY vs FREQUENCY FIGURE 6.PSRR vs FREQUENCY

-5

-4

-3-2-1010.1M

1M 10M FREQUENCY (Hz)N O R M A L I Z E D G A I N (d B )

V IN = 100mV P-P

V DD = 5V

V DD = 3.3V

100M

-5

-4

-3-2-101

N O R M A L I Z E D G A I N (d B )

0.1M

1M 10M 100M

V IN = 700mV P-P

V DD = 5V

V DD = 3.3V

FREQUENCY (Hz)

-60-50-40-30-20-10010N O R M A L I Z E D G A I N (d B )

0.1M

10M

FREQUENCY (Hz)

100M

V IN = 100mV P-P OR 700mV P-P

-1-0.8-0.6-0.4-0.200.2G A I N (d B )

0.1M

1M 10M

FREQUENCY (Hz)

100M

V IN = 100mV P-P

C L = 39pF

C L = 220pF

204060801001201400.1M

10M

100M

FREQUENCY (Hz)

D E L A Y (n s )

V DD = 5V

V DD = 3.3V

10k

100k

10Mk

FREQUENCY (Hz)

-70

-60-50-40-30-20-100R E J E C T I O N (d B )

V DD = 5V

V DD = 3.3V

V AC = 100mV P-P

FIGURE 7.OUTPUT IMPEDANCE vs FREQUENCY FIGURE 8.CROSSTALK vs FREQUENCY

FIGURE 9.MAXIMUM OUTPUT MAGNITUDE vs INPUT

MAGNITUDE

FIGURE 10.SUPPLY CURRENT vs SUPPLY VOLTAGE

FIGURE https://www.wendangku.net/doc/ed16483310.html,RGE SIGNAL STEP RESPONSE

FIGURE 12.SMALL SIGNAL PULSE RESPONSE

10203040506070800.01M

0.1M

10M

100M

FREQUENCY (Hz)

I M P E D A N C E (Z )

V DD = 5V

V DD = 3.3V

-90

-80-70-60-50-40-30-20-1000.1M

10M

100M

FREQUENCY (Hz)

C R O S S T A L K (d B )

CHROMA TO LUMA

CV TO CHROMA

Y TO CHROMA

CHROMA TO CV Y TO CV

CV TO Y

00.51.01.52.02.53.03.54.04.55.00

0.5

1.0 1.5

2.0 2.5

3.0

INPUT MAGNITUDE (V P-P )

O U T P U T M A G N I T U D E (V P -P )

f = 500kHz

8.0

8.28.48.68.89.09.29.43.0

3.2

3.4

3.6

3.8

4.0

4.2

4.4

4.6

4.8

5.0

VOLTAGE (V)

C U R R E N T (m A )

INPUTS FLOATING NO LOAD

f IN = 500kHz

TIMEBASE = 200ns/DIV

VERTICAL SCALE: 500mV/DIV

f IN = 500kHz

TIMEBASE = 200ns/DIV

VERTICAL SCALE: 100mV/DIV

OUTPUT

FIGURE 13.2T RESPONSE FIGURE 14.12.5T RESPONSE

FIGURE 15.NTSC COLOR BAR FIGURE 16.S-VIDEO OUTPUT

FIGURE 17.DIFFERENTIAL GAIN FIGURE 18.DIFFERENTIAL PHASE

TIMEBASE = 100ns/DIV INPUT: 200mV/DIV OUTPUT: 500mV/DIV

INPUT

OUTPUT

TIMEBASE = 500ns/DIV INPUT: 200mV/DIV OUTPUT: 500mV/DIV

OUTPUT

INPUT

TIMEBASE = 10μs/DIV INPUT: 500mV/DIV OUTPUT: 1V/DIV

OUTPUT

INPUT

Y OUT

SYNC TIP: +130mV

C OUT

AVERAGE LEVEL: +1.26V

TIMEBASE = 10μs/DIV Y OUT : 500mV/DIV C OUT : 500mV/DIV

-0.15

-0.10-0.0500.050.100.150.20

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

INPUT DC VOLTAGE (V)

D I F F

E R E N T I A L G A I N (%)

VAC = 40mV P-P f = 3.58MHz

-0.6

-0.5-0.4-0.3-0.2-0.100.10.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

INPUT DC LEVEL (V)

D I F F

E R E N T I A L P H A S E (%)

VAC = 40mV P-P f = 3.58MHz

FIGURE 19.HARMONIC DISTORTION vs FREQUENCY FIGURE 20.HARMONIC DISTORTION vs OUTPUT VOLTAGE

FIGURE 21.OUTPUT VOLTAGE NOISE vs FREQUNCY FIGURE 22.-3dB BANDWIDTH vs INPUT RESISTANCE

FIGURE 23.RESPONSE TO +500mV DC STEP ON INPUT (SEE

FIGURE 27)FIGURE 24.RESPONSE TO -500mV DC STEP ON INPUT (SEE

FIGURE 27)

-100

-90-80-70-60-50-40-30-20-1000.5M

1.0M

1.5M

2.0M 2.5M

3.0M 3.5M

4.0M

4.5M

5.0M

FREQUENCY (Hz)

H A R M O N I C D I S T O R T I O N (d B c )

3RD HD

2ND HD

V DD = 3.3V

V OUT = 1.5V P-P , SINEWAVE R L = 150Ω

THD

-80-70-60-50-40-30-20-1000.5

0.9

1.3 1.7

2.1

2.5

OUTPUT VOLTAGE (V P-P )

T H D (d B c )

V DD = 3.3V R L = 150Ω

f IN = 5MHz

f IN = 500kHz

20406080100120140160

1802001k

10k

100k

10M

FREQUENCY (Hz)

V O L T A G E N O I S E (n V /√H z )8.08.18.28.38.48.58.68.70

100

200300400

500

INPUT RESISTANCE (Ω)

-3d B P O I N T (M H z )

INPUT = NTSC VIDEO + 2Hz SQUARE WAVE (BEFORE COUPLING CAPACITOR)

TIMEBASE = 10ms/DIV INPUT: 500mV/DIV OUTPUT: 1V/DIV

OUTPUT

INPUT = NTSC VIDEO + 2Hz SQUARE WAVE (BEFORE COUPLING CAPACITOR)

TIMEBASE = 500μs/DIV

INPUT: 500mV/DIV OUTPUT: 1V/DIV

OUTPUT

Application Information

The ISL59119 is a single-supply rail-to-rail triple (one

S-video channel and one composite channel) video amplifier with internal sync tip clamps, a typical -3dB bandwidth of 8MHz and slew rate of about 25V/μs. This part is ideally suited for applications requiring high composite and S-video performance with very low power consumption. As the performance characteristics and features illustrate, the ISL59119 is optimized for portable video applications.

Internal Sync Clamp

Embedded video DACs typically use ground as their most negative supply. This places the sync tip voltage at a

minimum of 0V. Presenting a 0V input to most single supply amplifiers will saturate the output stage of the amplifier resulting in a clipped sync tip and degraded video image. The ISL59119 features an internal sync clamp and offset function that level shifts the entire video signal to the

optimum level before it reaches the amplifiers’ input stage. These features also help avoid saturation of the output stage of the amplifier by setting the signal closer to the best voltage range.

The simplified block diagram on page 1 shows the basic operation of the ISL59119’s sync clamp. The Y and CVBS inputs’ AC-coupled video sync signal is pulled negative by a current source at the input. When the sync tip goes below the comparator threshold, the comparator output goes high, pulling up on the input through the diode, forcing current into the coupling capacitor until the voltage at the input is again 0V, and the comparator turns off. This forces the sync tip clamp to always be 0V, setting the offset for the entire video signal. The C-Channel is slaved to the Y-Channel and clamped to a 500mV level at the input.

Figure 27 shows the setup for testing the clamp’s response to a large step response at the input.

Once the signals are clamped at the input they are level shifted by +65mV before being amplified by a gain of x2.

The Sallen Key Low Pass Filter

The Sallen Key is a classic low pass configuration. This provides a very stable low pass function, and in the case of the ISL59119, a three-pole roll-off at 8MHz. The three-pole function is accomplished with an RC low pass network placed in series with and before the Sallen Key. The first pole is

formed by an RC network, with poles two and three generated with a Sallen Key, creating a nice three-pole roll-off at 8MHz.

Output Coupling

The ISL59119 can be AC or DC coupled to its output. When AC coupling, a 220μF coupling capacitor is recommended to ensure that low frequencies are passed, preventing video “tilt” or “droop” across a line.

The ISL59119’s internal sync clamp makes it possible to DC couple the output to a video load, eliminating the need for any AC coupling capacitors, saving board space, cost, and eliminating any “tilt” or offset shift in the output signal. The

FIGURE 25.PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE FIGURE 26.PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0

P O W E R D I S S I P A T I O N (W )

0.4

1.00.8

0.2

0.6

010*******

AMBIENT TEMPERATURE (°C)50257585435mW 909mW

θJ

A =

+230°C /W

S O

T 23-6θJ

= +110°C /W S O 8JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD

0P O W E R D I S S I P A T I O N (W )

0.20.70.60.10.4

0.50.30

100

125

150

AMBIENT TEMPERATURE (°C)

7585391mW 625mW θJ

60°C /W S O 8θJ A =

56°C /W

S O

T 23-675Ω

75Ω

500Ω

0.1μF

NTSC VIDEO

1Hz SQUARE WAVE

150Ω

OUTPUT ISL59119

CH1

CH2

FIGURE 27.DC STEP RESPONSE CIRCUIT

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at https://www.wendangku.net/doc/ed16483310.html,/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see https://www.wendangku.net/doc/ed16483310.html,

trade-off is larger supply current draw, since the DC component of the signal is now dissipated in the load

resistor. Typical load current for AC coupled signals is 5mA compared to 10mA for DC coupling.

Output Drive Capability

The ISL59119 does not have internal short circuit protection circuitry. If the output is shorted indefinitely, the power

dissipation could easily overheat the die or the current could eventually compromise metal integrity. Maximum reliability is maintained if the output current never exceeds ±40mA. This limit is set by the design of the internal metal interconnect. Note that for transient short circuits, the part is robust.Short circuit protection can be provided externally with a back match resistor in series with the output placed close as possible to the output pin. In video applications this would be a 75Ω resistor and will provide adequate short circuit protection to the device. Care should still be taken not to stress the device with a short at the output.

Power Dissipation

With the high output drive capability of the ISL59119, it is possible to exceed the +125°C absolute maximum junction temperature under certain load current conditions.

Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area.

The maximum power dissipation allowed in a package is determined according to Equation 1:

Where:

T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature ΘJA = Thermal resistance of the package

The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or:for sourcing use Equation 2:

for sinking use Equation 3:

Where:

V S = Supply voltage

I SMAX = Maximum quiescent supply current V OUT = Maximum output voltage of the application R LOAD = Load resistance tied to ground I LOAD = Load current

Power Supply Bypassing Printed Circuit Board Layout

As with any modern operational amplifier, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, a single 4.7μF tantalum capacitor in parallel with a 0.1μF ceramic capacitor from V S + to GND will suffice.

Printed Circuit Board Layout

For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance.

PD MAX T JMAX T AMAX

–ΘJA

--------------------------------------------=(EQ. 1)

PD MAX V S I SMAX V S V OUT –()+×V OUT

---------------×=(EQ. 2)

PD MAX V S I SMAX V OUT V S –()+×I LOAD

×=(EQ. 3)

Small Outline Package Family (SO)

GAUGE PLANE

DETAIL X

SEATING PLANE

0.010B

M C A 0.004C

0.010B

M C A B

(N/2)

(N/2)+1

PIN #1I.D. MARK

h X 45°

SEE DETAIL “X”

0.010

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL

INCHES

TOLERANCE

NOTES

SO-8SO-14SO16 (0.150”)SO16 (0.300”) (SOL-16)

SO20 (SOL-20)SO24 (SOL-24)SO28 (SOL-28)A 0.0680.0680.0680.1040.1040.1040.104MAX -A10.0060.0060.0060.0070.0070.0070.007±0.003-A20.0570.0570.0570.0920.0920.0920.092±0.002-b 0.0170.0170.0170.0170.0170.0170.017±0.003-c 0.0090.0090.0090.0110.0110.0110.011±0.001-D 0.1930.3410.3900.4060.5040.6060.704±0.0041, 3E 0.2360.2360.2360.4060.4060.4060.406±0.008-E10.1540.1540.1540.2950.2950.2950.295±0.0042, 3e 0.0500.0500.0500.0500.0500.0500.050Basic -L 0.0250.0250.0250.0300.0300.0300.030±0.009-L10.0410.0410.0410.0560.0560.0560.056Basic -h 0.0130.0130.0130.0200.0200.0200.020Reference -N 8

Reference

-Rev. M 2/07

NOTES:

1.Plastic or metal protrusions of 0.006” maximum per side are not included.

2.Plastic interlead protrusions of 0.010” maximum per side are not included.

3.Dimensions “D” and “E1” are measured at Datum Plane “H”.

4.Dimensioning and tolerancing per ASME Y14.5M -1994