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HCF4067

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September 2002s

LOW ON RESISTANCE : 125? (Typ.) OVER 15V p-p SIGNAL INPUT RANGE FOR V DD - V SS = 15V

HIGH OFF RESISTANCE : CHANNEL LEAKAGE OF 10pA (Typ.) at V DD - V SS = 10V

MATCHED SWITCH CHARACTERISTICS : ?R ON = 5? (Typ.) FOR V DD - V SS =15V s

VERY LOW QUIESCENT POWER

DISSIPATION UNDER A DIGITAL CONTROL INPUT AND SUPPLY CONDITIONS : 0.2μW (Typ.) at V DD - V SS = 10V

s BINARY ADDRESS DECODING ON CHIP s

QUIESCENT CURRENT SPECIFIED UP TO 20V

STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS

s 5V, 10V AND 15V PARAMETRIC RATINGS s

INPUT LEAKAGE CURRENT

I I = 100nA (MAX) AT V DD = 18V T A = 25°C s 100% TESTED FOR QUIESCENT CURRENT s

MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"

DESCRIPTION

HCF4067B is monolithic integrated circuits fabricated in Metal Oxide Semiconductor technology available in SOP package. HCF4067B, analog multiplexer/demultiplexer CMOS, is a digitally controlled analog switches device having low ON impedance, low OFF leakage current and internal address decoding. In addition, the ON resistance is relatively constant over the full input-signal range.

HCF4067B ia a 16-channel multiplexer with four binary control inputs A, B, C, D, and an inhibit input, arranged so that any combination of the inputs selects one switch.

HCF4067B

ANALOG SINGLE 16 CHANNEL MULTIPLEXER/DEMULTIPLEXER

ORDER CODES

PACKAGE TUBE T & R SOP

HCF4067BM1

HCF4067M013TR

HCF4067B

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INPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

FUNCTIONAL DIAGRAM

TRUTH TABLE

PIN No SYMBOL NAME AND FUNCTION 10, 11, 14,

A, B, C, D

Binary Control Inputs

1COMMON

OUT/IN Common Out/In

INHIBIT Inhibit Input 9, 8, 7, 6, 5, 4, 3, 2, 23, 22, 21, 20, 19, 18, 17,

0 to 15

CHANNEL IN/OUT

16 channel In/Out 12V SS Negative Supply Voltage 24

V DD

Positive Supply Voltage

A B C D INH SELECTED CHANNEL

X X X X H NONE L L L L L 0H L L L L 1L H L L L 2H H L L L 3L L H L L 4H L H L L 5L H H L L 6H H H L L 7L L L H L 8H L L H L 9L H L H L 10H H L H L 11L L H H L 12H L H H L 13L H H H L 14H

HCF4067B LOGIC DIAGRAM

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HCF4067B

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ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

All voltage values are referred to V SS pin voltage.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter

Value Unit V DD Supply Voltage -0.5 to +22V V I DC Input Voltage -0.5 to V DD + 0.5

V I I DC Input Current

± 10mA P D Power Dissipation per Package

200mW Power Dissipation per Output Transistor 100mW T op Operating Temperature -55 to +125°C T stg

Storage Temperature

-65 to +150

°C

Symbol Parameter

Value Unit V DD Supply Voltage 3 to 20V V I Input Voltage

0 to V DD V T op

Operating Temperature

-55 to 125

°C

HCF4067B

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STATIC ELECTRICAL CHARACTERISTICS

(T amb = 25°C,Typical temperature coefficient for all V DD value is 0.3 %/°C)

The Noise Margin for both "1" and "0" level is: 1V min. with V DD =5V, 2V min. with V DD =10V, 2.5V min. with V DD =15V ? Determined by minimum feasible leakage measurement for automating testing

Symbol

Parameter

Test Condition

Value

Unit V IS (V)

V EE (V)

V SS (V)

V DD (V)T A = 25°C -40 to 85°C -55 to 125°C Min.

Typ.Max.Min.

Max.Min.

Max.I L

Quiescent Supply Current

50.045150150μA

100.0410300300150.042060060020

0.0810030003000SWITCH

R ON On Resistance

0 < V I

< V DD

5470105012001200?

1018040050052015125240

300

?ON

Resistance ?RON (between any 2 of 4 switches)

510?

1010155OFF (?) Channel Leakage

Current Any Channel Off

0018

±0.1

10010001000

μA

Channel Leakage Current All Channel Off

(Common Out/In)0018±0.110010001000

C Capacitance Input

-555

Output capacitance 55Feedthrough

0.2

CONTROL

V IL

Input Low Voltage = VDD

thru

1K ? V EE = V SS R L = 1K ? to

V SS

I IS < 2μA (on

all OFF channels)

5 1.5 1.5 1.5V

10333154

V IH

Input High Voltage

5 3.5 3.5 3.5V

107771511

I I

Input Leakage Current

V I = 0/18V 18

±10-3±0.1±1±1μA C I

Input Capacitance

Any Address or Inhibit

Input

7.5

HCF4067B

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DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, C L = 50pF, R L = 200K ?, t r = t f = 20 ns)

DD (**) : Both Ends of Channel

(?) : Peak to Peak voltage symmetrical about (V DD - V SS ) / 2

HCF4067B

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APPLICATION INFORMATION

In applications where separate power sources are used to drive V DD and the signal inputs, the V DD current capability should exceed V DD /R L (R L =effective external load). This provision avoids permanent current flow or clamp action on the V DD supply when power is applied or removed from the HCF4067B.

When switching from one address to another,some of the ON periods of the channels of the multiplexers will overlap momentarily, which may be objectionable in certain applications. Also,when a channel is turned ON or OFF by an address input, there is a momentary conductive path from the channel to V SS , which will dump some charge from any capacitor connected to the input or output of the channel. The inhibit input turning on a channel will similarly dump some charge to V SS .

The amount of charge dumped is mostly a function of the signal level above V SS . Typically, at V DD - V SS = 10V, a 100 pF capacitor connected to the input or output of the channel will lose 3-4% of its voltage at the moment the channel turns ON or OFF. This loss of voltage is essentially independent of the address or inhibit signal transition time, if the transition time is less than 1-2 ms. When the inhibit signal turns a channel off,there is no change dumping of V SS . Rather, there is a slight rise in the channel voltage level (65 mV typ.) due to the capacitance coupling from inhibit input to channel input or output. Address input also couple some voltage steps onto the channel signal levels.

In certain applications, the external load-resistor current may include both V DD and signal line components. To avoid drawing V DD current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.8V (calculated from R ON values shown in ELECTRICAL CHARACTERISTICS CHART). No V DD current will flow through R L if the switch current flows into terminal 1 on the HCF4067B.

TEST CIRCUIT

L R L = 200K ?

R T = Z OUT of pulse generator (typically 50?)

HCF4067B

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WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)

WAVEFORM : PROPAGATION DELAY TIMES

(f=1MHz; 50% duty cycle)

HCF4067B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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