补码除法器VHDL

Library IEEE;
Use IEEE.Std_logic_1164.ALL;
Use IEEE.Std_logic_unsigned.all;
Use IEEE.Std_logic_arith.all;

Entity Divider_Dec is
Generic(
Data_Width : integer;
Precision_Width : integer);
Port(
Dividend : in std_logic_vector(Data_Width-1 downto 0);
Divisor : in std_logic_vector(Data_Width-1 downto 0);
Quotient : Out std_logic_vector(Data_Width+Precision_Width-1 downto 0);
Error : Out std_logic
);
End Divider_Dec;

Architecture RTL of Divider_Dec Is
Component Adder_Subtracter
Generic(
Data_Width : integer);
Port(
Add_Sub : In Std_logic;
Minuend : In Std_logic_vector(Data_Width-1 downto 0);
Subtrahend : In Std_logic_vector(Data_Width-1 downto 0);
Sum_Diff : Out Std_logic_vector(Data_Width-1 downto 0));
End Component;

Type Array_Dividend Is Array (Data_Width+Precision_Width-1 downto 0) Of Std_logic_vector(Data_Width downto 0);
Signal Temp_Dividend : Array_Dividend;
Signal Temp_Remainder : Array_Dividend;
Signal Temp_Divisor : Std_logic_vector(Data_Width downto 0);
Signal Temp_Quotient : Std_logic_vector(Data_Width+Precision_Width-1 downto 0);
Signal Quotient_Final : Std_logic_vector(Data_Width-1 downto 0);
Signal Dividend_Dec : Std_logic_vector(Data_Width+Precision_Width-1 downto 0);
Signal Add_Sub : Std_logic_vector(Data_Width+Precision_Width-1 downto 0);
Signal Fill_Sign : Std_logic_vector(Data_Width-1 downto 0);
Signal Fill_High : Std_logic_vector(Data_Width-2 downto 0);
Signal Fill_Zero : Std_logic_vector(Precision_Width-1 downto 0);

Begin
Fill_High <= (Others => '1');
Fill_Zero <= (Others => '0');
Temp_Divisor <= Divisor(Data_Width-1) & Divisor;
Dividend_Dec <= Dividend & Fill_Zero;
--*****
Gen_Sign : For Index in 0 to Data_Width-1 Generate
Fill_Sign(Index) <= Dividend(Data_Width-1);
End Generate Gen_Sign;

Temp_Dividend(0) <= Fill_Sign & Dividend_Dec(Data_Width+Precision_Width-1);
Gen_Dividend : For Index in 0 to Data_Width+Precision_Width-2 Generate
Temp_Dividend(Index+1) <= Temp_Remainder(Index)(Data_Width-1 downto 0) & Dividend_Dec(Data_Width+Precision_Width-Index-2);
End Generate Gen_Dividend;

Gen_Add_Sub : For Index in 0 to Data_Width+Precision_Width-1 Generate
Add_Sub(Index) <= '1' When Temp_Dividend(Index)(Data_Width) = Temp_Divisor(Data_Width) Else '0';
End Generate Gen_Add_Sub;

Gen_Adder_Subtracter : For Index in 0 to Data_Width+Precision_Width-1 Generate
Inst_Adder_Subtracter : Adder_Subtracter
Generic Map(
Data_Width => Data_Width+1)
Port Map(
Add_Sub => Add_Sub(Index),
Minuend => Temp_Dividend(Index),
Subtrahend => Temp_Divisor,
Sum_Diff => Temp_Remainder(Index));
End Generate Gen_Adder_Subtracter;

Gen_Quotient : For Index in 0 to Data_Width+Precision_Width-1 Generate
Temp_Quotient(Data_Width+Precision_Width-I

ndex-1) <= '1' When Temp_Remainder(Index)(Data_Width) = Temp_Divisor(Data_Width) Else '0';
End Generate Gen_Quotient;

Quotient <= Temp_Quotient + 1 When Temp_Quotient(Data_Width+Precision_Width-1) = '1' Else Temp_Quotient;
--Remainder <= Temp_Remainder(Data_Width-1)(Data_Width-1 downto 0);
Error <= '1' when Divisor(Data_Width-2 downto 0) = 0 Else '0';
End RTL;