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P4C116L-12CMB中文资料

Document # SRAM110 REV A

P4C116/P4C116L

ULTRA HIGH SPEED 2K x 8STATIC CMOS RAMS

DESCRIPTION

The P4C116/P4C116L are 16,384-bit ultra high-speed static RAMs organized as 2K x 8. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V±10% tolerance power supply. Current drain is typically 10 μA from a 2.0V supply.

Access times as fast as 10 nanoseconds are available,permitting greatly enhanced system operating speeds.CMOS is used to reduce power consumption.

The P4C116 is available in 24-pin 300 mil DIP, SOJ and SOIC packages, a solder seal flatpack and 4 different LCC packages (24, 28, 32, and 40 pin).

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)– 10/12/15/20/25/35 ns (Commercial)

– 15/20/25/35 ns (Military)

Low Power Operation

Output Enable Control Function

Single 5V±10% Power Supply

Common Data I/O

Fully TTL Compatible Inputs and Outputs Produced with PACE II Technology

Standard Pinout (JEDEC Approved)– 24-Pin 300 mil DIP, SOIC, SOJ – 24-Pin Solder Seal Flat Pack

– 24-Pin Rectangular LCC (300 x 400 mils)– 28-Pin Square LCC (450 x 450 mils)

– 32-Pin Rectangular LCC (450 x 550 mils)– 40-Pin Square LCC (480 x 480 mils)

LCC configurations at end of datasheet

DIP (P4, C4), SOJ (J4), SOIC (S4)

SOLDER SEAL FLAT PACK (FS-1) SIMILAR

P4C116/P4C116L

MAXIMUM RATINGS (1)

Symbol Parameter Value Unit V CC

Power Supply Pin with –0.5 to +7V

Respect to GND Terminal Voltage with –0.5 to V TERM Respect to GND V CC +0.5V (up to 7.0V)

T A

Operating Temperature

–55 to +125

°C

Symbol Parameter Value Unit T BIAS Temperature Under –55 to +125°C Bias

T STG Storage Temperature –65 to +150

°C P T Power Dissipation 1.0W I OUT

DC Output Current

Symbol Parameter Conditions Typ.Unit C IN Input Capacitance

V IN = 0V

5pF C OUT

Output Capacitance V OUT = 0V

Grade (2)Ambient Temp Gnd

Vcc

Commercial 0°C to 70°C 0V 5.0V ±10%Military

-55°C to +125°C

5.0V ±10%

RECOMMENDED OPERATING CONDITIONS

CAPACITANCES (4)

(V CC = 5.0V, T A = 25°C, f = 1.0MHz)DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage (2) I SB

Standby Power Supply Current (TTL Input Levels)

CE ≥ V IH, Mil.V CC = Max, Ind./Com’l.f = Max., Outputs Open ______3020____________

1510

20n/a

1n/a

______

CE ≥ V HC , Mil.V CC = Max, Ind./Com’l.f = 0, Outputs Open V IN ≤ V LC or V IN ≥ V HC

Standby Power Supply Current

(CMOS Input Levels)

I SB1

Symbol V IH V IL V HC V LC V CD V OL V OH I LI I LO Parameter

Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage

Input Clamp Diode Voltage Output Low Voltage

(TTL Load)

Output High Voltage (TTL Load)

Input Leakage Current Output Leakage Current Test Conditions

V CC = Min., I IN = –18 mA I OL = +8 mA, V CC = Min.

I OH = –4 mA, V CC = Min.V CC = Max. Mil.V IN = GND to V CC Com’l.V CC = Max., CE = V IH , Mil.V OUT = GND to V CC Com’l.P4C116Min 2.2–0.5(3)V CC –0.2–0.5(3)

2.4–10–5–10–5Max V CC +0.50.8V CC +0.50.2–1.20.4

+10+5+10+5P4C116L Min Max 2.2–0.5(3)V CC –0.2–0.5(3)

2.4–5n/a –5n/a V CC +0.50.8V CC +0.5

0.20.4

–1.2+5n/a +5n/a Unit V V V V V V V μA μA

n/a = Not Applicable

AC ELECTRICAL CHARACTERISTICS—READ CYCLE

(V CC = 5V ± 10%, All Temperature Ranges)(2)

*V CC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = V IL , OE = V IH .

I CC

Symbol Parameter

Temperature

Range Dynamic Operating Current*

Commercial Military

–10N/A

–12–20–25–35Unit mA mA

POWER DISSIPATION CHARACTERISTICS VS. SPEED

N/A

170

160

155

150

180170160155150140–15DATA RETENTION CHARACTERISTICS (P4C116L Military Temperature Only)

Symbol V DR I CCDR t CDR t R ?

Parameter

V CC for Data Retention Data Retention Current Chip Deselect to

Data Retention Time Operation Recovery Time

Test Conditons CE ≥ V CC –0.2V,V IN ≥ V CC –0.2V or V IN ≤ 0.2V

Min 2.0

0t RC §

Typ.*V CC = 2.0V 3.0V Max V CC = 2.0V 3.0V

Unit 1015600900V

μA ns ns

*T A = +25°C

§t RC = Read Cycle Time

This parameter is guaranteed but not tested.

DATA RETENTION WAVEFORM

P4C116/P4C116L

TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)

Notes:

1.Stresses greater than those listed under MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification

is not implied. Exposure to MAXIMUM rating conditions for extended

periods may affect reliability.

2.Extended temperature operation guaranteed with 400 linear feet per

minute of air flow.

3.Transient inputs with V

IL and I

not more negative than –3.0V and

–100mA, respectively, are permissible for pulse widths up to 20 ns.4.This parameter is sampled and not 100% tested.

5.WE is HIGH for READ cycle.

6.CE is LOW and OE is LOW for READ cycle.

7.ADDRESS must be valid prior to, or coincident with CE transition

LOW.

8.Transition is measured ± 200 mV from steady state voltage prior to

change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested.

9.Read Cycle Time is measured from the last valid address to the first

transitioning address.

TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)

(5)

AC CHARACTERISTICS—WRITE CYCLE

(V CC = 5V ± 10%, All Temperature Ranges)(2)

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)

Notes:

10.CE and WE must be LOW for WRITE cycle.

11.OE is LOW for this WRITE cycle to show t WZ and t OW .

12.If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state

13.Write Cycle Time is measured from the last valid address to the first

transitioning address.

t WC Sym.t CW t AW t AS t WP t AH t DW t DH t WZ t OW

Parameter

Write Cycle Time

Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time

Write Enable to Output in High Z Output Active from End of Write

–10–12–15–20

–25–35

Unit Min Max Min Max Min Max Min Max Min Max Min Max

1512120120100

2015150150120

2518180180150

35252502002000

ns ns

ns ns ns ns ns ns ns ns

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)

108808070

6121010010080

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P4C116/P4C116L

Mode CE OE WE I/O Power Standby H X X High Z Standby D OUT

Disabled L H H High Z Active Read L L H D OUT Active Write

High Z

Active

Input Pulse Levels GND to 3.0V

Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V

Output Load

See Figures 1 and 2

AC TEST CONDITIONS

TRUTH TABLE

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test fixture.

Note:

Because of the ultra-high speed of the P4C116/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 μF high frequency

capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50? test environment should be terminated into a 50? load with 1.73V (Thevenin Voltage) at the comparator input, and a 116? resistor must be used in series with D OUT to match 166? (Thevenin Resistance).

24-Pin LCC (L8)

28-Pin LCC (L5-1)

LCC PIN CONFIGURATIONS

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P4C116/P4C116L

ORDERING INFORMATION

N/A = Not Available

SELECTION GUIDE

The P4C116 is available in the following temperature, speed and package options.

SIDE BRAZED DUAL IN-LINE PACKAGE

SOLDER SEAL FLATPACK

P4C116/P4C116L

SOJ SMALL OUTLINE IC PACKAGE

SQUARE LEADLESS CHIP CARRIER

RECTANGULAR LEADLESS CHIP CARRIER

P4C116/P4C116L

SQUARE LEADLESS CHIP CARRIER

SOIC/SOP SMALL OUTLINE IC PACKAGE

P4C116/P4C116L

REVISIONS

DOCUMENT NUMBER:SRAM110

DOCUMENT TITLE:P4C116 / P4C116L ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS

REV.ISSUE

DATE

ORIG. OF

CHANGE

DESCRIPTION OF CHANGE

OR1997DAB New Data Sheet

A Oct-05JD

B Change logo to Pyramid