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CY7C1049CV33-15ZE中文资料

4-Mbit (512K x 8) Static RAM

CY7C1049CV33

Features

?Temperature Ranges —Commercial: 0°C to 70°C —Industrial: –40°C to 85°C —Automotive: –40°C to 125°C ?High speed —t AA = 10 ns ?Low active power —324 mW (max.)?2.0V data retention

?Automatic power-down when deselected ?TTL-compatible inputs and outputs

Easy memory expansion with CE and OE features

Functional Description [1]

The CY7C1049CV33 is a high-performance CMOS Static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers.Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O 0 through I/O 7) is then written into the location specified on the address pins (A 0 through A 18).

Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O 0 through I/O 7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW).

The CY7C1049CV33 is available in standard 400-mil-wide 36-pin SOJ package and 44-pin TSOP II package with center power and ground (revolutionary) pinout.

Notes:

1.For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at https://www.wendangku.net/doc/f53418253.html,.

1415Logic Block Diagram Pin Configuration

A 1A 2A 3A 4A 5A 6A 7A 8COLUMN DECODER

R O W D E C O D E R

S E N S E A M P S

INPUT BUFFER

POWER DOWN

WE OE

I/O 0

I/O 1

I/O 2

I/O 3512K x 8ARRAY

I/O 7

I/O 6I/O 5

I/O 4A 0A 11A 13A 12A CE A A 16A 1712345678910111423242827262529323130Top View

SOJ 12133336353416152122GND A 1A 2A 3A 4A 5A 6A 7A 8WE V CC A 18A 15A 12A 14I/O 5I/O 4A 9A 0I/O 0I/O 1I/O 2OE A 17A 16A 13CE A 9A 18

1719

20GND I/O 7I/O 3I/O 6V CC A 10A 11NC NC

A 10

A 612345678910111431323635343337403938Top View

TSOP II 12134144434216152930V CC A 7A 8A 9NC NC

NC NC A 18V SS NC A 15A 0A 3I/O 0A 4CE A 17A 12A 1A 218172019I/O 12728252622

2123

24NC

V SS WE I/O 2I/O 3A 5NC A 16V CC OE I/O 7I/O 6I/O 5I/O 4A 14A 13A 11A 10NC NC NC

Selection Guide

-8[]-10-12-15Unit Maximum Access Time8101215ns Maximum Operating Current Commercial100908580mA

Industrial1101009590mA

Automotive---95mA Maximum CMOS Standby Current Commercial / Industrial10101010mA

Automotive---15mA Shaded areas contain advance information.

Pin Definitions

Pin Name

36-SOJ

Pin Number

44 TSOP-II

Pin Number I/O Type Description

A0-A181-5,14-18,

20-24,32-35

3-7,16-20,

26-30,38-41

Input Address Inputs used to select one of the address locations.

I/O0 - I/O77,8,11,12,25,

26,29,309,10,13,14,

31,32,35,36

Input/Output Bidirectional Data I/O lines. Used as input or output lines

depending on operation

NC[2]19,361,2,21,22,23,

24,25,42,43,

No Connect No Connects. This pin is not connected to the die

WE1315Input/Control Write Enable Input, active LOW. When selected LOW, a WRITE

is conducted. When selected HIGH, a READ is conducted.

CE68Input/Control Chip Enable Input, active LOW. When LOW, selects the chip.

When HIGH, deselects the chip.

OE3137Input/Control Output Enable, active LOW. Controls the direction of the I/O pins.

When LOW, the I/O pins are allowed to behave as outputs. When

deasserted HIGH, I/O pins are three-stated, and act as input data

pins.

V SS, GND10,2812,34Ground Ground for the device. Should be connected to ground of the

system.

V CC9,2711,33Power Supply Power Supply inputs to the device.

Notes:

2.NC pins are not connected on the die.

Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)

Storage Temperature .................................–65°C to +150°C Ambient Temperature with

Power Applied.............................................–55°C to +125°C Supply Voltage on V CC to Relative GND[3]....–0.5V to +4.6V DC Voltage Applied to Outputs

in High-Z State[3]....................................–0.5V to V CC + 0.5V DC Input Voltage[3]................................–0.5V to V CC + 0.5V Current into Outputs (LOW).........................................20 mA Operating Range

Range Ambient Temperature V CC Commercial0°C to +70°C 3.3V ± 0.3V Industrial–40°C to +85°C

Automotive–40°C to +125°C

Electrical Characteristics Over the Operating Range

Parame-

ter Description Test Conditions

-8[]-10-12-15

Unit Min.Max.Min.Max.Min.Max.Min.Max.

V OH Output HIGH Voltage V CC = Min.; I OH = –4.0 mA 2.4 2.4 2.4 2.4V V OL Output LOW Voltage V CC = Min.,; I OL = 8.0 mA0.40.40.40.4V

V IH Input HIGH Voltage 2.0V CC

+ 0.32.0V CC

+ 0.3

2.0V CC

+ 0.3

2.0V CC

+ 0.3

V IL Input LOW Voltage[3]–0.30.8–0.30.8–0.30.8–0.30.8V I IX Input Load Current GND < V I < V CC Com’l / Ind’l–1+1–1+1–1+1–1+1μA

Automotive------–20+20μA

I OZ Output Leakage

Current GND < V OUT <

V CC,

Output Disabled

Com’l / Ind’l–1+1–1+1–1+1–1+1μA

Automotive------–20+20μA

I CC V CC Operating

Supply Current V CC = Max.,

f = f MAX = 1/t RC

Com’l100908580mA

Ind’l1101009590mA

Automotive---95mA

I SB1Automatic CE

Power-down Current

—TTL Inputs Max. V CC, CE >

V IH; V IN > V IH or

V IN < V IL, f = f MAX

Com’l / Ind’l40404040mA

Automotive---45mA

I SB2Automatic CE

Power-down Current

—CMOS Inputs Max. V CC,

CE > V CC – 0.3V,

V IN > V CC – 0.3V,

or V IN < 0.3V, f = 0

Com’l/Ind’l10101010mA

Automotive---15mA

Capacitance[4]

Parameter Description Test Conditions Max.Unit

C IN Input Capacitance T A = 25°C, f = 1 MHz,

V CC = 3.3V 8pF

C OUT I/O Capacitance8pF Thermal Resistance[4]

Parameter Description Test Conditions 36-pin SOJ

(Non

Pb-Free)

36-pin SOJ

( Pb-Free)

44-TSOP-II

(Non

Pb-Free)

44-TSOP-II

( Pb-Free)Unit

ΘJA Thermal Resistance

(Junction to

Ambient)Test conditions follow

standard test methods

and procedures for

measuring thermal

impedance, per EIA /

JESD51.

46.5146.51 41.66 41.66°C/W

ΘJC Thermal Resistance

(Junction to Case)

18.818.810.5610.56°C/W

Notes:

3.V IL (min.) = –2.0V and V IH(max) = V CC + 0.5V for pulse durations of less than 20 ns.

4.Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms [5]

90%10%

3.0V GND

90%10%

ALL INPUT PULSES 3.3V OUTPUT

30 pF

* CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT

(b)

R 317?

R2351?

Rise Time: 1 V/ns

Fall Time: 1 V/ns

30 pF*

OUTPUT

Z = 50?

50?

1.5V

(c)

(a)

3.3V

OUTPUT

5 pF

(d)

R 317?

R2351?

8-, 10-ns devices:

12-, 15-ns devices:

High-Z characteristics:

AC Switching Characteristics [6] Over the Operating Range

Parameter Description -8[]

-10-12-15Unit Min.Max.

Min.Max.

Read Cycle t power [7]V CC (typical) to the first access 1111μs t RC Read Cycle Time 810

t AA Address to Data Valid

1215ns t OHA Data Hold from Address Change 3

3ns t ACE CE LOW to Data Valid 8101215ns t DOE OE LOW to Data Valid 4

7ns t LZOE OE LOW to Low-Z 00

ns t HZOE OE HIGH to High-Z [8, 9]4

7ns t LZCE CE LOW to Low-Z [9]33

ns t HZCE CE HIGH to High-Z [8, 9]4

7ns t PU CE LOW to Power-up 0

ns t PD CE HIGH to Power-down 8

ns Write Cycle [10, 11]

t WC Write Cycle Time 8101215ns t SCE CE LOW to Write End 67810ns t AW Address Set-up to Write End 67810ns t HA Address Hold from Write End 0000ns t SA Address Set-up to Write Start 0000ns t PWE WE Pulse Width 67810ns t SD Data Set-up to Write End 4567ns t HD Data Hold from Write End 0000ns t LZWE WE HIGH to Low-Z

[9]

t HZWE

WE LOW to High-Z [8, 9]

Notes:

5.AC characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).

Switching Waveforms

Read Cycle No. 1[12, 13]

Read Cycle No. 2 (OE Controlled)[13, 14]

Notes:

6.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.

7.t POWER gives the minimum amount of time that the power supply should be at stable, typical V CC values until the first memory access can be performed.8.t HZOE , t HZCE , and t HZWE are specified with a load capacitance of 5 pF as in part (d) of AC T est Loads. Transition is measured ±500 mV from steady-state voltage.9.At any given temperature and voltage condition, t HZCE is less than t LZCE , t HZOE is less than t LZOE , and t HZWE is less than t LZWE for any given device.

10.The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these

signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.11.The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t HZWE and t SD .12.Device is continuously selected. OE, CE = V IL .13.WE is HIGH for Read cycle.

PREVIOUS DATA VALID

DATA VALID

t RC

t AA

t OHA

ADDRESS

DATA OUT

50%

DATA VALID

t RC

t ACE

t DOE

t LZOE

t LZCE t PU

HIGH IMPEDANCE

t HZOE

t HZCE

t PD

HIGH OE

I CC I SB

IMPEDANCE

ADDRESS

DATA OUT V CC SUPPLY CURRENT

Write Cycle No. 1(WE Controlled, OE HIGH During Write)[15, 16]

Write Cycle No. 2 (WE Controlled, OE LOW)[16]

Notes:

14.Address valid prior to or coincident with CE transition LOW.15.Data I/O is high-impedance if OE = V IH .

16.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.17.During this period the I/Os are in the output state and input signals should not be applied.

Switching Waveforms (continued)

t HD

t SD

t PWE

t SA

t HA

t AW

t SCE

t WC

t HZOE

DATA IN VALID

ADDRESS

DATA I/O

NOTE 17

DATA VALID

t HD

t SD

t LZWE

t PWE

t SA

t HA

t AW

t SCE

t WC

t HZWE

ADDRESS

DATA I/O

NOTE 17

Truth Table

CE OE WE I/O0–I/O7Mode Power

H X X High-Z Power-down Standby (I SB)

L L H Data Out Read Active (I CC) L X L Data In Write Active (I CC) L H H High-Z Selected, Outputs Disabled Active (I CC)

Ordering Information

Speed

(ns)Ordering Code Package

Name Package Type

Operating

Range

10CY7C1049CV33-10VC V3636-lead (400-Mil) Molded SOJ Commercial CY7C1049CV33-10ZC Z4444-pin TSOP II

CY7C1049CV33-10VI V3636-lead (400-Mil) Molded SOJ Industrial CY7C1049CV33-10ZI Z4444-pin TSOP II

12CY7C1049CV33-12VC V3636-lead (400-Mil) Molded SOJ Commercial CY7C1049CV33-12ZC Z4444-pin TSOP II

CY7C1049CV33-12VI V3636-lead (400-Mil) Molded SOJ Industrial CY7C1049CV33-12ZI Z4444-pin TSOP II

15CY7C1049CV33-15VXC V3636-lead (400-Mil) Molded SOJ (Pb-Free)Commercial CY7C1049CV33-15VC V3636-lead (400-Mil) Molded SOJ

CY7C1049CV33-15ZXC Z4444-pin TSOP II (Pb-Free)

CY7C1049CV33-15ZC Z4444-pin TSOP II

CY7C1049CV33-15VI V3636-lead (400-Mil) Molded SOJ Industrial CY7C1049CV33-15ZI Z4444-pin TSOP II

CY7C1049CV33-15VE V3636-lead (400-Mil) Molded SOJ Automotive CY7C1049CV33-15ZE Z4444-pin TSOP II

Document #: 38-05006 Rev. *C

Page 8 of 9

All products and company names mentioned in this document may be the trademarks of their respective holders.Package Diagrams

36-Lead (400-Mil) Molded SOJ V36

51-85090-B

44-pin TSOP II Z44

51-85087-*A

Document History Page

Document Title: CY7C1049CV33 4-Mbit (512K x 8) Static RAM Document Number: 38-05006

REV.ECN NO.Issue

Date

Orig. of

Change Description of Change

**11256903/06/02HGK New Data Sheet

*A11409104/25/02DFP Changed Tpower unit from ns to μs

*B11647909/16/02CEA Add applications foot note to data sheet, page 1. *C262949See ECN RKF Added Automotive Specs to Datasheet

Added ΘJA and ΘJC values on Page #3.