PAL_D电视信号VHDL及VERILOG HDL程序代码
PAL_D电视信号VHDL以及verilog源程序！
FPGA设计PAL_D电视信号！VHDL源程序！两个程序都是黑白的video信号，输出可以直接在视频显示器上显示。
--############################################################## ###############
-- File Name :TV_SIGNAL05.VHD
-- Version: 1.0 Data :
-- Time : 11:52
-- Author : Email: htank@https://www.wendangku.net/doc/f73560976.html,
-- Commany:
-- LOGIC CORE: TV SIGNLA module
-- MODULE NAME: TV_SIGNAL04
-- FUNCTIONAL DESCRIPTION :
-- This module is the TV SIGNAL.
--
-- Copyright (C)1997-2003 *****Corporation
--############################################################## ###############
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TV_SIGNAL05 IS
PORT(
VCLK_39 : IN STD_LOGIC; --3.9mhz
VCLK_165 : IN STD_LOGIC; ---16.5mhz
VIDEO : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END TV_SIGNAL05 ;
ARCHITECTURE a OF TV_SIGNAL05 IS
SIGNAL HRST_D : STD_LOGIC;
SIGNAL HRST_B_D : STD_LOGIC;
SIGNAL VRST_B_D : STD_LOGIC;
SIGNAL HSYNC_L,VSYNC_L : STD_LOGIC;
SIGNAL COM_VH_D,COM_VH_DD : STD_LOGIC;
SIGNAL VRST_B_DD : STD_LOGIC;
SIGNAL VLINE : INTEGER RANGE 0 TO 625;
SIGNAL RESET : STD_LOGIC;
SIGNAL COM_VH_B_D : STD_LOGIC;
BEGIN
PROCESS (VCLK_39)
VARIABLE temp : INTEGER RANGE 0 TO 31;
BEGIN
IF (Vclk_39'EVENT AND Vclk_39= '1') THEN
IF TEMP>=20 THEN
RESET <='1';
ELSE
RESET <='0';
TEMP:= TEMP +1;
END IF;
END IF;
END PROCESS;
PROCESS (VCLK_39,reset) ----TV,VGA_TV_ST
VARIABLE temp_tv : INTEGER RANGE 0 TO 255;
VARIABLE VLINE : INTEGER RANGE 0 TO 628; －－－2003.10.20修改
BEGIN
IF reset ='0' THEN --VGA_TV_ST='1' OR
temp_tv := 0;
VLINE:= 1;
ELSIF (VCLK_39'EVENT AND VCLK_39= '1') THEN
temp_tv :=temp_tv + 1;
IF temp_tv=252 THEN ---------0---237---238 POINT-238252
temp_tv :=0;
VLINE :=VLINE+ 1;
END IF;
IF VLINE=626 THEN-----1--617 =617
VLINE:=1;
END IF;
IF temp_tv>=5 AND temp_tv <=22 THEN---5--22--18---------FOR HRST HRST_D<='1';-------5--22---18
ELSE
HRST_D <='0';
END IF;
IF temp_tv>=1 AND temp_tv <=52 THEN ---1--38--38------FOR HRST BANK HRST_B_D<='1';----0--51--52
ELSE
HRST_B_D<='0';
END IF;
IF VLINE>=1 AND VLINE<=23 THEN -----FOR VRST BANK--18
VRST_B_D<='1';
ELSIF VLINE >=311 AND VLINE <=335 THEN----21
VRST_B_D<='1';
ELSIF VLINE >=622 AND VLINE <=625 THEN---3 ---18+21+3＝42 VRST_B_D<='1';
ELSE
VRST_B_D<='0';
END IF;
IF VLINE>=1 AND VLINE <=2 THEN --------FOR COM_VH IF temp_tv>=5 AND temp_tv<=113 THEN
COM_VH_D <='1';
ELSIF temp_tv>=131 AND temp_tv<=239 THEN
COM_VH_D <='1';
ELSE
COM_VH_D <='0';
END IF;
ELSIF VLINE =3 THEN
IF temp_tv>=5 AND temp_tv<=113 THEN-----105---111
COM_VH_D <='1';
ELSIF temp_tv>=131 AND temp_tv<=139 THEN
COM_VH_D <='1';--old-124-132---- new-131--237
ELSE
COM_VH_D <='0';
END IF;
ELSIF VLINE>=4 AND VLINE<=5 THEN
IF temp_tv>=5 AND temp_tv<=13 THEN
COM_VH_D <='1';
ELSIF temp_tv>=131 AND temp_tv<=139 THEN
COM_VH_D <='1';
ELSE
COM_VH_D <='0';
END IF;
ELSIF VLINE>=6 AND VLINE<=310 THEN
IF temp_tv>=5 AND temp_tv<=22 THEN
COM_VH_D <='1';
ELSE
COM_VH_D <='0';
END IF;
ELSIF VLINE>=311 AND VLINE<=312 THEN
IF temp_tv>=5 AND temp_tv<=13 THEN
COM_VH_D <='1';
ELSIF temp_tv>=131 AND temp_tv<=139 THEN
COM_VH_D <='1';
ELSE
END IF;
ELSIF VLINE =313 THEN
IF temp_tv>=5 AND temp_tv<=13 THEN
COM_VH_D <='1';
ELSIF temp_tv>=131 AND temp_tv<=239 THEN COM_VH_D <='1';
ELSE
COM_VH_D <='0';
END IF;
ELSIF VLINE>=314 AND VLINE<=315 THEN
IF temp_tv>=5 AND temp_tv<=113 THEN
COM_VH_D <='1';
ELSIF temp_tv>=131 AND temp_tv<=239 THEN COM_VH_D <='1';
ELSE
COM_VH_D <='0';
END IF;
ELSIF VLINE>=316 AND VLINE<=317 THEN
IF temp_tv>=5 AND temp_tv<=13 THEN
COM_VH_D <='1';
ELSIF temp_tv>=131 AND temp_tv<=139 THEN COM_VH_D <='1';
ELSE
COM_VH_D <='0';
END IF;
ELSIF VLINE =318 THEN
IF temp_tv>=5 AND temp_tv<=13 THEN
COM_VH_D <='1';
ELSE
COM_VH_D <='0';
END IF;
ELSIF VLINE>=319 AND VLINE<=622 THEN
IF temp_tv>=5 AND temp_tv<=22 THEN
COM_VH_D <='1';
ELSE
COM_VH_D <='0';
END IF;
ELSIF VLINE =623 THEN
IF temp_tv>=5 AND temp_tv<=22 THEN
COM_VH_D <='1';
ELSIF temp_tv>=131 AND temp_tv<=139 THEN COM_VH_D <='1';
ELSE
END IF;
ELSIF VLINE>=624 AND VLINE<=625 THEN
IF temp_tv>=5 AND temp_tv<=13 THEN
COM_VH_D <='1';
ELSIF temp_tv>=131 AND temp_tv<=139 THEN
COM_VH_D <='1';
ELSE
COM_VH_D <='0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS( VCLK_39)
BEGIN
IF VCLK_39'EVENT AND VCLK_39='1' THEN
COM_VH_DD <= COM_VH_D;
--COM_VH_B <=VRST_B_D OR HRST_B_D;
COM_VH_B_D <=VRST_B_D OR HRST_B_D;
--VRST_B <=VRST_B_D;
--HRST <=HRST_D;
--HRST_B <=HRST_B_D;
END IF;
END PROCESS;
PROCESS( CLK_165)
-- VARIABLE DATA_O : STD_LOGIC_VECTOR (7 DOWNTO 0);
VARIABLE TTT : STD_LOGIC_VECTOR (9 DOWNTO 0);
VARIABLE IMAGE : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF ( CLK_165'EVENT AND CLK_165='1') THEN
IF COM_VH_B_D ='1' THEN
IMAGE := (OTHERS=>'0');
TTT := (OTHERS=>'0');
VIDEO <= (NOT COM_VH_DD) & '0'&"00000000";
ELSIF COM_VH_B_D ='0' THEN
TTT := TTT + 1;
IF ( (VLINE >=24 AND VLINE <=124) or ( VLINE >=335 AND VLINE <=436 ) )THEN---2 IF TTT>=0 AND TTT <=75 THEN ---------FOR VIDEO OUT
IMAGE:="00001111";-- TV_TT:=TV_TT+1;
ELSIF TTT>=76 AND TTT <=150 THEN ---------FOR VIDEO OUT
IMAGE:="00100000";-- TV_TT:=TV_TT+1;
ELSIF TTT>=151 AND TTT <=225 THEN ---------FOR VIDEO OUT IMAGE:="00101111";-- TV_TT:=TV_TT+1;
ELSIF TTT>=226 AND TTT <=300 THEN ---------FOR VIDEO OUT IMAGE:="01000000";-- TV_TT:=TV_TT+1;
ELSIF TTT>=301 AND TTT <=375 THEN ---------FOR VIDEO OUT IMAGE:="01001111";-- TV_TT:=TV_TT+1;
ELSIF TTT>=376 AND TTT <=450 THEN ---------FOR VIDEO OUT IMAGE:="01100000";-- TV_TT:=TV_TT+1;
ELSIF TTT>=451 AND TTT <=525 THEN ---------FOR VIDEO OUT IMAGE:="01101111";-- TV_TT:=TV_TT+1;
ELSIF TTT>=526 AND TTT <=600 THEN ---------FOR VIDEO OUT IMAGE:="11111111";-- TV_TT:=TV_TT+1;
ELSE
IMAGE:="00000000";
END IF;
ELSE
IMAGE:=(OTHERS=>'0');
END IF;
VIDEO <= (NOT COM_VH_DD)&'1'&IMAGE;
END IF;
END IF;
END PROCESS;
END a;
FPGA设计PAL_D电视信号！verilog源程序！
verilog 版本：
/*
信号定义与说明：
clk_66MHz:input clock with a frequency of 66MHz;
clk_33MHz:division twice from clk_66MHz;
clk_4MHz: division from clk_33MHz,as a matter of fact,its frequency is 4.125MHz; H_HIDE: 行消隐信号；
V_HIDE: 场消隐信号；
COM_HIDE:复合消隐信号；
H_SYNC: 行同步信号；
V_SYNC: 场同步信号；
COM_SYNC：复合同步信号；
Gray：扫描灰阶图像信号；
front_balance,back_balance:前后均衡脉冲；
Slot_ON_V_SYNC:场同步期中的槽脉冲；*/
module
tv_sig_gen(clk_66MHz,clk_33MHz,clk_4MHz,H_HIDE,V_HIDE,H_SYNC,Gray,COM_HIDE,front_balance,ba ck_balance,Slot_ON_V_SYNC,V_SYNC,COM_SYNC);
parameter size=4; //定义一个寄存器的大小，产生4MHz时钟用；
input clk_66MHz;
output
clk_33MHz,clk_4MHz,H_HIDE,V_HIDE,H_SYNC,Gray,COM_HIDE,front_balance,back_balance,Slot_ON_V _SYNC,V_SYNC,COM_SYNC;
reg[size-1:0] reg_for_4MHz;
reg[8:0] Counter_For_H_SYNC;
reg[9:0] Hcounter;
reg[7:0] Gray;
reg[3:0] counter_for_Gray;
reg
clk_33MHz,clk_4MHz,temp,H_HIDE,V_HIDE,H_SYNC,front_balance,back_balance,Slot_ON_V_SYNC,V_S YNC,Htongbu_mask;
wire COM_HIDE,COM_SYNC;
assign COM_SYNC=(front_balance|back_balance|Slot_ON_V_SYNC)|((!Htongbu_mask)&H_SYNC); assign COM_HIDE=H_HIDE||V_HIDE;
always @(posedge clk_66MHz) //产生33MHz频率时钟;
clk_33MHz=~clk_33MHz;
always @(posedge clk_33MHz)
begin
if(reg_for_4MHz==0) reg_for_4MHz=1; //对寄存器进行初始化;
else
begin
if(reg_for_4MHz[size-1]) clk_4MHz=~clk_4MHz; //每size个时钟脉冲clk_4MHz跳变;
temp=reg_for_4MHz[size-1]; //暂存;
reg_for_4MHz[size-1:1]=reg_for_4MHz[size-2:0];
reg_for_4MHz[0]=temp;
end
end
always @(posedge clk_4MHz) //产生行消隐信号,行同步信号;
begin
case(Counter_For_H_SYNC)
213: begin
Counter_For_H_SYNC=Counter_For_H_SYNC+1;
H_HIDE=~H_HIDE;
end
219: begin
Counter_For_H_SYNC=Counter_For_H_SYNC+1;
H_SYNC=~H_SYNC;
end
238: begin
Counter_For_H_SYNC=Counter_For_H_SYNC+1;
H_SYNC=~H_SYNC;
end
263: begin
Counter_For_H_SYNC=0;
H_HIDE=~H_HIDE;
end
default:Counter_For_H_SYNC=Counter_For_H_SYNC+1;
endcase
end
always @(posedge clk_4MHz) //在行正程产生灰阶信号; begin
case(H_HIDE)
0: begin
case(counter_for_Gray)
12: begin //每13个4MHz时钟周期灰阶加一；
counter_for_Gray=0;
Gray[7:4]=Gray[7:4]+1;
end
default:
counter_for_Gray=counter_for_Gray+1;
endcase
end
1: begin
counter_for_Gray=0;
Gray=0;
end
endcase
end
always @(posedge clk_4MHz) //产生场消隐信号；
begin
case(Counter_For_H_SYNC)
82: case(Hcounter)
286: V_HIDE=~V_HIDE;
311: V_HIDE=~V_HIDE;
endcase
263: case(Hcounter)
599:V_HIDE=~V_HIDE;
624:V_HIDE=~V_HIDE;
endcase
endcase
end
always @(posedge H_HIDE) //行计数；
begin
case(Hcounter)
624: Hcounter=0;
default:Hcounter=Hcounter+1;
endcase
end
always @(posedge clk_4MHz)
begin
case(Counter_For_H_SYNC)
82: case(Hcounter)
286: begin front_balance=~front_balance; Htongbu_mask=~Htongbu_mask; end 287: front_balance=~front_balance;
288: front_balance=~front_balance;
291: back_balance=~back_balance;
292: back_balance=~back_balance;
293: back_balance=~back_balance;
endcase
92: case(Hcounter)
286: front_balance=~front_balance;
287: front_balance=~front_balance;
288: front_balance=~front_balance;
291: back_balance=~back_balance;
292: back_balance=~back_balance;
293: begin back_balance=~back_balance; Htongbu_mask=~Htongbu_mask; end endcase
213: case(Hcounter)
286: front_balance=~front_balance;
287: front_balance=~front_balance;
291: back_balance=~back_balance;
292: back_balance=~back_balance;
endcase
222: case(Hcounter)
287: front_balance=~front_balance;
288: front_balance=~front_balance;
292: back_balance=~back_balance;
293: back_balance=~back_balance;
endcase
263: case(Hcounter)
599: begin front_balance=~front_balance; Htongbu_mask=~Htongbu_mask; end 600: front_balance=~front_balance;
601: front_balance=~front_balance;
604: back_balance=~back_balance;
605: back_balance=~back_balance;
606: back_balance=~back_balance;
endcase
9: case(Hcounter)
599: front_balance=~front_balance;
600: front_balance=~front_balance;
601: front_balance=~front_balance;
604: back_balance=~back_balance;
605: back_balance=~back_balance;
606: begin back_balance=~back_balance; Htongbu_mask=~Htongbu_mask; end endcase
130: case(Hcounter)
599: front_balance=~front_balance;
600: front_balance=~front_balance;
604: back_balance=~back_balance;
605: back_balance=~back_balance;
endcase
140: case(Hcounter)
599: front_balance=~front_balance;
600: front_balance=~front_balance;
604: back_balance=~back_balance;
605: back_balance=~back_balance;
endcase
endcase
end
always @(posedge clk_4MHz)
begin
case(Counter_For_H_SYNC)
79: case(Hcounter)
291: V_SYNC=~V_SYNC;
endcase
131: case(Hcounter)
601: V_SYNC=~V_SYNC;
213: case(Hcounter)
288: V_SYNC=~V_SYNC;
endcase
263: case(Hcounter)
604: V_SYNC=~V_SYNC;
endcase
endcase
end
always @(posedge clk_4MHz)
begin
case(Counter_For_H_SYNC)
213: case(Hcounter)
288: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
62: case(Hcounter)
289: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
290: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
291: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
81: case(Hcounter)
289: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
290: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
endcase
131: case(Hcounter)
601: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
200: case(Hcounter)
289: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
290: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
601: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
602: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
603: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
219: case(Hcounter)
290: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
291: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
602: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
603: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
68: case(Hcounter)
602: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
603: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
87: case(Hcounter)
602: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
603: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
endcase
endcase
end
/*
always @(posedge H_HIDE)
begin
case(Hcounter)
286: begin
if(Counter_For_H_SYNC==130) V_HIDE=~V_HIDE; //第287行的第32us时刻场消隐开始; Hcounter=Hcounter+1;
end
311: begin
if(Counter_For_H_SYNC==130) V_HIDE=~V_HIDE;
Hcounter=Hcounter+1;
end
599: begin
if(Counter_For_H_SYNC==263) V_HIDE=~V_HIDE;
Hcounter=Hcounter+1;
end
624: begin
if(Counter_For_H_SYNC==263) V_HIDE=~V_HIDE;
Hcounter=0;
end
default:Hcounter=Hcountr+1;
endcase
end
*/
/*
always @(posedge clk_4MHz)
begin
case(Counter_For_H_SYNC)
82: case(Hcounter)
286: front_balance=~front_balance;
287: front_balance=~front_balance;
288: front_balance=~front_balance;
291: back_balance=~back_balance;
292: back_balance=~back_balance;
293: back_balance=~back_balance;
endcase
92: case(Hcounter)
286: front_balance=~front_balance; 287: front_balance=~front_balance; 288: front_balance=~front_balance; 291: back_balance=~back_balance; 292: back_balance=~back_balance; 293: back_balance=~back_balance;
endcase
213: case(Hcounter)
286: front_balance=~front_balance; 287: front_balance=~front_balance; 291: back_balance=~back_balance; 292: back_balance=~back_balance;
endcase
222: case(Hcounter)
287: front_balance=~front_balance; 288: front_balance=~front_balance; 292: back_balance=~back_balance; 293: back_balance=~back_balance; endcase
263: case(Hcounter)
599: front_balance=~front_balance; 600: front_balance=~front_balance; 601: front_balance=~front_balance; 604: back_balance=~back_balance; 605: back_balance=~back_balance; 606: back_balance=~back_balance;
endcase
9: case(Hcounter)
599: front_balance=~front_balance; 600: front_balance=~front_balance; 601: front_balance=~front_balance; 604: back_balance=~back_balance; 605: back_balance=~back_balance; 606: back_balance=~back_balance;
endcase
130: case(Hcounter)
599: front_balance=~front_balance; 600: front_balance=~front_balance; 604: back_balance=~back_balance; 605: back_balance=~back_balance;
endcase
140: case(Hcounter)
599: front_balance=~front_balance;
600: front_balance=~front_balance;
604: back_balance=~back_balance;
605: back_balance=~back_balance;
endcase
endcase
end
always @(posedge clk_4MHz)
begin
case(Counter_For_H_SYNC)
82: case(Hcounter)
291: V_SYNC=~V_SYNC;
endcase
263: case(Hcounter)
288: V_SYNC=~V_SYNC;
603: V_SYNC=~V_SYNC;
endcase
131: case(Hcounter)
601: V_SYNC=~V_SYNC;
endcase
endcase
end
always @(posedge clk_4MHz)
begin
case(Counter_For_H_SYNC)
263: case(Hcounter)
288: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
117: case(Hcounter)
289: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
136: case(Hcounter)
289: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
253: case(Hcounter)
289: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
6: case(Hcounter)
290: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
291: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
602: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
603: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
604: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
118: case(Hcounter)
290: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
291: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
602: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
603: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
137: case(Hcounter)
290: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
602: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
endcase
249: case(Hcounter)
290: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
602: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
603: Slot_ON_V_SYNC=~Slot_ON_V_SYNC;
604: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
131: case(Hcounter)
601: Slot_ON_V_SYNC=~Slot_ON_V_SYNC; endcase
endcase
*/
endmodule