IDT74244TSO中文资料

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1995

The IDT octal buffer/line drivers are built using an advanced dual metal CMOS technology. The FCT240T/FCT2240T and FCT244T/FCT2244T are designed to be employed as memory and address drivers, clock drivers and bus-oriented transmit-ter/receivers which provide improved board density.

The FCT540T and FCT541T/FCT2541T are similar in function to the FCT240T/FCT2240T and FCT244T/FCT2244T,respectively, except that the inputs and outputs are on oppo-site sides of the package. This pinout arrangement makes these devices especially useful as output ports for micropro-cessors and as backplane drivers, allowing ease of layout and greater board density.

The FCT2240T, FCT2244T and FCT2541T have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resis-tors. FCT2xxxT parts are plug-in replacements for FCTxxxT parts.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

?Common features:

–Low input and output leakage ≤1μA (max.)–CMOS power levels

–True TTL input and output compatibility – V OH = 3.3V (typ.)– V OL = 0.3V (typ.)

–Meets or exceeds JEDEC standard 18 specifications –Product available in Radiation Tolerant and Radiation Enhanced versions

–Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked)

–Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages

?Features for FCT240T/FCT244T/FCT540T/FCT541T:–Std., A, C and D speed grades

–High drive outputs (-15mA I OH , 64mA I OL )?Features for FCT2240T/FCT2244T/FCT2541T:–Std., A and C speed grades

–Resistor outputs (-15mA I OH , 12mA I OL Com.)

(-12mA I OH , 12mA I OL Mil.)

–Reduced system switching noise

2565 drw 03

2565 drw 02

2565 drw 01

DA 0DA 1DA 2DA 3DB 0DB 1DB 2DB 3

FCT240/2240T

DA 0OB 0DA 1OB 1DA 2OB 2DA 3OB 3OA 0DB 0OA 1DB 1DB 2DB 3

OA 2OA 3FCT244/2244T D O 0D D D D D D D O 1O 2O 3O 4O 5O 6O 7

FCT540/541/2541T

*Logic diagram shown for 'FCT540.

'FCT541/2541T is the non-inverting option.

OE A

OE B

OE A

OE B OE OB 0OB 1OB 2OB 3

OE B

OA 0OA 1OA 2OA 3FUNCTIONAL BLOCK DIAGRAMS

PIN CONFIGURATIONS

FCT240/2240T

FCT244/2244T

2565 drw 08

2565 drw 04

2565 drw 07

DA 0DA 1DA 2DA 3GND

DB 0DB 1DB 2DB 3

V CC DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

DB 0DB 10

O B G N D B O A D B 2

LCC TOP VIEW

OE A 0

123OE B 0OA 1OA 230OA 1OA 2

DA 0OB 0DA 1OB 1DA 2OB 2DA 3OB 3OA 0DB 0OA 1DB 1DB 2DB 3

OA 2OA 3V CC DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

OA 0DB 0OA 1DB 1OA 2

*

O B G N D B 3

O A D B

LCC TOP VIEW

OE B OE A A

2565 drw 05

FCT540/541/2541T

D 0D 2D 3D 4D 5D 6D 7GND

O 0*O 1*O 2*O 3*O 5*O 7*

O 4*O 6*V CC DIP/SOIC/QSOP/CERPACK

TOP VIEW

O 0*O 1*O 2*O 3*O 4*

LCC TOP VIEW

C

D 7

G N O 7*

O 6O 5A A

OE B D 12565 drw 06

2565 drw 09

*O x for 540, Ox for 541/2541T

(1)

A 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed V CC by +0.5V unless otherwise noted.2.Input and V CC terminals only.3.Outputs and I/O terminals only.

2565 tbl 02

1.H = High Voltage Level X = Don’t Care

L = Low Voltage Level Z = High Impedance

2565 lnk 04

NOTE:

1. This parameter is measured at characterization but not tested.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

2565 lnk 07 NOTES:

1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2.Typical values are at Vcc = 5.0V, +25°C ambient.

3.Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4.The test limit for this parameter is ±5μA at T A = –55°C.

1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2.Typical values are at V CC = 5.0V, +25°C ambient.

3.Per TTL driven input (V IN = 3.4V). All other inputs at V CC or GND.

4.This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5.Values for these conditions are examples of the I CC formula. These limits are guaranteed but not tested.

6.I C = I QUIESCENT + I INPUTS + I DYNAMIC

I C = I CC + ?I CC D H N T + I CCD (f CP/2 + f i N i)

I CC = Quiescent Current

?I CC = Power Supply Current for a TTL High Input (V IN = 3.4V)

D H = Duty Cycle for TTL Inputs High

N T = Number of TTL Inputs at D H

I CCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

f CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f i = Input Frequency

N i = Number of Inputs at f i

All currents are in milliamps and all frequencies are in megahertz.

2565 tbl 11

NOTES:

1.See test circuit and waveforms.

2.Minimum limits are guaranteed but not tested on Propagation Delays.

1.See test circuit and waveforms.

2.Minimum limits are guaranteed but not tested on Propagation Delays.

TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

DEFINITIONS:

C L =Load capacitance: includes jig and probe capacitance.

R T =Termination resistance: should be equal to Z OUT of the Pulse

Generator.

2565 drw 12

7.0V

3V 1.5V 0V

3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V DATA INPUT

PRESET CLEAR ETC.

1.5V

1.5V

SAME PHASE INPUT TRANSITION

3V 1.5V 0V 1.5V V OH OUTPUT

OPPOSITE PHASE INPUT TRANSITION

3V 1.5V 0V V OL 3V

1.5V

0V 3.5V 0V

V OL

ENABLE

DISABLE

V OH

PRESET CLEAR

CLOCK ENABLE

ETC.

PROPAGATION DELAY ENABLE AND DISABLE TIMES

2565 drw 14

NOTES:

1.Diagram shown for input Control Enable-LOW and input Control Disable-HIGH

2.Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t F ≤ 2.5ns; t R ≤ 2.5ns

ORDERING INFORMATION

2565 drw 15

IDT XX

Temp. Range

XXXX Device Type

X Package

X

Process

Blank B P D SO L E PY Q 240T 244T 540T 541T 240AT 244AT 540AT 541AT 240CT 244CT 540CT 541CT 240DT 244DT Commercial

MIL-STD-883, Class B

Plastic DIP CERDIP

Small Outline IC

Leadless Chip Carrier CERPACK

Shrink Small Outline Package

Quarter-size Small Outline Package Inverting Octal Buffer/Line Driver

Non-Inverting Octal Buffer/Line Driver Non-Inverting Octal Buffer/Line Driver Inverting Octal Buffer/Line Driver

Non-Inverting Octal Buffer/Line Driver

–55°C to +125°C 0°C to +70°C

FCT

X Family

Blank 2High Drive

Balanced Drive