当前位置：文档库 › Nexys4 开发板用户手册

Nexys4 开发板用户手册

1300 Henl e y Cou rt Pu ll ma n, W A 99163

509.334.6306 www.di gi le nt in c.co m

Nexys4? FPGA Board Reference Manual

Nexys4 rev. B; Revised S ept emb er 6, 2013

Overview

The Nexys4 board is a complete, ready-to-use digital

circuit development platform based on the latest Artix-7? Field Programmable Gate Array (FPGA) from Xilinx. With its large, high-capacity FPGA (Xilinx part number

XC7A100T-1CSG324C), generous external memories, and collection of USB, Ethernet, and other ports, the Nexys4 can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, speaker amplifier and lots of I/O devices allow the Nexys4 to be used for a wide range of designs without needing any other components.

The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more resources than earlier designs. Artix-7 100T features include: ? 15,850 logic slices, each with four 6-input LUTs and 8 flip-flops ? 4,860 Kbits of fast block RAM

? Six clock management tiles, each with phase-locked loop (PLL) ? 240 DSP slices

? Internal clock speeds exceeding 450MHz ?

On-chip analog-to-digital converter (XADC)

The Nexys4 also offers an improved collection of ports and peripherals, including: ? 16 user switches ? 16 user LEDs

? Two 4-digit 7-segment displays ? USB-UART Bridge ? Two tri-color LEDs ? Micro SD card connector ? 12-bit VGA output ? PWM audio output ? PDM microphone ? 3-axis accelerometer ? Temperature sensor ? 10/100 Ethernet PHY ? 16Mbyte CellularRAM ? Serial Flash

? Four Pmod ports

Pmod for XADC signals

Digilent Adept USB port for programming and data

USB HID Host for mice,

keyboards and memory sticks

The Nexys4 is compatible with Xilinx’s new high -performance Vivado ? Design Suite as well as the ISE toolset, which includes ChipScope and EDK. Xilinx offers free “Webpack” versions of these toolsets, so designs can be implemented for no additional cost.

A growing collection of board support IP, reference designs, and add-on boards are available on the Digilent website. See the Nexys4 page at https://www.wendangku.net/doc/f75171453.html, for more information.

1 Power Supplies

The Nexys4 board can receive power from the Digilent USB-JTAG port (J6) or from an external power supply. Jumper JP3 (near the power jack) determines which source is used.

All Nexys4 power supplies can be turned on and off by a single logic-level power switch (SW16). A power-good LED (LD22), driven by the “power good” output of the ADP2118 supply, indicates that the supplies are turned on and operating normally. An overview of the Nexys4 power circuit is shown in Figure 2.

VU5V0

3.3V

1.8V

1.0V

Figure 2. Nexys4 Power Circuit

The USB port can deliver enough power for the vast majority of designs. A few demanding applications, including any that drive multiple peripheral boards, might require more power than the USB port can provide. Also some applications may need to run without being connected to a PC’s USB port. In these instances an external power supply or battery pack can be used.

An external power supply can be used by plugging into to the power jack (JP3) and setting jumper J13 to “wall”. The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 4.5VDC to 5.5VDC and at least 1A of current (i.e., at least 5W of power). Many suitable supplies can be purchased through Digikey or other catalog vendors.

An external battery pack can be used by connecting the battery’s positive terminal to the center pin of JP3 and the negative terminal to the pin labeled J12 directly below JP3. Since the main regulator on the Nexys4 cannot accommodate input voltages over 5.5VDC, an external battery pack must be limited to 5.5VDC. The minimum voltage of the battery pack depends on the application - if the USB Host function (J5) is used, at least 4.6V need to be provided. In other cases the minimum voltage is 3.6V.

Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, and 1.0V supplies from the main power input Table 2 provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs).

2 FPGA Configuration

After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of four ways:

1. A PC can use the Digilent USB-JTAG circuitry (portJ6, labeled “PROG”) to program the FPGA any time the

power is on

2. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.

3. A programming file can be transferred to the FPGA from a micro SD card.

4. A programming file can be transferred from a USB memory stick attached to the USB HID port. Figure 3 Shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) and a media selection jumper (JP2) select between the programming modes.

Micro-AB USB

Connector (J6)

Type A USB Host Connector (J5)

6-pin JTAG Header (J10)

Micro SD Connector (J1)(JP2)

The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx can create bitstreams from VHDL, Verilog, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze? embedded processor -based designs).

Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic functions and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset button attached to the PROG input, or by writing a new configuration file using the JTAG port.

Table 2. Nexys4 Power Supplies

Figure 3. Nexys4 Configuration Options

An Artix-7 100T bitstream is typically 30,606,304 bits and can take a long time to transfer. The time it takes to program the Nexys4 can be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitsream itself during configuration. Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools (ISE or Vivado) to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.

After being successfully programmed, the FPGA will cause the "DONE" LED to illuminate. Pressing the “PROG” button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately attempt to reprogram itself from whatever method has been selected by the programming mode jumpers.

The following sections provide greater detail about programming the Nexys4 using the different methods available.

2.1 JTAG Programming

The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J6) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to port J10. You can perform JTAG programming any time after the Nexys4 has been powered on, regardless of what the mode jumper (JP1) is set to. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG setting (seen in Figure 3Error! Reference source not found.) is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG programming occurs.

Programming the Nexys4 with an uncompressed bitstream using the on-board USB_JTAG circuitry usually takes around five seconds.

JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the labtools version of Vivado.

The demonstration project available at https://www.wendangku.net/doc/f75171453.html, gives an in depth tutorials on how to program your board.

2.2 Quad-SPI Programming

When programming a nonvolatile flash device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). After the flash device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper setting (see Figure 3). Programming files stored in the flash device will remain until they are overwritten, regardless of power-cycle events.

Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory technology. Once written however, FPGA configuration can be very fast, less than a second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilnx tools that can affect configuration speed.

Quad-SPI programming can be done using the iMPACT tool included with ISE or the labtools version of Vivado.

2.3 USB Host and Micro SD Programming

You can program the FPGA from a pen drive attached to the USB-HID port (J5) or a microSD card inserted into J1 by doing the following:

1.Format the storage device (Pen drive or microSD card) with a FAT32 file system.

2.Place a single .bit configuration file in the root directory of the storage device.

3.Attach the storage device to the Nexys

4.Set the JP1 Programming Mode jumper on the Nexys4 to “USB/SD”.

5.Select the desired storage device using JP2.

6.Push the PROG button or power-cycle the Nexys4.

The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not built for the proper Artix-7 device will be rejected by the FPGA.

The Auxiliary Function Status or “BUSY” LED gives vis ual feedback on the state of the configuration process when the FPGA is not yet programmed:

?When steadily lit the auxiliary microcontroller is either booting up or currently reading the configuration medium (microSD or pen drive) and downloading a bitstream to the FPGA.

? A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.

?In case of an error during configuration the LED will blink rapidly.

When the FPGA is has been successfully configured, the behavior of the LED is application-specific. For example, if

a USB keyboard is plugged in, a rapid blink will signal the receipt of an HID input report from the keyboard.

3 Memory

The Nexys4 board contains two external memories: a 128Mbit Cellular RAM (pseudo-static DRAM) and a 128Mbit non-volatile serial Flash device. The Cellular RAM has an SRAM interface, and the serial Flash is on a dedicated quad-mode (x4) SPI bus. The connections and pin assignments between the FPGA and external memories are shown in Figure 4 and Table 3.

The 16Mbyte Cellular RAM (Micron part number M45W8MW16) has a 16-bit bus that supports 8 or 16 bit data access. It can operate as a typical asynchronous SRAM with read and write cycle times of 70ns, or as a synchronous memory with a 104MHz bus. When operated as an asynchronous SRAM, the Cellular RAM automatically refreshes its internal DRAM arrays, allowing for a simplified memory controller (similar to any SRAM controller). When operated in synchronous mode, continuous transfers of up to 104MHz are possible.

FPGA configuration files can be written to the Quad SPI Flash (Spansion part number S25FL128S), and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 100T configuration file requires just under four Mbytes of memory, leaving about 77% of the flash device available for user data.

NOTE: Refer to the manufacturer’s data sheets and the reference designs posted on Digilent’s website for more information about the memory devices.

Figure 4. Nexys4 External Memories

Table 3. CellRAM Address and Data Bus Pin Assignments

4 Ethernet PHY

The Nexys4 board includes an SMSC 10/100 Ethernet PHY (SMSC part number LAN8720A) paired with an RJ-45 Ethernet jack with integrated magnetics. The SMSC PHY uses the RMII interface and supports 10/100 Mb/s. Figure 5 illustrates the pin connections between the Artix-7 and the Ethernet PHY. At power-on reset, the PHY is set to the following defaults:

?RMII mode interface

?Auto-negotiation enabled, advertising all 10/100 mode capable

?PHY address=00001

Two on-board LEDs (LD23 = LED2, LD24 = LED1) connected to the PHY provide link status and data activity feedback. See the PHY datasheet for details.

EDK-based designs can access the PHY using either the axi_ethernetlite (AXI EthernetLite) IP core or the

axi_ethernet (Tri Mode Ethernet MAC) IP core. A mii_to_rmii core (Ethernet PHY MII to Reduced MII) needs to be inserted to convert the MAC interface from MII to RMII. Also a 50 MHz clock needs to be generated for the

mii_to_rmii core and the CLKIN pin of the external PHY. To account for skew introduced by the mii_to_rmii core, generate each clock individually, with the external PHY clock having a 45 degree phase shift relative to the

mii_to_rmii Ref_Clk. An EDK demonstration project that properly uses the Ethernet PHY can be found on the Nexys4 product page at https://www.wendangku.net/doc/f75171453.html,.

ISE designs can use the IP Core Generator wizard to create an Ethernet MAC controller IP core.

NOTE: Refer to the LAN8720A data sheet on the https://www.wendangku.net/doc/f75171453.html, website for further information.

Artix-7SMSC LAN8720A

Figure 5. Pin connections between the Artix-7 and the Ethernet PHY

5 Oscillators/Clocks

The Nexys4 board includes a single 100MHz crystal oscillator connected to pin E3 (E3 is a MRCC input on bank 35). The input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 100MHz input clock. For a full description of these rules and of the capabilities of the Artix-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx.

Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy to use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Project Navigator or Core Generator tools.

6 USB-UART Bridge (Serial Port)

The Nexys4 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J6) that lets you use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from https://www.wendangku.net/doc/f75171453.html, under the "Virtual Com Port" or VCP heading, convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD) and optional hardware flow control (RTS/CTS). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the C4 and D4 FPGA pins.

Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (LD20) and the receive LED (LD19). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.

The FT2232HQ is also used as the controller for the Digilent USB-JTAG circuitry, but the USB-UART and USB-JTAG functions behave entirely independent of one another. Programmers interested in using the UART functionality of the FT2232 within their design do not need to worry about the JTAG circuitry interfering with the UART data transfers, and vice-versa. The combination of these two features into a single device allows the Nexys4 to be programmed, communicated with via UART, and powered from a computer attached with a single Micro USB cable.

The connections between the FT2232HQ and the Artix-7 are shown in Figure 6.

Figure 6. Nexys4 FT2232HQ connections

7 USB HID Host

The Auxiliary Function microcontroller (Microchip PIC24FJ128) provides the Nexys4 with USB HID host capability. After power-up, the microcontroller is in configuration mode, either downloading a bitstream to the FPGA, or waiting to be programmed from other sources. Once the FPGA is programmed, the microcontroller switches to application mode, which is USB HID Host in this case. Firmware in the microcontroller can drive a mouse or a

keyboard attached to the type A USB connector at J5 labeled "USB Host.” Hub support is not currently available, so only a single mouse or a single keyboard can be used. The PIC24 drives several signals into the FPGA – two are used to implement a standard PS/2 interface for communication with a mouse or keyboard, and the others are connected to the FPGA’s two -wire serial programming port, so the FPGA can be programmed from a file stored on a USB pen drive or microSD card.

7.1 HID Controller

The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing PS/2 IP cores. Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to communicate with a host. On the Nexys4, the microcontroller emulates a PS/2 device, while the FPGA plays the role of the host. Both the mouse and the keyboard use 11-bit words that include a start bit, data byte (LSB first), odd parity, and stop bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown in Figure 8.

CLOCK

DATA

The clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic ‘1.’ This requires that when the PS/2 signals are used in a design, internal pull-ups must be enabled in the FPGA on the data and clock pins. The clock signal is normally driven by the device, but may be held low by the host

Figure 7. Nexys4 PIC24 Connections

Figure 8. PS/2 Device-to-Host Timing Diagram

in special cases. The timings define signal requirements for mouse-to-host communications and bi-directional

keyboard communications. A PS/2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface.

When a keyboard or mouse is connected to the Nexys4, a “self -test passed” command (0xAA) is sent to the host.

After this, commands may be issued to the device. Since both the keyboard and the mouse use the same PS/2 port, one can tell the type of device connected using the device ID. This ID can be read by issuing a Read ID

command (0xF2). Also, a mouse sends its ID (0x00) right after the “self

-test passed” command, which distinguishes it from a keyboard.

7.2 Keyboard

The keyboard uses open-collector drivers so the keyboard, or an attached host device, can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use input-only ports).

PS/2-style keyboards use scan codes to communicate key press data. Each key is assigned a code that is sent whenever the key is pressed. If the key is held down, the scan code will be sent repeatedly about once every

100ms. When a key is released, an F0 key-up code is sent, followed by the scan code of the released key. If a key can be shifted to produce a new character (like a capital letter), then a shift character is sent in addition to the scan code, and the host must determine which ASCII character to use. Some keys, called extended keys, send an E0

ahead of the scan code (and they may send more than one scan code). When an extended key is released, an E0 F0

key-up code is sent, followed by the scan code. Scan codes for most keys are shown in Figure 9.

A host device can also send data to the keyboard. Table 4 shows a list of some common commands a host might send.

The keyboard can send data to the host only when both the data and clock lines are high (or idle). Because the host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To facil itate this, the clock line is used as a “clear to send” signal. If the host drives the clock line low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that

contain a ‘0’ start bit, follow ed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at 20 to 30KHz) when the data is sent, and data is valid on the falling edge of the clock.

Figure 9. Keyboard scan codes

Table 4. Keyboard commands

7.3 Mouse

Once entered in stream mode and data reporting enabled the mouse outputs a clock and data signal when it is moved: otherwise, these signals remain at logic ‘1.’ Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device, as shown in Figure 10. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Thus, each data transmission contains 33 bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 11, 21, and 33 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in the figure above. Data is valid at the falling edge of the clock, and the clock period is 20 to 30KHz.

The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits –a ‘1’ indicates a negative number). The magnitude of the X and Y numbers represent the rate of mouse movement – the larger the number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators –a ‘1’ means overflow has occurred). If the mouse moves continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and Right button presses (a ‘1’ indicates the button is being pressed).

Idle state Idle state

Figure 10. Mouse Data Format

The microcontroller also supports Microsoft Intellimouse-type extensions for reporting back a third axis representing the mouse wheel, as shown in Table 5.

Table 5. Microsoft Intellimouse-type extensions, commands and actions

8 VGA Port

The Nexys4 board uses 14 FPGA signals to create a VGA port with 4 bits-per-color and the two standard sync signals (HS – Horizontal Sync, and VS – Vertical Sync). The color signals use resistor-divider circuits that work in conjunction with the 75-ohm termination resistance of the VGA display to create 16 signal levels each on the red, green, and blue VGA signals. This circuit, shown in Figure 11, produces video color signals that proceed in equal increments between 0V (fully off) and 0.7V (fully on). Using this circuit, 4096 different colors can be displayed, one for each unique 12-bit pattern. A video controller circuit must be created in the FPGA to drive the sync and color signals with the correct timing in order to produce a working display system.

Figure 11. Nexys4 VGA Interface

8.1 VGA System Timing

VGA signal timings are specified, published, copyrighted and sold by the VESA organization (https://www.wendangku.net/doc/f75171453.html,). The following VGA system timing information is provided as an example of how a VGA monitor might be driven in 640 by 480 mode.

NOTE: For more precise information, or for information on other VGA frequencies, refer to documentation available at the VESA website.

CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays (so the “signals” discussion below pertains to both CRTs and LCDs). Color CRT displays use three electron beams (one for red, one for blue, and one for green) to energize the phosphor that coats the inner side of the display end of a cathode ray tube (see Figure 12).

Electron bea ms emanate from “electron guns” which are finely-pointed heated cathodes placed in close proximity to a positively charged annular plate called a “grid.” The electrostatic force imposed by the grid pulls rays of energized electrons from the cathodes, and those rays are fed by the current that flows into the cathodes. These particle rays are initially accelerated towards the grid, but they soon fall under the influence of the much larger electrostatic force that results from the entire phosphor-coated display surface of the CRT being charged to 20kV (or more). The rays are focused to a fine beam as they pass through the center of the grids, and then they accelerate to impact on the phosphor-coated display surface. The phosphor surface glows brightly at the impact point, and it continues to glow for several hundred microseconds after the beam is removed. The larger the current fed into the cathode, the brighter the phosphor will glow.

Between the grid and the display surface, the beam passes through the neck of the CRT where two coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of charged particles (electrons), they can be deflected by these magnetic fields. Current waveforms are passed through the coils to produce magnetic fields that interact with the cathode rays and cause them to transverse the display su rface in a “raster” pattern, horizontally from left to right and vertically from top to bottom, as shown in Figure 14. As the cathode ray moves over the surface of the display, the current sent to the electron guns can be increased or decreased to change the brightness of the display at the cathode ray impact point.

Information is only displayed when the beam is moving in the “forward” direction (left to right and top to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at which the beam can be traced across the display, and the frequency at which the electron beam can be modulated determine the display resolution.

Modern VGA displays can accommodate different resolutions, and a VGA controller circuit dictates the resolution by producing timing signals to control the raster patterns. The controller must produce synchronizing pulses at 3.3V (or 5V) to set the frequency at which current flows through the deflection coils, and it must ensure that video data is applied to the electron guns at the correct time. Raster vi deo displays define a number of “rows” that corresponds to the number of horizontal passes the cathode makes over the display area, and a number of “columns” that corresponds to an area on each row that is assigned to one “picture element” or pixel. Typica l displays use from 240 to 1200 rows and from 320 to 1600 columns. The overall size of a display and the number of rows and columns determines the size of each pixel.

coil HS

Video data typically comes from a video refresh memory, with one or more bytes assigned to each pixel location (the Nexys4 uses 12 bits per pixel). The controller must index into video memory as the beams move across the display, and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel.

A VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video data

based on the pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron b eam intensity, with practical refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be displayed at a given refresh

frequency defines the horizontal “retrace” frequency. For a 640-pixel by 480-row display using a 25MHz pixel clock and 60 +/-1Hz refresh, the signal timings shown in Figure 14 can be derived. Timings for sync pulse width and front and back porch intervals (porch intervals are the pre- and post-sync pulse times during which information cannot be displayed) are based on observations taken from actual VGA displays.

Figure 13. VGA Horizontal Synchronization

A VGA controller circuit, such as the one diagramed in Figure 15, decodes the output of a horizontal-sync counter driven by the pixel clock to generate HS signal timings. You can use this counter to locate any pixel location on a given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to generate VS signal timings, and you can use this counter to locate any given row. These two continually running counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified, so you can arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation.

9 Basic I/O

The Nexys4 board includes two tri-color LEDs, sixteen slide switches, six push buttons, sixteen individual LEDs, and an eight-digit seven-segment display, as shown in Figure 16. The pushbuttons and slide switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). The five pushbuttons arranged in a plus-sign configuration are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. The red pushbutton labeled “CPU RESET,” on the other hand, generates a high output when at rest and a low output when pressed. The CPU RESET button is intended to

Figure 14. Signal timings for a 640-pixel by 480 row display using a 25MHz pixel clock and 60Hz vertical refresh

Figure 15. VGA display controller block diagram

be used in EDK designs to reset the processor, but you can also use it as a general purpose pushbutton. Slide switches generate constant high or low inputs depending on their position.

Figure 16. General Purpose I/O devices on the Nexys4

The sixteen individual high-efficiency LEDs are anode-connected to the FPGA via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs that are not user-accessible indicate power-on, FPGA programming status, and USB and Ethernet port status.

9.1 Seven-Segment Display

The Nexys4 board contains two four-digit common anode seven-segment LED displays, configured to behave like a single eight-digit display. Each of the eight digits is composed of seve n segments arranged in a “figure 8” pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, so any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark, as shown in Figure 17.

Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful.

The anodes of the seven LEDs forming each digit are tied together into one “common anode” circuit node, but the LED cathodes remain separate, as shown in Figure 18. The common anode signals are available as eight “digit enable” input signals to the 8-digit display. The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG (so, for example, the eight “D” cathodes from the eight digits are grouped together into a single circuit node called “CD”). Th ese seven cathode signals are available as inputs to the 8-digit display. This signal connection scheme creates a multiplexed display, where the cathode signals are

common to all digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted.

To illuminate a segment, the anode should be driven high, while the cathode is driven low. However, since the Nexys4 uses transistors to drive enough current into the common anode point, so the anode enables are inverted. Therefore, both the AN0..7 and the CA..G/DP signals are driven low, when active.

Individual cathodes

Figure 17. An un-illuminated seven-segment display, and nine illumination patterns corresponding to decimal digits

Figure 18. Common anode circuit node

A scanning display controller circuit can be used to show an eight-digit number on this display. This circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession, at an update rate that is faster than the human eye can detect. Each digit is illuminated just one-eighth of the time, but because the eye cannot perceive the darkening of a digit before it is illuminated again, the digit appears

continuously illuminated. If the update or “refresh” rate is slowed to around 45 hertz,, a flicker can be noticed in the display.

For each of the four digits to appear bright and continuously illuminated, all eight digits should be driven once every 1 to 16ms, for a refresh frequency of about 1KHz to 60Hz. For example, in a 62.5Hz refresh scheme, the entire display would be refreshed once every 16ms, and each digit would be illuminated for 1/8 of the refresh cycle, or 2ms. The controller must drive low the cathodes with the correct pattern when the corresponding anode signal is driven high. To illustrate the process, if AN0 is asserted while CB and CC are asserted, then a “1” will be displayed in digit position 1. Then, if AN1 is asserted while CA, CB and CC are asserted, a “7” will be displayed in digit position 2. If AN0, CB, and CC are driven for 4ms, and then AN1, CA, CB, and CC are driven for 4ms in an endless success ion, the display will show “71” in the first two digits. An example timing diagram for a four -digit controller is shown in Figure19.

AN0AN1AN2AN3Cathodes

9.2 Tri-Color LEDs

The Nexys4 board contains two tri-color LEDs. Each tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the signal corresponding to one of these colors high will illuminate the internal LED. The input signals are driven by the FPGA through a transistor, which inverts the signals. Therefore, to light up the tri-color LED, the corresponding signals need to be driven high. The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high, and green is driven low, the tri-color LED will emit a purple color.

Note: Digilent strongly recommends that the use of Pulse-Width Modulation (PWM) when driving the tri-color LEDs (for information on PWM, see section 15.1). Driving any of the inputs to a steady logic ‘1’ will result in the LED being illuminated at an uncomfortably bright level. You can avoid this by ensuring that none of the tri-color signals are driven with more than a 50% duty cycle. Using PWM also greatly expands the potential color palette of the tri-color led. Individually adjusting the duty cycle of each color between 50% and 0% causes the different colors to be illuminated at different intensities, allowing virtually any color to be displayed.

Figure19. Four digit scanning display controller timing diagram

CSR8670开发板使用说明书

一、开发板资源介绍开发板是针对蓝牙免提，蓝牙音响应用设计的一款多媒体蓝牙开发套件。开发板采用英国CSR 公司CSR8670 蓝牙芯片，可以用来开发单声道蓝牙耳机，立体声蓝牙耳机，蓝牙车载免提，蓝牙音频适配器，蓝牙虚拟串口(SPP), 蓝牙人机交互接口（HID），蓝牙文件传输（FTP）等。开发板带有USB，UART，I2C，PCM，音频输入、输出等接口，并引出PIO 和AIO 接口，方便用户扩展，进行二次开发。I开发板支持程序在线调试以及参数修改。 1、硬件资源： ◆标配CSR8670 蓝牙芯片，内置kalimba DSP ，支持蓝牙协议V4.0+EDR ◆集成16Mb FLASH ◆7个按键（1个复位键，1个开机键，5个用户按键） ◆16个PIO 接口（其中PIO6、PIO7作为I2C） ◆2个AIO 接口 ◆3个LED 指示灯

◆ 1个USB 接口 ◆ 音频输出接口 ◆ 音频输入接口 ◆ 板载麦克风 ◆ RS232 接口 ◆ SPI 调试接口 ◆ IIC 接口（PIO 复用） ◆ 64Kbit E2PROM 【注意】：板载的部分资源会因为芯片所采用的芯片的不同而未被使用到，具体请参考原理图。

二、硬件连接和使用 1、请参照上图，将下载线通过10PIN的排线和开发板连接，将MINI-USB线连接下载线并接到电脑，此时板子左上方的红色LED灯会亮，说明开发板已经正常上电。【注意】： 1. 本开发板将VREN 开机信号单独连接到一个按键作为开机用，所以在使用bluelab或pstool连接开发板时，请务必按下改开机键不放，否则将会导致软件无法读取芯片的现象,bluelab 会提示"Unable to query BlueCore over SPI" 错误。 2. 使用bluelab下载调试程序时，请务先设置【Debug】菜单下的【Tansport】是否设置为USB，否则bluelab 将会提示"Unable to query BlueCore over SPI" 错误

51开发板说明书

开发板开发板简介简介简介硬件：供电方式采用USB 取电和外部电源(5V)供电。带有多种品牌（Atmel,Winbond,SST,STC ）单片机的ISP 电路，均通过下载接口或USB 线和PC 相连，简单方便稳定，速度快。有常用的LCD 接口,数码管显示电路，等等。

一、STC单片机的程序烧写与运行 1.1 打开STC-ISP V483软件的exe 文件，如下图所示：步骤1：选择要下载的单片机型号，如下图所示：步骤2：打开要下载的程序文件，注意这里下载的需要是扩展名为.hex或.bin的文件，这里的图片是默认的测试文件

再双击test-hex文件夹得到以下图片：

选择twoball-2k.bin，点击打开。步骤3：选择端口首先把实验板通过USB延长线连接到电脑上，然后右击“我的电脑”，选择“管理”，单击设备管理器，点击端口前的加号将其展开，当发现这个时，说明驱动的安装和实验板的下载电路应该是没什么问题的，这里的可以看出端口是COM14。其次是选择好端口，如下图所示：步骤4：下载程序到单片机（注意的是STC的单片机需要重新给系统上电才能下载到单片机）点击下图所示的Download/下载按钮当出现下图所示的提示时，如果实验板是在通电的情况下，则按一下实验板的开关稍等两秒左右，再按一下开关重新给实验板上电，稍等片刻就下载成功。如果实验板是在不通电的情况下，则按一下实验板的开关重新给实验板上电，稍等片刻就下载成功下载成功的提示如下图：下载过程中如果端口选择对的情况下，出现如下图所示：原因在于连电脑USB插口松动。解决办法：1、重新把延长线从实验板上拔掉，然后再插上。

金龙STM32F207开发板用户手册

1.概述金龙STM32开发板用户手册芯片描述 -ARM32-bit Cortex-M3CPU -120MHz maximum frequency,150DMIPS/1.25DMIPS/MHz -Memory protection unit Memories -Up to1Mbyte of Flash memory -Up to128+4Kbytes of SRAM -Flexible static memory controller (supports Compact Flash,SRAM,PSRAM,NOR,NAND memories) -LCD parallel interface,8080/6800modes Clock,reset and supply management -1.8to3.6V application supply and I/Os -POR,PDR,PVD and BOR -4to25MHz crystal oscillator -Internal16MHz factory-trimmed RC -32kHz oscillator for RTC with calibration -Internal32kHz RC with calibration Low power -Sleep,Stop and Standby modes -VBAT supply for RTC, C32bit backup registers 20 optional4KB backup SRAM C12-bit,0.5us A/D converters 3 -up to24channels -up to6MSPS in triple interleaved mode C12-bit D/A converters 2 General-purpose DMA -16-stream DMA controller centralized FIFOs and burst support Up to17timers -Up to twelve16-bit and two32-bit timers Debug mode -Serial wire debug(SWD)&JTAG interfaces -Cortex-M3Embedded Trace Macrocell Up to140fast I/O ports with interrupt capability -51/82/114/140I/Os,all5V-tolerant Up to15communication interfaces C I2C interfaces(SMBus/PMBus) -Up to3 -Up to6USARTs(7.5Mbit/s,ISO7816interface,LIN,IrDA,modem control)

KR-51开发板使用说明

KR-51/AVR开发板使用说明声明：本指导教程和配套程序仅在开发和学习中参考，不得用于商业用途，如需转载或引用，请保留版权声明和出处。请不要在带电时拔插芯片以及相关器件。自行扩展搭接导致不良故障，本公司不负任何责任。产品不定时升级，所有更改不另行通知，本公司有最终解释权。一、开发板硬件资源介绍 1 .开发板支持USB 程序下载（宏晶科技STC系列单片机） 2. 开发板支持AT89S51 ，AT89S52 单片机下载（需要配合本店另外下载器下载） 3. 开发板支持ATmega16，ATmega32 AVR 单片机下载（需要配合本店另外转接板和下载器使用） 4. 开发板供电模式为：电脑USB 供电（USB 接口）和外部5V 电源供电（DC5V接口） 5. 开发板复位方式：上电复位和51按键复位 6. 外扩电源：通过排针外扩5路5V 电源，3路3.3V电源方便连接外部实验使用 7. 所有IO 引脚全部外扩，方便连接外部实验使用 8. 开发板集成防反接电路，防止接反，保护开发板二、开发板功能模块介绍（1 ）8 位高亮度贴片led 跑马灯；（2） 4 位共阳数码管显示；（3）LCD1602 和LCD12864液晶屏接口；（4） 1 路无源蜂鸣器；（5） 1 路ds18b20 温度测量电路（与DHT11 温湿度接口共用）；（6） 1 路红外接口电路（7） 4 路独立按键（8） 1 路CH340 USB转串口通讯电路（全面支持XP/WIN7/WIN8系统）；（9）1路蓝牙模块接口（可做蓝牙测试板，USB转蓝牙）；（10）1路2.4G模块接口；（11）1路WiFi模块接口（可做WiFi测试板，USB转WiFi）三开发板跳线选择本开发板接线简单，适合初学者使用，开发板各模块的跳线使用注意事项：烧写程序时，拔掉蓝牙模块，WiFi模块，J10处用跳线帽短接1,3和2,4。蓝牙模块和WiFi模共用串口，不能同时使用。使用1602、12864液晶接口时请拔下数码管J4 跳线帽。以下是几个主要跳线的使用说明；

路虎开发板用户手册

路虎NXP LPC1768开发板用户手册

1、概述路虎开发板采用 NXP公司 LPC1768 ARM是一款基于第二代 ARM Cortex-M3内核的微控制器，是为嵌入式系统应用而设计的高性能、低功耗的 32位微处理器，适用于仪器仪表、工业通讯、电机控制、灯光控制、报警系统等领域。路虎开发板板载 USB仿真器，支持 USB2.0 Device，具有双 CAN接口、RS-485接口等功能。路虎开发板配套丰富的例程和详尽的资料，方便用户快速进行项目开发。功能特点：强大的 MCU内核：Cortex-M3 ●处理速率高达 100MHz，并包含一个支持 8个区的存储器保护单元（MPU） ●内置嵌套向量中断控制器（NVIC） ● 512KB片上 Flash程序存储器，支持在系统编程（ISP）和在应用编程（IAP） ● 64KB SRAM可供高性能 CPU通过指令总线、系统总线、数据总线访问 ● AHB多层矩阵上具有 8通道的通用 DMA控制器（GPDMA） ●支持SSP、UART、AD/DA、定时器、GPIO等，并可用于存储器到存储器的传输 ●标准 JTAG测试/调试接口以及串行线调试和串行线跟踪端口选项 ●仿真跟踪模块支持实时跟踪 ● 4个低功率模式：睡眠、深度睡眠、掉电、深度掉电

●单个 3.3V电源（2.4V – 3.6V） ●工作温度：-40 °C - 85°C ●不可屏蔽中断（NMI）输入 ●片内集成上电复位电路 ●内置系统节拍定时器（SysTick），方便操作系统移植。丰富的板载资源： 1、2路 RS232串行接口（使用直通串口线、其中一路串口支持 ISP下载程序） 2、2路 CAN总线通信接口（CAN收发器：SN65VHD230） 3、RS485通信接口（485收发器：SP3485） 4、RJ45-10/100M Ethernet网络接口（以太网 PHY：DP83848） 5、DA输出接口(可做 USB声卡实验、板载扬声器和扬声器输出驱动) 6、AD输入接口（可调电位器输入） 7、彩色液晶显示接口(可接 2.8寸或 3.2寸 TFT 320X240彩屏) 8、USB2.0接口,USB host及 USB Device接口。 9、SD/MMC卡(SPI)接口(提供带 FAT12、FAT16、FAT32文件系统)

RK3188开发板使用手册v1.0

RK3188开发板使用手册v1.0 一.安装RockUsb驱动 (2) 二.查看串口输出信息 (5) 三.烧写/下载固件 (8) 四.Kernel开发 (11) 五.Android开发 (12) 六.制作固件升级包update.img (13) 七.Recovery系统 (14) 八.Android系统USB操作 (17)

一.安装RockUsb驱动 Rockusb驱动放在RK3188\tools\RockusbDriver文件夹中当你第一次使用RK3188SDK开发板时，接好USB线，按住“VOL+(RECOVERY)”按键上电，会要求安装驱动，按下面的图示步骤进行安装：图1 选择“否，暂时不(T)”，点击“下一步”进入图2所示界面

图2 选择“从列表或指定位置安装（高级）”，点击下一步，进入图3界面图3 选择你的驱动所存放的目录，点击“下一步”开始安装驱动，如图4所示

图4 完成以后可以在设备管理器看到设备已经安装成功图5

二.查看串口输出信息 RK3188SDK开发板没有使用普通的串口，而是使用USB口来输出串口信息，你可以用一根特殊的USB调试线将开发板上的USB口连接到你的电脑中来查看串口信息。 1、在连接USB口之前，请先安装PL-2303USB转串口驱动 2、驱动安装完成后，再使用USB线将开发板上名为“UART0”的USB口连接到PC 中，然后你应该可以在设备管理器中看到一个新设备，如下所示： 3、使用串口工具查看开发板的输出信息。在这边我以Windows自带的超级终端为例说明串口的配置： a、点击开始->所有程序->附件->通讯->超级终端点击确定 b、选择正确的COM口：

51单片机开发板使用手册

STU_MAIN单片机开发板使用手册第一章STU_MAIN 单片机开发板简介 (2) 1.1 单片机开发板概述 (2) 1.2 单片机开发板载资源介绍 (2) 1.3 STU_MAIN 单片机开发板接口说明 (4) 1.4 如何开始学习单片机 (5) 第二章软件使用方法 ......................... . (6) 2.1 KEIL 软件的使用方法 (6) 2.2 STC-ISP 软件的安装与使用 (13) 2.3 使用USB 口下载程序时设置步骤 (18) 第三章STU_MAIN 开发板例程详细介绍 (21) 3.1 准备工作 (21) 3.2 安装STC-ISP下载程序 (21) 3.3 闪烁灯 (22) 3.4 流水灯 (23) 3.5 单键识别 (25) 3.6 利用定时器和蜂鸣器唱歌 (28) 3.7 DS18B20 温度测量显示实验 (31) 3.8 LCD1602 字符液晶显示 (36) 3.9 串口通讯实验 (39) 3.10 基于DS1302的多功能数字钟实验 (41) 3.11 EEPROM X5045 实验 (47)

第一章STU_MAIN 单片机开发板简介 1.1 单片机开发板概述 STU_MAIN 单片机开发板是经过精心设计开发出的多功能MCS-51 单片机开发平台。该开发板集常用的单片机外围资源、串口调试下载接口于一身，可以让您在最短的时间内，全面的掌握单片机编程技术。该开发板特别适合单片机初学者、电子及通信等专业的课程设计以及电子爱好者自学使用。 STU_MAIN 单片机开发板可作为单片机课程的配套设备，课程从最基本的预备知识开始讲起，非常详细的讲解KEIL 编译器的使用，包括软件仿真、测定时间、单步运行、全速运行、设置断点、调试、硬件仿真调试、变量观察等，整个过程全部用单片机的C 语言讲解，从C 语言的第一个主函数MAIN 讲起，一步步一条条讲解每一个语法、每条指令的意思，即使对单片机一巧不通，对C 语言一无所知，通过本课程的学习也可以让你轻松掌握MCS-51 单片机的C 语言编程。全新的讲课风格，跳过复杂的单片机内部结构知识，首先从单片机的应用讲起，一步步深入到内部结构，让学生彻底掌握其实际应用方法，把MCS-51单片机的所有应用、每个部分都讲解的非常清晰明了，授课教师在教室前面用电脑一条一条写程序，旁边用STU_MAIN 单片机开发板逐个实验的演示，给学生解释每条指令的意思及原理，通过一学期的学习让学生完全掌握单片机的C 语言编程及单片机外围电路设计的思想。以实践为主、学生现场写程序、直接下载到开发板观察现象。 1.2 单片机开发板载资源介绍一. STU_MAIN单片机开发板(串口直接下载程序) 本开发板以STC 公司生产的STC90C54RD+ 单片机做核心控制芯片,它是一款性价比非常高的单片机，它完全兼容ATMEL 公司的51/52系列单片机，除此之外它自身还有很多特点，如：无法解密、低功耗、高速、高可靠、强抗静电、强抗干扰等。其次STC 公司的单片机内部资源比起ATMEL 公司的单片机来要丰富的多，它内部有1280 字节的SRAM、8-64K 字节的内部程序存储器、2-8K 字节的ISP 引导码、除P0-P3 口外还多P4 口(PLCC封装)、片内自带8路8位AD(AD 系列)、片内自带EEPROM、片内自带看门狗、双数据指针等。目前STC 公司的单片机在国内市场上的占有率与日俱增,有关STC 单片机更详细资料请查阅相关网站。 STU_MAIN单片机开发板可完全作为各种MCS-51单片机的开发板，用汇编语言或C 语言对其进行编程。当用STC 公司的单片机时，直接用后面介绍的串口线将开发板与计算机串口相连，按照STC 单片机下载操作教程便可下载程序，

STM32F429开发板用户手册

STM32F429开发板用户手册介绍 STM32F429(32F429IDISCOVERY)开发板可以帮助你去学习高性能STM32F4系列，并去开发你自己的应用。它包含了一个STM32F429ZIT6和一个嵌入ST-LINK/V2调试接口，2.4吋TFTLCD，64MbitsSDRAM，ST微机电陀螺仪，按键和USB OTG接口。

1约定下表提供了一些约定惯例，目前的文档可能会用到。

2快速入门 STM32F429开发板是一种廉价且易于上手的开发套件，可以让使用者快速评估和开始STM32F4的开发工作。在安装和使用产品以前，请接收评估产品许可协议。 2.1启动跟随以下顺序来设置STM32F429开发板并开始开发应用： 1、确认跳线JP3和CN4被设置为“on”（开发模式） 2、连接STM32F429Discovery开发板CN1到PC，使用USB电缆（type A/mini-B）,开发板上电。 3、屏幕上以下应用可用：时钟日历和游戏视频播放器和图片浏览器（播放浏览USB大容量存储器上的视频和图片）性能显示器（观察CPU负载和图形测试）系统信息 4、演示软件，也像其他软件例程，运行你用来开发STM32F4。 5、从例程开始开发你自己的应用吧。 2.2系统要求 ?Windows PC(XP,Vista,7) ?USB type A to mini-B cable 2.3支持STM32F429开发板的开发工具 ?Altium:TASKING?VX-Toolset ?Atollic:TrueSTUDIO ?IAR:EWARM ?Keil?:MDK-ARM 2.4订购码要订购STM32F429Discovery kit，请使用STM32F429I-DISCO订购码。 3特性 STM32F429Discovery开发板提供一下特性： ?S TM32F429ZIT6具有2MB闪存，256KB的RAM，LQFP144封装。 ?板载ST-LINK/V2，带有选择模式跳线，可以作为独立的ST-LINK/V2使用。 ?板电源：通过USB总线或外部3V或5V电源。 ?L3GD20：ST微机电动作传感器，3轴数字输出陀螺仪 ?TFT LCD，2.4寸，262K色RGB，240*230分辨率 ?SDRAM64Mbits(1Mbit x16-bit x4-bank)，包含自动刷新模式和节能模式 ?六个LED： LD1（红绿）：USB通信 LD2（红）：3.3V电源两个用户LED LD3（绿），LD4红两个USBOTG LED：LD5(绿)VBUS和LD6OC（过流） ?两个按键（user and reset）

百问网精智JZ2440开发板使用手册 S3C2440

百问网·精智JZ2440使用手册提示：除了QT外，可以不看本手册，参考《嵌入式Linux应用开发完全手册》及视频即可

第1章嵌入式Linux开发环境构建 (4) 1.1 安装Ubuntu 9.10 (4) 1.1.1 安装VMware (4) 1.1.2 安装Ubuntu 9.10 (13) 1.2 安装Ubuntu下的开发工具 (20) 1.3 安装Windows下的开发工具 (22) 第2章精智JZ2440开发板烧写程序方法 (23) 2.1 使用JTAG工具烧写开发板 (23) 2.1.1 Windows下并口JTAG驱动安装 (23) 2.1.2 Windows下OpenJTAG驱动安装 (29) 2.1.3 Ubuntu下驱动程序的安装 (29) 2.1.4 JTAG烧写软件oflash的用法 (29) 2.2 通过u-boot烧写整个系统 (29) 2.2.1 在Windows下使用dnw和u-boot烧写系统 (30) 2.2.2 在Linux下使用dnw和u-boot烧写系统 (31) 第3章板上Linux系统搭建 (33) 3.1 修改、编译、使用u-boot (33) 3.1.1 使用补丁修改、编译u-boot (33) 3.1.2 u-boot使用方法 (33) 3.2 修改、编译、使用Linux内核 (36) 3.2.1 使用补丁修改、编译内核 (36) 3.2.2 使用uImage (36) 3.3 修改、编译QT (36) 3.3.1 编译依赖的软件 (36) 3.3.2 使用补丁修改、编译QT (39) 3.4 构造根文件系统 (39) 3.4.1 基于最小根文件系统制作QT文件系统 (39) 3.4.2 制作YAFFS2、JFFS2文件系统映象文件 (42)

DL-51单片机开发板用户使用手册

STC89C52RC 动力DL-51Board○R User's Manual Preliminary

开发指南 Copyright?2010-2011Milk-Power Limited.All rights reserved 版本信息本手册进行了以下更改。芯达STM32用户手册修订记录日期修订版本CR ID修改章节修改描述作者2011-10-12 1.00全部创建Milk-power 2011-10-26 1.10修改键盘程序Milk-power Milk-power 2011-11-08 1.20修改开发板外观图片

版权声明本手册版权归属https://www.wendangku.net/doc/f75171453.html,（以下简称“Milk-Power”）所有,并保留一切权力。非经Milk-Power同意(书面形式)，任何单位或个人不得擅自摘录本手册部分或全部，违者我们将追究其法律责任。敬告：在售开发板的手册会经常更新，请在https://www.wendangku.net/doc/f75171453.html, 网站查看最近更新，并下载最新手册，不再另行通知。

目录目录 (4) 4写在前面........................................................................................................................ ........................................................................................................................55第一章买到DL-51该如何下手 (6) 6第二章DL-51硬件资源.............................................................................................. ..............................................................................................772.1DL-51开发板硬件概述.. (7) 2.2DL-51开发板硬件资源清单 (8) 2.3DL-51开发板的特点 (9) 2.4DL-51开发板原理图说明 (10) 2.4.1电源电路 (10) 2.4.2系统时钟电路 (10) 2.4.3复位电路 (11) 2.4.4用户LED 电路 (11) 2.4.5数码管电路 (11) 2.4.6串口电路 (12) 2.4.7按键电路 (12) 2.4.8LCD 液晶接口电路 (13) 2.4.9外扩IO 接口电路 (14) 第三章DL-51单片机开发快速入门........................................................................ ........................................................................15153.1单片机开发流程简介 (15) 3.2简单的单片机开发举例 (17) 工作室简介 (18) 18

STM32F0-DISCOVERY用户手册

1/30 文档ID 022910第1版2012年3 月 STM32F0DISCOVERY STM32F0探索套件 UM1525 前言 STM32F0DISCOVERY 是意法半导体STM32F0系列微控制器的探索套件，用于帮助你探索STM32F0 Cortex-M0微控制器的功能，轻松开发应用设计。STM32F0探索套件基于1颗STM32F051R8T6微控制器，组件包括ST-LINK/V2嵌入式调试工具、LED 指示灯、按键和1个原型板。图1： STM32F0 探索套件用户手册

2/30UM1525 文档ID 022910第1版目录目录 1. 约定....................................................................................................................................52. 快速入门 (6) 2.1 开始使用........................................................................................................ 62.2 系统要求..........................................................................................................62.3 支持STM32F0探索套件的开发工具链 .......................................................62.4 订货代码. (6) 3. 特性....................................................................................................................................74. 硬件与原理图.. (8) 4.1 STM32F051R8T6 微控制器 ..........................................................................114.2 嵌入式ST-LINK/V2编程器/调试器 . (13) 4.2.1 使用ST-LINK/V2向板载STM32F0烧录和调试代码 ............................14 4.2.2 使用ST-LINK/V2向外部STM32应用板烧录和调试代码. (15) 4.3电源和电源选择............................................ 164.4 LED 指示灯 ...................................................................................................164.5 按键................................................................................................................164.6 JP2（Idd ）﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍﹍ 16 4.7 OSC 时钟 -----------------------------------------------------------------------------174.7.1 OSC 时钟电源 .............................................................................................174.7.2 OSC 32kHz 时钟电源 17 4.8 焊桥.................................................................................................................184.9 扩展连接器.. (19) 5. 尺寸图..............................................................................................................................266. 原理图..............................................................................................................................277. 修改历史记录 (30)

单片机开发板操作手册.

单片机开发板操作手册一、概述 1，多功能单片机开发板，板载资源非常丰富，仅是包括的功能（芯片）有：步进电机驱动芯片ULN2003、八路并行AD转换芯片ADC0804、八路并行DA转换芯片DAC0832、光电耦合（转换）芯片MOC3063、八路锁存器芯片74HC573、实时时钟芯片DS1302及备用电池、 IIC总线芯片A T24C02、串行下载芯片MAX232CPE，双向可控硅BTA06-600B、 4*4矩阵键盘、 4位独立按键、 DC5V SONGLE继电器、 5V蜂鸣器、八位八段共阴数码管 5V稳压集成块78M05 八路发光二极管显示另还有功能接口（标准配置没有芯片但留有接口，可直接连接使用）：单总线温度传感器DS18B2接口、红外线遥控接收头SM003接口8、蓝屏超亮字符型液晶1602接口、蓝屏超亮点阵图形带中文字库液晶12864接口、 2（4）相五线制小功率步进电机接口、外接交流（7V-15V）电源接口 USB直接取电接口镀金MCU晶振座 40DIP锁紧座外接电源和5V稳压电源的外接扩展接口及MCU所有IO口扩展2，可以完成的单片机实验： 1、LED显示实验（点亮某一个指示灯、流水灯）， 2、八位八段数码管显示实验（你可以任意显示段字符和数字以及开发板所有功能芯片的显示）， 3、液晶显示（1602液晶显示、12864点阵中文图形液晶显示、可以显示出开发板所有功能芯片的操作）， 4、继电器的操作 5、蜂鸣器的操作（你可以编写程序让它发出美妙动听的歌声） 6、可控硅的操作（胆大的朋友就利用这一独有的功能吧，你见过实验室温度实验箱没有，它的驱动就是这样的；聪明的朋友就可以自己写个程序把把加热温度温度恒定在（X±0.5）度的范围内了 7、步进电机的操作（这个是迈向自动化控制的第一步，现在的数控机床、机器人呀

AX301用户手册REV1.0

FPGA黑金开发平台用户手册 AX301 REV 1.0 芯驿电子科技（上海）有限公司黑金动力社区 https://www.wendangku.net/doc/f75171453.html,

目录一、简介 (3) 二、电源 (6) 三、FPGA (7) 1)JTAG接口 (8) 2)配置芯片：M25P16 (8) 3)FPGA供电引脚 (9) 4)FPGA时钟输入引脚 (10) 四、50M有源晶振 (11) 五、SDRAM (11) 六、EEPROM 24LC04 (14) 七、PS/2接口 (15) 八、实时时钟DS1302 (16) 九、数码管 (17) 十、USB转串口 (19) 十一、VGA接口 (20) 十二、蜂鸣器 (23) 十三、SD卡槽 (24) 十四、扩展口 (25) 十五、LED (27) 十六、按键 (28) 十七、摄像头接口 (29) 十八、7寸TFT接口 (30)

FPGA黑金开发平台学生版2014款正式发布了，此款开发平台是在前两款学生版的基础上升级而来，型号为：AX301。虽然是一款入门级的FPGA开发平台，但是我们不管是在PCB设计上，还是在整个构造上都花费了很多的心思，真可谓“简约而不简单”。一、简介在这里，对这款FPGA开发平台进行简单的功能介绍。此款开发板使用的是ALERA公司的CYCLONE IV系列FPGA，型号为EP4CE6F17C8，256个引脚的FBGA封装。根据ALTERA官方的数据，CYCLONE IV相对CYCLONE III来说，功耗减少25%，如下图所示此款FPGA的资源如下图所示：

其中，主要的参数，逻辑单元LE：6272；乘法器LAB：392； RAM：276480bit； IO数量：179个；内核电压：1.15V-1.25V(推荐1.2V); 工作温度：0-85℃ 图为整个系统的结构示意图：

EXCD1开发板使用手册

EXCD‐1开发板参考手册北京中教仪装备技术有限公司 2010年3月

目录 1 概述 (1) 2 板上资源 (2) 3 使用说明 (3) 3.1使用前准备 (3) 3.2输入时钟 (4) 3.3LED，拨码开关和按键 (5) 3.47段数码管 (9) 3.5VGA接口 (10) 3.6RS232串口 (12) 3.7PS/2鼠标键盘接口 (13) 3.8I/O扩展接口 (14) 3.9SRAM和F LASH存储器 (16) 联系我们地址：北京市西城区德外大街4号C座邮编：100120 客户服务热线：4006061700 传真 : 010- 58582440 销售Email : ECsales@https://www.wendangku.net/doc/f75171453.html, 技术支持Email：Ecservice@https://www.wendangku.net/doc/f75171453.html, 网址：https://www.wendangku.net/doc/f75171453.html,

1 概述 EXCD-1是一款易于使用的开发板，它能够实现大量基于FPGA 的数字系统。开发板采用Xilinx Spartan 3E FPGA 器件，板上资源丰富，有2Mbytes 的Flash 和1Mbytes 的快速SRAM ，以及各种输入输出设备，可以方便的设计具有各种功能的数字系统，也可设计含有Xilinx MicroBlaze 软核的嵌入式处理器系统。EXCD-1开发板有5个扩展接口，可灵活的扩展各种功能模块，如数模转换模块，模数转换模块，LCD 显示模块等。 VGA 接口RS232PRom PS2LEDs 晶振图1-1 EXCD-1开发板

2板上资源 displays 4 buttons port2 图2-1 EXCD-1板上资源框图 1.Xilinx Spartan 3E XC3S500E PQ208 FPGA器件 z10,476 逻辑单元 z1,164 CLBs z73Kbits分布式RAM z360Kbits块RAMs z20个专用乘法器 z4个DCMs z158个用户I/O管脚 z PQ208管脚封装 2.时钟：50MHZ晶振输入 3.高速异步SRAM z512K × 16bits 4.Flash存储器 z1M ×16bits 5.配置Flash： XCF04S

Xilinx 开发板用户手册

SP605 Hardware User Guide UG526 (v1.6) July 18, 2011

? Copyright 2009–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DISCLAIMER The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR ST ATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. Y ou may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at https://www.wendangku.net/doc/f75171453.html,/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: https://www.wendangku.net/doc/f75171453.html,/warranty.htm#critapps. Revision History The following table shows the revision history for this document. Date Version Revision 10/07/09 1.0Initial Xilinx release. 11/09/09 1.1?Updated Figure1-17 and Figure1-23. ?Changed speed grade from -2 to -3. ?Miscellaneous typographical edits. 02/01/10 1.1.1Minor typographical edits to Table1-24 and Table1-25. 05/18/10 1.2Updated Figure1-2. Added Note 6 to Table1-11. Updated board connections for SFP_TX_DISABLE in Table1-12. Added note about FMC LPC J63 connector in 18. VITA 57.1 FMC LPC Connector. Updated U1 FPGA Pin column for FMC_LA00_CC_P/N in Table1-28. Updated description of PMBus Pod and TI Fusion Digital Power Software GUI in Onboard Power Regulation. Updated Appendix B, VITA 57.1 FMC LPC Connector Pinout, and Appendix C, SP605 Master UCF. 06/16/10 1.3Updated 2. 128 MB DDR3 Component Memory. Added note 1 to Table1-30. 09/24/10 1.4Updated description of Fusion Digital Power Software in Onboard Power Regulation. 02/16/11 1.5Revised oscillator manufacturer information from Epson to SiTime in Table1-1. Revised oscillator manufacturer information from Epson to SiTime on page page23. Deleted note on page 44 referring to J55: “Note: This header is not installed on the SP605 as built.” Revised values for R50 and R216 in Figure1-12. Revised oscillator manufacturer information from Epson to SiTime on page page69. 07/18/11 1.6Corrected “jitter” to “stability” in section Oscillator (Differential), page23. Revised the feature and notes descriptions for reference numbers 6 and 12 in Table1-1, page10. Revised FPGA pin numbers for ZIO and RZQ in Table1-4, page14. Added Table1-29, page52, Table1-31, page55, and table notes in Table1-30. SP605 Hardware User Guide https://www.wendangku.net/doc/f75171453.html, UG526 (v1.6) July 18, 2011