MAXQ3180-RAN+中文资料
General Description
The MAXQ3180 is a dedicated electricity measurement front-end that collects and calculates polyphase volt-age, current, power, energy, and many other metering and power-quality parameters of a polyphase load. The computed results can be retrieved by an external mas-ter through the on-chip serial peripheral interface (SPI?) bus. This bus is also used by the external mas-ter to configure the operation of the MAXQ3180 and monitor the status of operations.
The MAXQ3180 performs voltage and current measure-ments using an integrated ADC that can measure up to seven external differential signal pairs. An eighth differ-ential signal pair is used to measure the die tempera-ture. An internal amplifier automatically adjusts the current channel gain to compensate for low-current channel-signal levels.
Applications
3-Phase Multifunction Electricity Meters Remote Terminal Unit (RTU) Applications for Electric Load Management
Features
?Supports IEC 60687, IEC 61036, and IEC 61268Standards
?Compatible with 3-Phase/3-Wire, 3-Phase/4-Wire,and Other 3-Phase Services
?Calculates Active/Reactive/Apparent Energy, RMS Voltage, RMS Current, Voltage Phasor Angle, and Line Frequency
?Less Than 0.1% Active Energy Error Over a Dynamic Range of 1000:1 at +25°C
?Less Than 0.2% Reactive Energy Error Over a Dynamic Range of 1000:1 at +25°C
?Better Than 0.5% Accuracy for RMS Voltage and RMS Current
?Two Pulse Outputs: One for Active Power and One Selectable Between Reactive and Apparent Power
?Programmable Pulse Width
?Programmable Startup Current Threshold ?Programmable Meter Constant ?Up to 21st Harmonic Measurement ?Neutral Line Current Measurement
?Calculates Amp-Hours in the Absence of Voltage Signals
?On-Chip User-Programmable Thresholds for Line Voltage Undervoltage and Overvoltage Detection ?On-Chip Digital Integrator Enables Direct
Interface-to-Current Sensors with di/dt Output ?On-Chip Digital Temperature Sensor
?Precision Internal Voltage Reference 2.048V (30ppm/°C Typical); Also Supports an External Voltage Reference Input
?Active Energy of Each Phase and Combined 3-Phase (kWh), Positive and Negative
?Active Power of Each Phase and Combined 3-Phase (kW)
?Reactive Energy of Each Phase and Combined 3-Phase (kVarh), Quadrants 1 to 4
?Reactive Power of Each Phase and Combined 3-Phase (kVar)
?Apparent Energy of Each Phase and Combined 3-Phase (kVAh)
?Apparent Power of Each Phase and Combined 3-Phase (kVA)
?Line Frequency (Hz)?Power Factor
?Overcurrent and Overvoltage Detection ?Voltage Sag Detection
?RMS Current and RMS Voltage
?Line-Cycle-Wise Instant Current, Voltage, and Power
?Phase Sequence Error Detection ?Phase Voltage Absence Detection ?Supports Software Meter Calibration ?Up to 3-Point Multipoint Calibration to Compensate for Transducer Nonlinearity ?Power-Fail Detection
?Bidirectional Reset Input/Output
?SPI-Compatible Serial Interface with Interrupt Request (IRQ ) Output
?Single 3.3V Supply, Low Power (10mW Typical)?28-Pin TSSOP Package
MAXQ3180
Low-Power, Multifunction, Polyphase AFE
________________________________________________________________Maxim Integrated Products 1
Ordering Information
Rev 0; 2/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at https://www.wendangku.net/doc/f05385024.html,.
Note:Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: https://www.wendangku.net/doc/f05385024.html,/errata .
MAXQ is a registered trademark of Maxim Integrated Products, Inc.SPI is a trademark of Motorola, Inc.
Pin Configuration and Typical Application Circuit appear at end of data sheet.
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ABSOLUTE MAXIMUM RATINGS
METERING SPECIFICATIONS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on DVDD Relative to DGND .........-0.3V to +4.0V Voltage Range on AVDD Relative to AGND..........-0.3V to +4.0V Voltage Range on AGND Relative to DGND..........0.3V to +0.3V Voltage Range on AVDD Relative to DVDD..........-0.3V to +0.3V Voltage Range on Any Pin Relative to
GND or AGND...................................................-0.3V to +4.0V
Operating Temperature Range ...........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +150°C Lead Soldering Temperature.............................Refer to the IPC/
JEDEC J-STD-020 Specification.
ELECTRICAL CHARACTERISTICS
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ELECTRICAL CHARACTERISTICS (continued)
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ELECTRICAL CHARACTERISTICS (continued)
Note 3:Specifications to -40°C are guaranteed by design and are not production tested.
SPI Slave Mode Timing
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Block Diagram
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Detailed Description
Operating Modes
The MAXQ3180 has four basic modes of operation,each of which is described in the following sections.The Initialization Mode is the default mode upon power-up or following reset; entry to and exit from the other operating modes is only performed as a result of com-mands sent by the master.
Initialization Mode
This is the default operating mode for the MAXQ3180following reset, power-up, or a switch into or out of Low-Power Measurement Mode (LPMM). In this mode, no power measurements are taken because the MAXQ3180 has not yet been configured. When entering this mode, the MAXQ3180 sets the status flag NOINIT to 1 and drives the IRQ pin low to indicate to the master that initialization is required. The master is responsible for performing the following series of operations:
?Interrogating the MAXQ3180 to determine that the NOINIT bit has been set.
?Loading all RAM configuration registers with appro-priate values.
?Clearing the NOINIT bit to zero.
Once the NOINIT bit has been cleared to zero, the MAXQ3180 exits Initialization Mode and enters Run Mode (or LPMM mode if LOWPM = 1). It is the master’s responsibility to ensure that all configuration registers have been set to their correct values before clearing the NOINIT bit.
Run Mode
This mode is the normal operating mode for the MAXQ3180. In this mode, the MAXQ3180 continuously executes the following operations:
?Scans analog front-end channels and collects raw voltage and current samples.
?Processes voltage and current samples through DSP filters as enabled and configured.
?Calculates power, energy, and other required quanti-ties and stores these values in RAM registers.
?Responds to register write and read commands from the master.
?Outputs power pulses on CFP and CFQ as configured.?Drives IRQ when an interrupt condition has been detected and the interrupt is not masked.Low-Power Measurement Mode (LPMM)
This mode allows the MAXQ3180 to perform all normal electric-metering functions while operating at a
reduced clock rate to conserve power. In this mode,the MAXQ3180 switches its system clock from the high-frequency external crystal (or external clock source) to its internal RC oscillator. The actual system clock fre-quency used is the RC oscillator output frequency divided by 8, which results in a system clock frequency of approximately 1MHz.
Entry to LPMM Mode only occurs at the request of the master. The master must set the LOWPM bit (STATUS.2)to 1 to place the MAXQ3180 into LPMM mode. Setting this bit automatically sets the NOINIT bit and returns the device to Initialization Mode. This is done because changing the clock frequency invalidates a number of configuration registers, which need to be reinitialized with new, updated values before metering-measure-ment operations can continue. Note that it is also possi-ble to set LOWPM = 1 (and load configuration registers appropriately) immediately following reset, which caus-es the MAXQ3180 to transition directly from Initialization Mode to LPMM Mode once NOINIT has been cleared by the master.
The master can also instruct the MAXQ3180 to exit LPMM Mode by clearing the LOWPM bit. This causes NOINIT to be set as with LPMM entry, and the master must reset the appropriate configuration registers and clear NOINIT to allow measurement to continue.
Stop Mode
This mode places the MAXQ3180 into a power-saving state where it consumes the least possible amount of current. In Stop Mode, all functions are suspended,including the ADC and power and voltage measurement and processing. The MAXQ3180 does not respond to any commands from the master in this operating state.Entry into Stop Mode only occurs at the request of the master. To place the MAXQ3180 into Stop Mode, the master must set the STOPM bit (STATUS.1) to 1. Once this bit has been written, the MAXQ3180 enters Stop Mode immediately following the end of the register write command (after the transmission of the final ACK byte by the MAXQ3180).
There are three possible ways to bring the MAXQ3180back out of Stop Mode.
?Power Cycle. The MAXQ3180 automatically exits Stop Mode if a power-on reset occurs. Following exit from Stop Mode, all registers are cleared back to their default states, and the MAXQ3180 transitions to Initialization Mode.
?External Reset.The MAXQ3180 exits Stop Mode if an external reset is triggered by driving RESET low.Once the RESET pin is released and allowed to
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Figure 1. Operating Modes
return to a high state, the MAXQ3180 comes out of reset and goes into Initialization Mode. All registers are cleared to their default states when exiting Stop Mode in this manner.
?External Interrupt. Driving the SSEL pin low causes the MAXQ3180 to exit Stop Mode without undergoing a reset cycle. When exiting Stop Mode in this man-ner, all register and configuration settings are retained, and the MAXQ3180 automatically resumes electric-metering functions and sample processing.Note that when the master is communicating with the MAXQ3180, the SSEL line is normally driven low at the beginning of each SPI command. This means that if the master sends an SPI command after the MAXQ3180enters Stop Mode, the MAXQ3180 automatically exits Stop Mode and receives the command.
Reset Sources
There are several different sources that can cause the MAXQ3180 to undergo a reset cycle. For any type of hardware reset, the RESET pin is driven low when a reset occurs.
External Reset
This hardware reset is initiated by an external source (such as the master controller or a manual pushbutton press) driving the RESET pin on the MAXQ3180 low.The RESET line must be held low for at least four cycles of the currently selected clock for the external reset to take effect. Once the external reset takes effect, it remains in effect indefinitely as long as RESET is held low. Once the external reset has been released, the MAXQ3180 clears all registers to their default states and resumes execution in Initialization Mode.
When an external reset occurs outside of Stop Mode,execution (in Initialization Mode) resumes after four cycles of the currently selected clock (external high-fre-quency crystal for Run Mode, 1MHz internal RC oscilla-tor for LPMM Mode). As the MAXQ3180 enters Initialization Mode, the LOWPM bit is always cleared to 0, meaning that the MAXQ3180 always switches to the high-frequency clock before it begins accepting com-mands in Initialization Mode.
When an external reset occurs from Stop Mode, execu-tion (in Initialization Mode) resumes after 128 cycles of the internal RC oscillator (or approximately 128μs).
Power-On Reset
When the MAXQ3180 is first powered up, or when the power supply, DV DD , drops below the V RST power-fail trip point (outside of Stop Mode), the MAXQ3180 is held in power-on reset. Once the power supply rises above the V RST level, the power-on reset state is released and all registers are reset to their defaults and execution resumes in Initialization Mode. The high-fre-quency external crystal (LOWPM = 0) is always select-ed as the clock source following any power-on or brownout reset.
In Stop Mode brownout detection is disabled, so a power-on reset does not occur until DV DD drops to a lower level (V POR ). From the master’s perspective,power-on resets and brownout resets both cause the MAXQ3180 to reset in the same way.
Watchdog Reset
The MAXQ3180 includes a hardware watchdog timer that is armed and periodically reset automatically during nor-mal operation. Under normal circumstances, the MAXQ3180 always resets the watchdog timer often enough to prevent it from expiring. However, if an internal
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Figure 2. External Reset
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error of some kind causes the MAXQ3180 to lock up or enter an endless execution loop, the watchdog timer expires and triggers an automatic hardware reset. There is no register flag to indicate to the master that a watch-dog reset has occurred, but the RESET line strobes low briefly. Because the reset causes the MAXQ3180 to re-enter Initialization Mode, the IRQ line drops low.
The watchdog timer does not run during Stop Mode.
Software Reset
A software reset is initiated by the master by setting the RST (STATUS0.4) bit to 1. When a software reset occurs, the MAXQ3180 clears all registers to their default states and returns to Initialization Mode, in the same manner as if an external reset had taken place.Unlike a hardware reset, however, a software reset does not cause the MAXQ3180 to drive the RESET line low.
Power-Supply Monitoring
In addition to the hardware reset provided by the power-on reset and brownout reset circuits, the MAXQ3180 includes the capability to detect a low power supply on the DVDD pin and alert the master through the interrupt (IRQ ) mechanism before a hard-ware reset occurs. This function, which is always enabled outside of Stop Mode, causes the RAM status register flag PWRF (STATUS1.1) to be set to 1 whenev-er DV DD drops below the V PFW trip point. Once PWRF has been set to 1 by hardware, it can only be cleared by the master (or by a system reset). Whenever PWRF = 1, if the EPWRF interrupt masking bit is also set to 1,the MAXQ3180 drives IRQ low to signal to the master that an interrupt condition (in this case, a power-fail warning) exists and requires attention.
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Figure 3. Brownout Reset
Clock Sources
All operations including ADC sampling and SPI com-munications are synchronized to a single system clock.This clock can be obtained from any one of three selec-table sources, as shown in Figure 4.
External High-Frequency Crystal
The default system clock source for the MAXQ3180 is an external high-frequency crystal oscillator circuit con-nected between XTAL1 and XTAL2. When clocked with an external crystal, a parallel-resonant, AT-cut crystal oscillating in the fundamental mode is required. The typical values of the external load capacitors vary with the type of crystal being used and should be selected based on the load capacitance as suggested by the crystal manufacturer.
When using a high-frequency crystal, the fundamental oscillation mode of the crystal operates as inductive reactance in parallel resonance with external capaci-tors C1 and C2. The typical values of these external capacitors vary with the type of crystal being used and should be selected based on the load capacitance as suggested by the crystal manufacturer.
Since noise at XTAL1 and XTAL2 can adversely affect device timing, the crystal and capacitors should always be placed as close as possible to the XTAL1 and XTAL2 pins, with connection traces between the crystal
and the device kept as short and direct as possible. In multiple layer boards, avoid running other high-speed digital signals underneath the crystal oscillator circuit if possible, as this may inject unwanted noise into the clock circuit.
Following power-up or any system reset, the high-fre-quency clock is automatically selected as the system clock source. However, before this clock can be used for system execution, a crystal warmup timer must count 65,536 cycles of the high-frequency clock. While this warmup time period is in effect, execution contin-ues using the internal 1MH z oscillator. Once the 65,536-cycle count completes (which requires approxi-mately 8.2ms at 8MH z), the device automatically switches over to the high-frequency clock. This crystal warmup timer is also activated upon exit from Stop Mode, since the high-frequency crystal oscillator is shut down during Stop Mode.
External High-Frequency Clock
Instead of using a crystal oscillator to generate the high-frequency clock, it is also possible to input a high-frequency clock that has been generated by another source (such as a digital oscillator IC) directly into the XTAL1 pin of the MAXQ3180.
To use an external high-frequency clock as the system clock source, the XTAL1 pin should be used as the
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Figure 4. Simplified Clock Sources
M A X Q 3180
clock input and the XTAL2 pin should be left uncon-nected. The master should also shut down the internal crystal oscillator circuit by setting the EXTCLK bit (STA-TUS0.6) to 1. This bit is only cleared by the MAXQ3180if a power-on or brownout reset occurs and is unaffect-ed by other resets.
When using an external high-frequency clock, the clock signal should be generated by a CMOS driver. If the clock driver is a TTL gate, its output must be connected to DVDD through a pullup resistor to ensure that the correct logic levels are generated. To minimize system noise in the clock circuitry, the external clock source must meet the maximum rise and fall times and the minimum high and low times specified for the clock source in the Electrical Characteristics table.
Internal RC Oscillator
When the external high-frequency crystal is warming up, or when the MAXQ3180 is placed into LPMM mode,the system clock is sourced from an internal RC oscilla-tor. This internal oscillator is designed to run at approxi-mately 8MHz, although the exact frequency varies over temperature and supply voltage.
If no external crystal circuit or high-frequency clock will be used, the MAXQ3180 can be forced to operate indefinitely from the internal oscillator by grounding XTAL1. This ensures that the crystal warmup count never completes, so the MAXQ3180 runs from the inter-nal oscillator in all active modes (Initialization Mode,Run Mode, and LPMM Mode).
Master Communications
Before the MAXQ3180 can begin performing electric-metering operations, the master must initialize a num-ber of configuration parameters. Since the MAXQ3180does not contain internal nonvolatile memory, these parameters (stored in internal registers) must be set by the master each time a power-up or reset cycle occurs,or each time a switch is made between LPMM Mode and Run Mode.
The external master communicates with the MAXQ3180over a standard SPI bus, using commands to read and write values to internal registers on the MAXQ3180.These registers include, among many other items:
?Operating mode settings (Stop Mode, LPMM Mode,external clock mode, etc.)
?Status and interrupt flags (not initialized, power-sup-ply failure, overcurrent/overvoltage detection)
?Masking control for interrupts to determine which conditions cause IRQ to be driven low ?Configuration settings for analog channel scanning
?Power pulse output configuration
?Filter coefficients and configuration
?Read-only registers containing accumulated power and energy data Once all the configuration registers have been set by the master to their proper values, the master must clear the NOINIT flag (STATUS1.0) to zero. Once this flag has been cleared, the MAXQ3180 exits Initialization Mode and begins execution in either Run Mode or LPMM Mode, depending on the setting of the LOWPM bit.
As the MAXQ3180 obtains voltage and current mea-surements in Run Mode or LPMM Mode, it accumu-lates, filters, and performs a number of calculations on the collected data. Many of these operations (including the various filtering stages) are configured by settings in registers written by the master. The output results can then be read by the master from various read-only registers in parallel with the ongoing measurement and processing operations.
SPI Communications Rate and Format
The MAXQ3180 provides an SPI bus for master/slave communications. All communications transfers are initi-ated by the external master. The interrupt request line IRQ , while not technically part of the SPI bus interface,is also used for master/slave communications, since it allows the MAXQ3180 to notify the master that an inter-rupt condition exists.
During an SPI transfer, data is simultaneously transmit-ted and received over two serial data lines (MISO and MOSI) with respect to a single serial shift clock (SCLK).The polarity and phase of the serial shift clock are the primary components in defining the SPI data transfer format. The polarity of the serial clock corresponds to the idle logic state of the clock line and, therefore, also defines which clock edge is the active edge. To define a serial shift clock signal that idles in a logic-low state (active clock edge = rising), the clock polarity select (CKPOL; SPICF.0) bit should be configured to a 0,while setting CKPOL = 1 causes the shift clock to idle in a logic-high state (active clock edge = falling). The phase of the serial clock selects which edge is used to sample the serial shift data. The clock phase select (CKPH A; SPICF.1) bit controls whether the active or inactive clock edge is used to latch the data. When CKPHA is set to a logic 1, data is sampled on the inac-tive clock edge (clock returning to the idle state). When CKPH A is set to a logic 0, data is sampled on the active clock edge (clock transition to the active state).Together, the CKPOL and CKPHA bits allow four possi-ble SPI data transfer formats.
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Figure 5a. SPI Interface Timing (CKPHA = 1). With CKPHA = 1 and CKPOL = 1, the SPI interface clocks data into the peripheral device on the clock’s rising edge and data out of the peripheral on the clock’s falling edge.
Figure 5b. SPI Interface Timing (CKPHA = 0). With CKHPA = 0 and CKPOL = 1, the SPI interface clocks data into the peripheral device on the clock’s falling edge and data out of the peripheral on the clock’s rising edge.
Transfers over the SPI interface always start with the most significant bit and end with the least significant bit. All SPI data transfers to and from the MAXQ3180are always 8 bits (one byte) in length. The MAXQ3180SPI interface does not support 16-bit character lengths.The default format (upon power-up or system reset) for the MAXQ3180 SPI interface is represented in Figure 5b (CKPOL = 0; CKPHA = 0). In this format, the SPI clock idle state is low, and data is shifted in and out on the rising edge of SCLK. Once SPI communication with the MAXQ3180 has been established, it is possible to alter the CKPOL and CKPHA format settings (as well as changing the SSEL signal from active low to active high) if desired by writing to the R_SPICF mirror register and then reading from the special command register UPD_SFR to copy the R_SPICF value into the internal SPI configuration register.
Whenever the active clock edge is used for sampling (CKPH A = 0), the transfer cycle must be started with assertion of the SSEL signal. This requirement means that the SSEL signal be deasserted and reasserted between successive transfers. Conversely, when the inactive edge is used for sampling (CKPH A = 1), the SSEL signal may remain low through successive
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transfers, allowing the active clock edge to signal the start of a new transfer.
The clock rate used for the SPI interface is determined by the bus master, since the MAXQ3180 always oper-ates as an SPI slave device. H owever, the maximum clock rate is limited by the system clock frequency of the MAXQ3180. For proper communications operation,the SPI clock frequency used by the master must be less than or equal to the MAXQ3180’s clock frequency divided by 8. For example, when the MAXQ3180 is run-ning at 8MHz, the SPI clock frequency must be 1MHz or less. And if the MAXQ3180 is running in LPMM Mode (or if the crystal is still warming up), the SPI clock fre-quency must remain at 125kHz or less for proper com-munications operation.
In addition to limiting the overall SPI bus clock rate, the master must also include a communications delay fol-lowing each byte transmit/receive cycle. This delay,which provides the MAXQ3180 with time to process the transmitted byte, should be a minimum of 1 ADC scan slot (time value contained in TIME_FS register, defined as (R_ADCRATE + 1)/(system clock frequency). With default settings and running at 8MHz, this delay time is 25μs. Reducing the system clock frequency to 1MH z (LPMM mode) would increase this delay period by a factor of 8μs to 200μs.
SPI Communications Protocol
All transactions between the master and the MAXQ3180 consist of the master writing to or reading from one of the MAXQ3180’s registers. There are sever-al different categories of internal registers on the MAXQ3180.
?RAM Registers.The values of these registers are stored in the internal RAM of the MAXQ3180. Some can be read and written by the master, while others are read only. RAM registers are either two or four bytes long (16 or 32 bits), although in some registers not all the bits have defined values. Read/write regis-ters are generally either status/flag registers (which can be written by either the MAXQ3180 or the mas-ter), configuration registers (which are written by the master and read by the MAXQ3180 firmware), or data registers (which are read only and are written by the MAXQ3180 firmware and read by the master).?Virtual Registers.These read-only registers are not stored in RAM; instead, they contain values that are
calculated on the fly by the MAXQ3180 firmware when the master reads them. These registers are used by the master to obtain values such as phase A, B, and C active, reactive, and apparent power;power factor; and RMS voltage and current, which are calculated from currently collected data on an as-needed basis. All virtual registers are 4 bytes in length.
?Hardware Registers.These registers control core functions of the MAXQ3180 including the ADC and the SPI slave bus controller. Each of these registers (R_ACFG, R_ADCRATE, R_ADCADQ, R_SPICF, and STATUS0 (bit 6, EXTCLK only)) has a register loca-tion in RAM that “shadows” the value of the hardware register. To read from a hardware register, the mas-ter must first read from the special command register UPD_MIR (A00h) to copy the values from the hard-ware registers to the mirror registers in RAM, and then the mirror register in RAM can be read. To write to a hardware register, the master reverses the process by writing to the mirror RAM register and then reading from the special command register UPD_SFR (900h) to copy the values from the mirror registers to the hardware registers.
?Special Command Registers.These registers (UPD_SFR and UPD_MIR) do not return meaningful data when read but instead trigger an operation.Reading UPD_SFR causes values to be copied from the mirror registers to hardware, and reading UPD_MIR causes values to be copied from the hard-ware to mirror registers.
Every defined register on the MAXQ3180 has a 12-bit address (from 0 to 4095). This address is used when addressing the register for either a read or write opera-tion. Addresses 0 to 1023 (000h to 3FFh) are used to address RAM registers. Registers with addresses from 1024 to 4095 (400h to FFFh) are used for virtual regis-ters and special command registers.
Each command consists of a read/write command code, a data length (1, 2, 4, or 8 bytes), a 12-bit regis-ter address, and the specified number of data bytes followed optionally by a CRC. Since SPI is a full-duplex interface, the master and slave must both transmit the same number of bytes during the command. When a multiple-byte register is read or written (2/4/8 byte length), the least significant byte is read or written first in the command.
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Optionally, a cyclic redundancy check (CRC) byte can be appended to each transaction. For write commands,the CRC byte is sent by the master, and for read com-mands the CRC byte is sent by the MAXQ3180. The CRC mode is enabled when the CRCEN bit is set to 1in STATUS0 register. Otherwise, the MAXQ3180assumes no CRC byte is used. The 8-bit CRC is calcu-lated for all bytes in a transaction, from the first com-mand byte sent by the master through the last data byte excluding sync bytes, using the polynomial P = x 8+ x 5+ x 4+ 1. If the transmitted CRC byte does not match the calculated CRC byte (for a write command),the MAXQ3180 ignores the command.
The length of the transfer is defined by the first com-mand byte and the status of the CRCEN bit in the
STATUS0 register. There is no special synchronization mechanism provided in this simple protocol. Therefore,the master is responsible for sending/receiving the cor-rect number of bytes. If the master mistakenly sends more bytes than are required by the current command,the extra bytes are either ignored (if the MAXQ3180 is busy processing the previous command) or are inter-preted as the beginning of a new command. If the mas-ter sends fewer bytes than are required by the current command, the MAXQ3180 waits for approximately 200ms, then drops the transaction and resets the com-munication channel. The duration of the timeout can be configured through the COM_TIMO register.
Figures 6 and 7 show typical 2-byte reading and writing transfers (without CRC byte).
Figure 6. Read SPI Transfer
Figure 7. Write SPI Transfer
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