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HY5V52LF-8中文资料

Preliminary HY5V52CF

4 Banks x 2M x 32Bit Synchronous DRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume DESCRIPTION

The Hynix HY5V52CF is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V52CF is organized as 4banks of 2,097,152x32.

HY5V52CF is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-width. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

?JEDEC standard 3.3V power supply

?All device pins are compatible with LVTTL interface

? 90Ball FBGA with 0.8mm of pin pitch

?All inputs and outputs referenced to positive edge of

system clock

?Data mask function by DQM0,1,2 and 3

?Internal four banks operation

?Auto refresh and self refresh

?4096 refresh cycles / 64ms

?Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

?Programmable CAS Latency ; 2, 3 Clocks

?Burst Read Single Write operation ORDERING INFORMATION

Part No.Clock Frequency Organization Interface Package HY5V52(L)F-8125MHz

4Banks x 2Mbits

x32

LVTTL 90Ball FBGA HY5V52(L)F-P100MHz

4Banks x 2Mbits

x32

LVTTL 90Ball FBGA HY5V52(L)F-S100MHz

4Banks x 2Mbits

x32

LVTTL 90Ball FBGA

Ball CONFIGURATION

Ball DESCRIPTION

PIN PIN NAME DESCRIPTION

CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK.

CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh

CS Chip Select Enables or disables all inputs except CLK, CKE and DQM

BA0, BA1Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity

A0 ~ A11Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10

RAS, CAS, WE Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

DQM0~3Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ31Data Input/Output Multiplexed data input / output pin

V DD/V SS Power Supply/Ground Power supply for internal circuits and input buffers

V DDQ/V SSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION (TA=0 to 70°C )

Note :

1.All voltages are referenced to V SS = 0V

2.V IH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes

3.V IL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes

AC OPERATING CONDITION (TA=0 to 70°C , 3.0V ≤V DD ≤3.6V, V SS =0V - Note1)

Note :

1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF) For details, refer to AC/DC output load circuit

Parameter

Symbol

Rating

Unit

Ambient Temperature T A 0 ~ 70°C Storage Temperature

T STG -55 ~ 125°C Voltage on Any Pin relative to V SS V IN , V OUT -1.0 ~ 4.6V Voltage on V DD relative to V SS V DD, V DDQ -1.0 ~ 4.6V Short Circuit Output Current I OS 50mA Power Dissipation

P D 1W Soldering Temperature ? Time

T SOLDER

260 ? 10

°C ? Sec

Parameter

Symbol Min Typ.Max Unit Note Power Supply Voltage V DD , V DDQ 3.135 3.3 3.6V 1Input high voltage V IH 2.0 3.0V DDQ + 0.3

V 1,2Input low voltage

V IL

V SSQ - 0.3

0.8

1,3

Parameter

Symbol Value Unit Note

AC input high / low level voltage

V IH / V IL 2.4/0.4V Input timing measurement reference level voltage Vtrip 1.4V Input rise / fall time

tR / tF 1ns Output timing measurement reference level

Voutref 1.4V Output load capacitance for access time measurement

CAPACITANCE (TA=25°C , f=1MHz, VDD=3.3V)

DC CHARACTERISTICS I (DC operating conditions unless otherwise noted)

Note :

1.V IN = 0 to 3.6V, All other pins are not under test = 0V

2.D OUT is disabled, V OUT =0 to

3.6V

Parameter

Symbol Min Max Unit Input capacitance

CLK

C I1tbd tbd pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3

CI 2tbd tbd pF Data input / output capacitance

DQ0 ~ DQ31

C I/O

tbd

Parameter

Symbol

Min.Max Unit Note Input leakage current I LI -11uA 1Output leakage current I LO -11uA 2

Output high voltage V OH 2.4-V I OH = -2mA Output low voltage

V OL

-0.4

I OL = +2mA

DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)

Note :

1.I DD1 and I DD4 depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3.HY5V52CF-8/P/S

4.HY5V52CL:F-8/P/S

Parameter

Symbol

Test Condition

speed

Unit

Note

-8

-P S Operating Current IDD1Burst length=1, One bank active t RC ≥ t RC (min), I OL =0mA tbd

tbd

Precharge Standby Current

in power down mode

IDD2P CKE ≤ V IL (max), t CK = 10ns tbd

IDD2PS

CKE ≤ V IL (max), t CK = ∞

tbd Precharge Standby Current

in non power down mode

IDD2N

CKE ≥ V IH (min), CS ≥ V IH (min), t CK = 10ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V

tbd

IDD2NS CKE ≥ V IH (min), t CK = ∞Input signals are stable.tbd Active Standby Current in power down mode

IDD3P CKE ≤ V IL (max), t CK = 10ns tbd

IDD3PS

CKE ≤ V IL (max), t CK = ∞

tbd Active Standby Current in non power down mode

IDD3N

CKE ≥ V IH (min), CS ≥ V IH (min), t CK = 10ns Input signals are changed one time during 2clks. All other pins ≥ V DD -0.2V or ≤ 0.2V

tbd

IDD3NS

CKE ≥ V IH (min), t CK = ∞Input signals are stable.

tbd

Burst Mode Operating Current

IDD4

t t CK ≥ t CK (min), I OL =0mA

All banks active

CL=3tbd tbd tbd

CL=2

-tbd tbd Auto Refresh Current

IDD5

t RC ≥ t RC (min), All banks active tbd

tbd

2Self Refresh Current IDD6

CKE ≤ 0.2V

tbd mA

tbd

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v

3.Data-out hold time to be measured under 30pF load condition, without Vt termination

Parameter

Symbol

-8

-P

-S

Unit Note

Min

Max

Min Max

System clock cycle time

CAS Latency = 3tCK38

100010

1000

CAS Latency = 2

tCK2-101012ns Clock high pulse width tCHW 3-3-3-ns 1Clock low pulse width tCLW 3-3-3-ns 1

Access time from clock

CAS Latency = 3

tAC3-6-6-6ns

CAS Latency = 2

tAC2-6-6-6ns Data-out hold time tOH 2-2-2-ns 3Data-Input setup time tDS 2-2-2-ns 1Data-Input hold time tDH 1-1-1-ns 1Address setup time tAS 2-2-2-ns 1Address hold time tAH 1-1-1-ns 1CKE setup time tCKS 2-2-2-ns 1CKE hold time tCKH 1-1-1-ns 1Command setup time tCS 2-2-2-ns 1Command hold time

tCH 1-1-1-ns 1CLK to data output in low Z-time tOLZ 1-1-1-ns CLK to data output in high Z-time

CAS Latency = 3tOHZ3-6-6-6ns CAS Latency = 2tOHZ2

-6

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

Parameter Symbol

-8-P-S

Unit

Not

e Min Max Min Max Min Max

RAS cycle time

Operation tRC64-70-70-ns

Auto Refresh tRRC64-70-70-ns RAS to CAS delay tRCD20-20-20-ns

RAS active time tRAS48100

100

RAS precharge time tRP20-20-20-ns RAS to RAS bank active delay tRRD2-20-20-CLK CAS to CAS delay tCCD1-1-1-CLK Write command to data-in delay tWTL0-0-0-CLK Data-in to precharge command tDPL1-1-1-CLK Data-in to active command tDAL4-4-4-CLK DQM to data-out Hi-Z tDQZ2-2-2-CLK DQM to data-in mask tDQM0-0-0-CLK MRS to new command tMRD2-2-2-CLK

Precharge to data output Hi-Z CAS Latency = 3tPROZ33-3-3-CLK CAS Latency = 2tPROZ22-2-2-CLK

Power down exit time tPDE1-1-1-CLK

Self refresh exit time tSRE1-1-1-CLK1 Refresh Time tREF-64-64-64ms

Note :

1. A new command can be given tRRC after self refresh exit

COMMAND TRUTH TABLE

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don ′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation

3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.

Command

CKEn-1CKEn CS RAS CAS WE DQM ADDR

A10/AP BA Note

Mode Register Set H X L L L L X OP code

No Operation H X

H X X X

X L

H H H Bank Active H

X L L H H X RA

V Read

Read with Autoprecharge H Write

X L H L L X CA

V Write with Autoprecharge H Precharge All Banks

X Precharge selected Bank L V

Burst Stop H X

H H

X X DQM H X V X Auto Refresh H H L L L H X X

Burst-Read-Single-WRITE

H X L L L L X A9 Pin High

(Other Pins OP code)

MRS Mode

Self Refresh 1

Entry

H L L L L H X

Exit

L H H H Precharge power down

Entry

L H H H

Exit

L H H H Clock Suspend

Entry H L

Exit

PACKAGE INFORMATION

90Ball FBGA with 0.8mm of pin pitch ( using ‘Multi Chip Package’ Technology)

1.30