当前位置：文档库 › MSP430FE425AIPM中文资料

MSP430FE425AIPM中文资料

D Wake-Up From Standby Mode in Less Than 6μs

D Frequency-Locked Loop,FLL+D 16-Bit RISC Architecture,125-ns Instruction Cycle Time

Embedded Signal Processing for Single-Phase Energy Metering With Integrated Analog Front-End and Temperature Sensor (ESP430CE1A)D 16-Bit Timer_A With Three Capture/Compare Registers

D Integrated LCD Driver for 128Segments D

Serial Communication Interface (USART),Asynchronous UART or Synchronous SPI Selectable by Software

Fuse

D Bootstrap Loader in Flash Devices D

Family Members Include:--MSP430FE423A:

8KB +256B Flash Memory,256B RAM

--MSP430FE425A:

16KB +256B Flash Memory,512B RAM

--MSP430FE427A:

32KB +256B Flash Memory,1KB RAM

D Available in 64-Pin Quad Flat Pack (QFP)D

For Complete Module Descriptions,Refer to the MSP430x4xx Family User’s Guide ,Literature Number SLAU056

description

The Texas Instruments MSP430family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications.The architecture,combined with five low power modes,is optimized to achieve extended battery life in portable measurement applications.The device features a powerful 16-bit RISC CPU,16-bit registers,and constant generators that contribute to maximum code efficiency.The digitally controlled oscillator (DCO)allows wake-up from low-power modes to active mode in less than 6μs.

The MSP430FE42xA series are microcontroller configurations with three independent 16-bit sigma-delta A/D converters and embedded signal processor core used to measure and calculate single-phase energy in both 2-wire and 3-wire configurations.Also included are a built-in 16-bit timer,128LCD segment drive capability,and 14I/O pins.

Typical applications include 2-wire and 3-wire single-phase metering including tamper-resistant meter implementations.

This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.These devices have limited built-in ESD protection.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.

AVAILABLE OPTIONS

PACKAGED DEVICES

T A

PLASTIC 64-PIN QFP

(PM)--40°C to 85°C

MSP430FE423AIPM MSP430FE425AIPM MSP430FE427AIPM

pin designation

P1.5/TACLK/ACLK/S28P 2.3/S V S I N P 2.4/U T X D 0P 2.5/U R X D 0R S T /N M I T C K T M S T D I /T C L K T D O /T D I P 1.0/T A 0P 1.1/T A 0/M C L K P 1.2/T A 1/S 31P 1.3/S V S O U T /S 30P 1.4/S 29

S 5S 6S 7S 8S 9S 10S 11S 12S 13S 14S 15S 16S 17S 18S 19S 20

P1.6/SIMO0/S27P1.7/SOMI0/S26P2.0/TA2/S25P2.1/UCLK0/S24R33R23R13R03COM3COM2COM1COM0S23S21

S22I1+I1--I2+I2--V1+V1--XIN XOUT P2.2/STE0

S0S1S2S4

S3V REF

A V C C

DV CC A V S S

D V S S

It is recommended to short unused analog input pairs and connect them to analog ground.

functional block diagram

DV AV AV

Terminal Functions

TERMINAL

DESCRIPTION

I/O

NAME NO.

DV CC1Digital supply voltage,positive terminal.

I1+2I Current1positive analog input.Internal connection to SD16Channel0A0+.(see Note1)

I1--3I Current1negative analog input.Internal connection to SD16Channel0A0--.(see Note1)

I2+4I Current2positive analog input.Internal connection to SD16Channel1A0+.(see Note1)

I2--5I Current2negative analog input.Internal connection to SD16Channel1A0--.(see Note1)

V1+6I Voltage1positive analog input.Internal connection to SD16Channel2A0+.(see Note1)

V1--7I Voltage1negative analog input.Internal connection to SD16Channel2A0--.(see Note1)

XIN8I Input for crystal oscillator XT1.Standard or watch crystals can be connected.

XOUT9O Output of crystal oscillator XT1

V REF10I/O Input for an external reference voltage/internal reference voltage output(can be used as mid-voltage) P2.2/STE011I/O General-purpose digital I/O/slave transmit enable—USART0/SPI mode

S012O LCD segment output0

S113O LCD segment output1

S214O LCD segment output2

S315O LCD segment output3

S416O LCD segment output4

S517O LCD segment output5

S618O LCD segment output6

S719O LCD segment output7

S820O LCD segment output8

S921O LCD segment output9

S1022O LCD segment output10

S1123O LCD segment output11

S1224O LCD segment output12

S1325O LCD segment output13

S1426O LCD segment output14

S1527O LCD segment output15

S1628O LCD segment output16

S1729O LCD segment output17

S1830O LCD segment output18

S1931O LCD segment output19

S2032O LCD segment output20

S2133O LCD segment output21

S2234O LCD segment output22

S2335O LCD segment output23

COM036O Common output COM0--3are used for LCD backplanes.

COM137O Common output COM0--3are used for LCD backplanes.

COM238O Common output COM0--3are used for LCD backplanes.

COM339O Common output COM0--3are used for LCD backplanes.

R0340I Input of fourth positive(lowest)analog LCD level(V5)

NOTE1:It is recommended to short unused analog input pairs and connect them to analog ground.

Terminal Functions(Continued) TERMINAL

I/O

NAME NO.

DESCRIPTION R1341I Input of third most positive analog LCD level(V4or V3)

R2342I Input of second most positive analog LCD level(V2)

R3343O Output of most positive analog LCD level(V1)

P2.1/UCLK0/S2444I/O General-purpose digital I/O/external clock input-USART0/UART or SPI mode,clock output—USART0/SPI mode/LCD segment output24(See Note1)

P2.0/TA2/S2545I/O General-purpose digital I/O/Timer_A Capture:CCI2A input,Compare:Out2output/LCD segment output 25(See Note1)

P1.7/SOMI0/S2646I/O General-purpose digital I/O/slave out/master in of USART0/SPI mode/LCD segment output26 (See Note1)

P1.6/SIMO0/S2747I/O General-purpose digital I/O/slave in/master out of USART0/SPI mode/LCD segment output27 (See Note1)

P1.5/TACLK/

ACLK/S2848I/O General-purpose digital I/O/Timer_A and SD16clock signal TACLK input/ACLK output(divided by1, 2,4,or8)/LCD segment output28(See Note1)

P1.4/S2949I/O General-purpose digital I/O/LCD segment output29(See Note1)

P1.3/SVSOUT/

S3050I/O General-purpose digital I/O/SVS:output of SVS comparator/LCD segment output30(See Note1)

P1.2/TA1/S3151I/O General-purpose digital I/O/Timer_A,Capture:CCI1A,CCI1B input,Compare:Out1output/LCD segment output31(See Note1)

P1.1/TA0/MCLK52I/O General-purpose digital I/O/Timer_A,Capture:CCI0B input/MCLK output. Note:TA0is only an input on this pin/BSL receive

P1.0/TA053I/O General-purpose digital I/O/Timer_A,Capture:CCI0A input,Compare:Out0output/BSL transmit TDO/TDI54I/O Test data output.TDO/TDI data output or programming data input terminal.

TDI/TCLK55I Test data input or test clock input.The device protection fuse is connected to TDI.

TMS56I Test mode select.TMS is used as an input port for device programming and test.

TCK57I Test clock.TCK is the clock input port for device programming and test.

RST/NMI58I Reset input or nonmaskable interrupt input port

P2.5/URXD059I/O General-purpose digital I/O/receive data in—USART0/UART mode

P2.4/UTXD060I/O General-purpose digital I/O/transmit data out—USART0/UART mode

P2.3/SVSIN61I/O General-purpose digital I/O/Analog input to brownout,supply voltage supervisor

AV SS62Analog supply voltage,negative terminal.Supplies SD16,SVS,brownout,oscillator,and LCD resistive divider circuitry.

DV SS63Digital supply voltage,negative terminal.

AV CC64Analog supply voltage,positive terminal.Supplies SD16,SVS,brownout,oscillator,and LCD resistive divider circuitry;must not power up prior to DV CC.

NOTE1:LCD function selected automatically when applicable LCD module control bits are set,not with PxSEL bits.

General-Purpose Register Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register PC/R0SP/R1SR/CG1/R2CG2/R3R4R5R12R13General-Purpose Register General-Purpose Register R6R7General-Purpose Register General-Purpose Register R8R9General-Purpose Register General-Purpose Register R10R11General-Purpose Register General-Purpose Register

R14R15

short-form description

CPU

The MSP430CPU has a 16-bit RISC architecture that is highly transparent to the application.All operations,other than program-flow instructions,are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16registers that provide reduced instruction execution time.The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers,R0to R3,are dedicated as program counter,stack pointer,status register,and constant generator,respectively.The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data,address,and control buses,and can be handled with all instructions.instruction set

The instruction set consists of 51instructions with three formats and seven address modes.Each instruction can operate on word and byte data.Table 1shows examples of the three types of instruction formats;the address modes are listed in Table 2.

Table 1.Instruction Word Formats

Dual operands,source-destination e.g,.ADD R4,R5R4+R5------>R5Single operands,destination only e.g.,CALL R8

PC ---->(TOS),R8---->PC Relative jump,un/conditional

e.g.,JNE

Jump-on-equal bit =0

Table 2.Address Mode Descriptions

ADDRESS MODE

S D

SYNTAX EXAMPLE OPERATION Register D D MOV Rs,Rd MOV R10,R11R10

---->R11

Indexed

D D MOV X(Rn),Y(Rm)MOV 2(R5),6(R6)

M(2+R5)---->M(6+R6)Symbolic (PC relative)

D D MOV EDE,TONI M(EDE)---->M(TONI)Absolute D D

MOV &MEM,&TCDAT M(MEM)---->M(TCDAT)Indirect D MOV @Rn,Y(Rm)MOV @R10,Tab(R6)M(R10)---->M(Tab+R6)

Indirect autoincrement D MOV @Rn+,Rm MOV @R10+,R11M(R10)---->R11R10+2---->R10Immediate

MOV #X,TONI

MOV #45,TONI #45

---->M(TONI)

NOTE:S =source,D =destination

operating modes

The MSP430has one active mode and five software selectable low-power modes of operation.An interrupt event can wake up the device from any of the five low-power modes,service the request,and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D Active mode(AM)

--All clocks are active.

D Low-power mode0(LPM0)

--CPU is disabled.

ACLK and SMCLK remain active,MCLK is available to modules.

FLL+loop control remains active.

D Low-power mode1(LPM1)

--CPU is disabled.

ACLK and SMCLK remain active,MCLK is available to modules.

FLL+loop control is disabled.

D Low-power mode2(LPM2)

--CPU is disabled.

MCLK,FLL+loop control,and DCOCLK are disabled.

DCO dc generator remains enabled.

ACLK remains active.

D Low-power mode3(LPM3)

--CPU is disabled.

MCLK,FLL+loop control,and DCOCLK are disabled.

DCO dc generator is disabled.

ACLK remains active.

D Low-power mode4(LPM4)

--CPU is disabled.

ACLK is disabled.

MCLK,FLL+loop control,and DCOCLK are disabled.

DCO dc generator is disabled.

Crystal oscillator is stopped.

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range of0FFFFh to0FFE0h.

The vector contains the16-bit address of the appropriate interrupt-handler instruction sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up

External reset

Watchdog

Flash memory

PC out-of-range(see Note4)

WDTIFG

KEYV

(see Note1)

Reset0FFFEh15,highest

NMI

Oscillator fault

Flash memory access violation

NMIIFG(see Notes1and3)

OFIFG(see Notes1and3)

ACCVIFG(see Notes1and3)

(Non)maskable

0FFFCh14

ESP430MBCTL_OUTxIFG,

MBCTL_INxIFG

(see Notes1and2)

Maskable0FFFAh13

SD16SD16CCTLx SD16OVIFG,

SD16CCTLx SD16IFG

(see Notes1and2)

Maskable0FFF8h12

0FFF6h11

Watchdog timer WDTIFG Maskable0FFF4h10 USART0receive URXIFG0Maskable0FFF2h9 USART0transmit UTXIFG0Maskable0FFF0h8

0FFEEh7 Timer_A3TACCR0CCIFG(see Note2)Maskable0FFECh6

Timer_A3

TACCR1and TACCR2

CCIFGs,and TACTL TAIFG

(see Notes1and2)

Maskable0FFEAh5

I/O port P1(eight flags)P1IFG.0to P1IFG.7

(see Notes1and2)Maskable0FFE8h4

0FFE6h3

0FFE4h2

I/O port P2(eight flags)P2IFG.0to P2IFG.7

(see Notes1and2)Maskable0FFE2h1 Basic Timer1BTIFG Maskable0FFE0h0,lowest NOTES: 1.Multiple source flags

2.Interrupt flags are located in the module.

3.(Non)maskable:the individual interrupt-enable bit can disable an interrupt event,but the general interrupt-enable cannot.

4.A reset is generated if the CPU tries to fetch instructions from within the module register memory address range(0h to01FFh)or

from within unused address ranges(from0600h to0BFFh).

special function registers

Most interrupt and module enable bits are collected into the lowest address space.Special function register bits that are not allocated to a functional purpose are not physically present in the device.Simple software access is provided with this arrangement.

interrupt enable 1and

Address 0h

WDTIE:Watchdog timer interrupt enable.Inactive if watchdog mode is selected.Active if watchdog timer is configured in interval timer mode.OFIE:Oscillator fault interrupt enable NMIIE:Nonmaskable interrupt enable ACCVIE:Flash access violation interrupt enable

URXIE0:USART0:UART and SPI receive interrupt enable UTXIE0:

USART0:UART and SPI transmit interrupt

enable

Address 1h

BTIE:Basic Timer1interrupt enable

interrupt flag register 1and

Address 02h

WDTIFG:Set on watchdog timer overflow (in watchdog mode)or security key violation.Reset on V CC power up or a reset condition at the RST/NMI pin in reset mode.OFIFG:Flag set on oscillator fault NMIIFG:Set via RST/NMI pin

URXIFG0:USART0:UART and SPI receive flag UTXIFG0:

USART0:UART and SPI transmit

flag

Address 3h

BTIFG:Basic Timer1interrupt flag

module enable registers 1and

rw–0

Address 04h

URXE0:USART0:UART mode receive enable UTXE0:USART0:UART mode transmit enable

USPIE0:

USART0:SPI mode transmit and receive

enable

Address 05h

Legend:rw--0,1:Bit Can Be Read and Written.It Is Reset or Set by PUC.

Bit Can Be Read and Written.It Is Reset or Set by POR.SFR Bit Not Present in Device.

memory organization

MSP430FE423A

MSP430FE425A MSP430FE427A Memory

Interrupt vector Code memory Size Flash Flash 8KB

0FFFFh to 0FFE0h 0FFFFh to 0E000h 16KB

0FFFFh to 0FFE0h 0FFFFh to 0C000h 32KB

0FFFFh to 0FFE0h 0FFFFh to 08000h Information memory Size 256Byte

010FFh to 01000h 256Byte

010FFh to 01000h Boot memory Size 1kB

0FFFh to 0C00h 1kB

0FFFh to 0C00h RAM Size 256Byte 02FFh to 0200h 512Byte 03FFh to 0200h 1KB

05FFh to 0200h Peripherals

16-bit 8-bit 8-bit SFR

01FFh to 0100h 0FFh to 010h 0Fh to 00h

bootstrap loader (BSL)

The MSP430bootstrap loader (BSL)enables users to program the flash memory or RAM using a UART serial interface.Access to the MSP430memory via the BSL is protected by user-defined password.For complete description of the features of the BSL and its implementation,see the Application report Features of the MSP430Bootstrap Loader ,Literature Number SLAA089.

BSL FUNCTION PM PACKAGE PINS

Data transmit 53-P1.0Data receive

52-P1.1

flash memory

The flash memory can be programmed via the JTAG port,the bootstrap loader,or in-system by the CPU.The CPU can perform single-byte and single-word writes to the flash memory.Features of the flash memory include:

D Flash memory has n segments of main memory and two segments of information memory (A and B)of 128

bytes each.Each segment in main memory is 512bytes in size.

D Segments 0to n may be erased in one step,or each segment may be individually erased.D Segments A and B can be erased individually,or as a group with segments 0to n.

Segments A and B are also called information memory.

D New devices may have some bytes programmed in the information memory (needed for test during

manufacturing).The user should perform an erase of the information memory prior to the first use.

32KB Main Memory

Information Memory

0FFFFh

0FA00h 0FE00h 0FDFFh

0FC00h 0FBFFh 0F9FFh

08400h 083FFh 08200h 081FFh 01000h

010FFh 08000h 01080h 0107Fh 16KB 0FFFFh

0FA00h 0FE00h 0FDFFh 0FC00h 0FBFFh 0F9FFh

0C400h 0C3FFh 0C200h 0C1FFh 01000h

010FFh 0C000h 01080h 0107Fh 8KB 0FFFFh

0FA00h 0FE00h 0FDFFh 0FC00h 0FBFFh 0F9FFh

0E400h 0E3FFh 0E200h 0E1FFh 01000h

010FFh 0E000h 01080h 0107Fh

peripherals

Peripherals are connected to the CPU through data,address,and control busses and can be handled using all instructions.For complete module descriptions,refer to the MSP430x4xx Family User’s Guide,literature number SLAU056.

oscillator and system clock

The clock system in the MSP430FE42xA family of devices is supported by the FLL+module that includes support for a32768-Hz watch crystal oscillator,an internal digitally-controlled oscillator(DCO)and a high-frequency crystal oscillator.The FLL+clock module is designed to meet the requirements of both low system cost and low power consumption.The FLL+features a digital frequency locked loop(FLL)hardware that,in conjunction with a digital modulator,stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.The internal DCO provides a fast turn-on clock source and stabilizes in less than6μs.

The FLL+module provides the following clock signals:

D Auxiliary clock(ACLK),sourced from a32768-Hz watch crystal or a high-frequency crystal.

D Main clock(MCLK),the system clock used by the CPU.

D Sub-Main clock(SMCLK),the sub-system clock used by the peripheral modules.

D ACLK/n,the buffered output of ACLK,ACLK/2,ACLK/4,or ACLK/8.

brownout,supply voltage supervisor(SVS)

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.The SVS circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision(the device is automatically reset)and supply voltage monitoring(SVM)(the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset.However,V CC may not have ramped to V CC(min)at that time.The user must ensure the default FLL+settings are not changed until V CC reaches V CC(min).If desired,the SVS circuit can be used to determine when V CC reaches V CC(min).

digital I/O

There are two8-bit I/O ports implemented—ports P1and P2(only six P2I/O signals are available on external pins):

D All individual I/O bits are independently programmable.

D Any combination of input,output,and interrupt conditions is possible.

D Edge-selectable interrupt input capability for all the eight bits of port P1and six bits of P2.

D Read/write access to port-control registers is supported by all instructions.

NOTE:

Six bits of port P2,P2.0to P2.5,are available on external pins-but all control and data bits for port

P2are implemented.

Basic Timer1

The Basic Timer1has two independent8-bit timers that can be cascaded to form a16-bit timer/counter.Both timers can be read and written by software.The Basic Timer1can be used to generate periodic interrupts and clock for the LCD module.

LCD drive

The LCD driver generates the segment and common signals required to drive an LCD display.The LCD controller has dedicated data memory to hold segment drive https://www.wendangku.net/doc/f26497515.html,mon and segment signals are generated as defined by the mode.Static,2-MUX,3-MUX,and4-MUX LCDs are supported by this peripheral.

WDT+watchdog timer

The primary function of the watchdog timer(WDT+)module is to perform a controlled system restart after a software problem occurs.If the selected time interval expires,a system reset is generated.If the watchdog function is not needed in an application,the module can be configured as an interval timer and can generate interrupts at selected time intervals.

Timer_A3

Timer_A3is a16-bit timer/counter with three capture/compare registers.Timer_A3can support multiple capture/compares,PWM outputs,and interval timing.Timer_A3also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

TIMER_A3SIGNAL CONNECTIONS

INPUT PIN NUMBER DEVICE INPUT

SIGNAL

MODULE INPUT

NAME MODULE BLOCK

MODULE OUTPUT

SIGNAL

OUTPUT PIN

NUMBER

48-P1.5TACLK TACLK

ACLK ACLK

SMCLK SMCLK

Timer NA

48-P1.5TACLK INCLK

53-P1.0TA0CCI0A53-P1.0

52-P1.1TA0CCI0B

DV SS GND

CCR0TA0

DV CC V CC

51-P1.2TA1CCI1A51-P1.2

51-P1.2TA1CCI1B

DV SS GND

CCR1TA1

DV CC V CC

45-P2.0TA2CCI2A45-P2.0 ACLK(internal)CCI2B

DV SS GND

CCR2TA2

DV CC V CC

universal synchronous/asynchronous receive transmit(USART)

The MSP430FE42xA devices have one hardware USART peripheral module(USART0)that is used for serial data communication.The USART supports synchronous SPI(3or4pin)and asynchronous UART communication protocols,using double-buffered transmit and receive channels.

ESP430CE1A

The ESP430CE1A module integrates a hardware multiplier,three independent16-bit sigma-delta A/D converters(SD16)and an embedded signal processor(ESP430).The ESP430CE1A module measures2-wire or3-wire single-phase energy and automatically calculates parameters that are made available to the MSP430 CPU.The module can be calibrated and initialized to accurately calculate energy,power factor,etc.,for a wide range of metering sensor configurations.

peripheral file map

PERIPHERALS WITH WORD ACCESS

Watchdog Watchdog timer control WDTCTL0120h

Timer_A3Timer_A interrupt vector TAIV012Eh _

Timer_A control TACTL0160h

Capture/compare control0TACCTL00162h

Capture/compare control1TACCTL10164h

Capture/compare control2TACCTL20166h

Reserved0168h

Reserved016Ah

Reserved016Ch

Reserved016Eh

Timer_A register TAR0170h

Capture/compare register0TACCR00172h

Capture/compare register1TACCR10174h

Capture/compare register2TACCR20176h

Reserved0178h

Reserved017Ah

Reserved017Ch

Reserved017Eh Hardware Multiplier Sum extend SUMEXT013Eh

(see Note1)Result high word RESHI013Ch

Result low word RESLO013Ah

Second operand OP20138h

Multiply signed+accumulate/operand1MACS0136h

Multiply+accumulate/operand1MAC0134h

Multiply signed/operand1MPYS0132h

Multiply unsigned/operand1MPY0130h Flash Flash control3FCTL3012Ch

Flash control2FCTL2012Ah

Flash control1FCTL10128h SD16(see Note1)General control SD16CTL0100h ()

(see also:Peripherals Byte Channel0control SD16CCTL00102h

With Access)

Channel1control SD16CCTL10104h

Channel2control SD16CCTL20106h

Reserved0108h

Reserved010Ah

Reserved010Ch

Reserved010Eh

Interrupt vector word register SD16IV0110h

Channel0conversion memory SD16MEM00112h

NOTE1:Module is contained within ESP430CE1A.Registers not accessible when ESP430is active.ESP430must be disabled or suspended to allow CPU access to these modules.

peripheral file map(continued)

PERIPHERALS WITH WORD ACCESS

SD16Channel1conversion memory SD16MEM10114h

(continued,see Note1)Channel2conversion memory SD16MEM20116h

Reserved0118h

Reserved011Ah

Reserved011Ch

Reserved011Eh

()

ESP430(ESP430CE1A)ESP430control ESPCTL0150h

Mailbox control MBCTL0152h

Mailbox in0MBIN00154h

Mailbox in1MBIN10156h

Mailbox out0MBOUT00158h

Mailbox out1MBOUT1015Ah

ESP430return value0RET001C0h

:::

ESP430return value31RET3101FEh

PERIPHERALS WITH BYTE ACCESS

()

SD16(see Note1)Channel0input control SD16INCTL00B0h

(see also:Peripherals Channel1input control SD16INCTL10B1h

With Word Access)

Channel2input control SD16INCTL20B2h

Reserved0B3h

Reserved0B4h

Reserved0B5h

Reserved0B6h

Reserved0B7h

Channel0preload SD16PRE00B8h

Channel1preload SD16PRE10B9h

Channel2preload SD16PRE20BAh

Reserved0BBh

Reserved0BCh

Reserved0BDh

Reserved0BEh

Reserved0BFh

LCD LCD memory20LCDM200A4h

:::

LCD memory16LCDM160A0h

LCD memory15LCDM1509Fh

:::

LCD memory1LCDM1091h

LCD control and mode LCDCTL090h

NOTE1:Module is contained within ESP430CE1A.Registers not accessible when ESP430is active.ESP430must be disabled or suspended to allow CPU access to these modules.

peripheral file map(continued)

PERIPHERALS WITH BYTE ACCESS(CONTINUED)

USART0Transmit buffer U0TXBUF077h

Receive buffer U0RXBUF076h

Baud rate U0BR1075h

Baud rate U0BR0074h

Modulation control U0MCTL073h

Receive control U0RCTL072h

Transmit control U0TCTL071h

USART control U0CTL070h Brownout,SVS SVS control register SVSCTL056h

FLL+Clock FLL+control1FLL_CTL1054h

FLL+control0FLL_CTL0053h

System clock frequency control SCFQCTL052h

System clock frequency integrator SCFI1051h

System clock frequency integrator SCFI0050h Basic Timer1BT counter2BTCNT2047h

BT counter1BTCNT1046h

BT control BTCTL040h Port P2Port P2selection P2SEL02Eh

Port P2interrupt enable P2IE02Dh

Port P2interrupt-edge select P2IES02Ch

Port P2interrupt flag P2IFG02Bh

Port P2direction P2DIR02Ah

Port P2output P2OUT029h

Port P2input P2IN028h Port P1Port P1selection P1SEL026h

Port P1interrupt enable P1IE025h

Port P1interrupt-edge select P1IES024h

Port P1interrupt flag P1IFG023h

Port P1direction P1DIR022h

Port P1output P1OUT021h

Port P1input P1IN020h p

Special Functions SFR module enable2ME2005h

SFR module enable1ME1004h

SFR interrupt flag2IFG2003h

SFR interrupt flag1IFG1002h

SFR interrupt enable2IE2001h

SFR interrupt enable1IE1000h

absolute maximum ratings ?

Voltage applied at V CC to V SS --0.3V to +4.1V ....................................................Voltage applied to any pin (see Note 1)--0.3V to V CC +0.3V .......................................Diode current at any device terminal ±2mA ......................................................Storage temperature (unprogrammed device)--55°C to 150°C ......................................Storage temperature (programmed device)--40°C to 85°C

.........................................?

Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1:All voltages referenced to V SS .The JTAG fuse-blow voltage,V FB ,is allowed to exceed the absolute maximum rating.The voltage is

applied to the TDI/TCLK pin when blowing the JTAG fuse.

recommended operating conditions (see Note 1)

PARAMETER

MIN NOM

MAX UNITS Supply voltage during program execution;ESP430and SD16disabled,V CC (AV CC =DV CC =V CC )(see Note 1)

MSP430FE42xA 1.8 3.6V Supply voltage during program execution;SVS enabled,PORON =1,ESP430and SD16disabled,V CC (AV CC =DV CC =V CC )(see Notes 1and 2)

MSP430FE42xA

2.0

3.6

Supply voltage during program execution;ESP430or SD16enabled or during programming of flash memory,V CC (AV CC =DV CC =V CC )(see Note 1)

MSP430FE42xA 2.7 3.6V Supply voltage (see Note 1),V SS (AV SS =DV SS =V SS )00V Operating free-air temperature range,T A

MSP430FE42xA --40

85°C LF selected,XTS_FLL =0

Watch crystal 32768

Hz frequency,f Note 3)

XT1selected,XTS_FLL =1Ceramic resonator 4508000kHz LFXT1crystal (LFXT1)(see XT1selected,XTS_FLL =1

Crystal 10008000kHz MCLK)V CC =2.7V DC 8.4Processor frequency (signal MCLK),f (System)(see Note 4)

V CC =3.6V

8.4

MHz

NOTES: 1.It is recommended to power AV CC and DV CC from the same source.A maximum difference of 0.3V between AV CC and DV CC can

be tolerated during power up and operation.

2.The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.

POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.3.The LFXT1oscillator in LF-mode requires a watch crystal.

4.For frequencies above 8MHz,MCLK is sourced by the built-in oscillator (DCO and FLL+).

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

supply current into AV CC +DV CC excluding external current (see Note 1)

PARAMETER

TEST CONDITIONS

V CC MIN

NOM

MAX

UNIT

I (AM)Active mode,

f (MCLK)=f (SMCLK)=f (DCO)=1MHz,f (ACLK)=32,768Hz,XTS_FLL =0(program executes in flash)

T A =--40°C to 85°C

400500μA

I (LPM0)Low-power mode,(LPM0/LPM1)f (MCLK)=f (SMCLK)=f (DCO)=1MHz,f (ACLK)=32,768Hz,XTS_FLL =0

FN_8=FN_4=FN_3=FN_2=0(see Note 2)T A =--40°C to 85°C 3V 130150μA

I (LPM2)

Low-power mode,(LPM2)(see Note 2)

T A =--40°C to 85°C 3V 1022μA

T A =--40°C 1.5 2.0Low power mode T A =25°C 1.6 2.1I (LPM3)

Low-power mode,(LPM3)(see Note 2)T A =60°C 3V 1.7 2.2μA

T A =85°C 2.0 3.5T A =--40°C

0.1

0.5Low-power (LPM4)(see Note 2)T A =25°C V 0.10.5I (LPM4)

Low power mode,T A =85°C

30.8

2.5

μA

NOTES: 1.All inputs are tied to 0V or V CC .Outputs do not source or sink any current.

The current consumption in LPM2,LPM3,and LPM4are measured with active Basic Timer1and LCD (ACLK selected).The current consumption of the ESP430CE1A and the SVS module are specified in their respective sections.LPMx currents measured with WDT+disabled.

The currents are characterized with a KDS Daishinku DT--38(6pF)crystal.2.Current for brownout included.

current consumption of active mode versus system frequency

I (AM)=I (AM)[1MHz]×f (System)[MHz]

current consumption of active mode versus supply voltage

I (AM)=I (AM)[3V]+170μA/V ×(V CC –3V)

f (MHz)

1.8V 3.6V

2.7V 3V 4.15MHz

8.4MHz

V CC --Supply Voltage --V

f S y s t e m --M a x i m u m P r o c e s s o r F r e q u e n c y --M H z

6MHz

Figure 1.Frequency vs Supply Voltage

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)(continued)

Schmitt-trigger inputs --Ports P1and P2,RST/NMI,JTAG (TCK,TMS,TDI/TCLK,TDO/TDI)

PARAMETER

V CC MIN TYP

MAX UNIT V IT+Positive-going input threshold voltage 3V 1.5 1.98V V IT--Negative-going input threshold voltage 3V 0.9 1.3V V hys

Input voltage hysteresis (V IT+--V IT--)

0.45

inputs Px.x,TAx

PARAMETER

TEST CONDITIONS

V CC MIN TYP

MAX

UNIT timing Port P2:P1.x trigger 3V 1.5cycle t (int)External interrupt P1,to P2.x,External signal for the interrupt flag (see Note 1)3V 50ns t (cap)Timer_A,capture timing TAx

3V 50

ns f (TAext)Timer_A clock frequency externally applied to pin TACLK,INCLK t (H)=t (L)

3V 10MHz f (TAint)

Timer_A clock frequency

SMCLK or ACLK signal selected

MHz

NOTES: 1.The external signal sets the interrupt flag every time the minimum t (int)cycle and time parameters are met.It may be set even with

trigger signals shorter than t (int).Both the cycle and timing specifications must be met to ensure the flag is set.t (int)is measured in MCLK cycles.

leakage current (see Note 1)

PARAMETER

TEST CONDITIONS

V CC MIN

NOM

MAX UNIT I lkg(P1.x)Port P1Port 1:V (P1.x)(see Note 2)±50I lkg(P2.x)

Leakage current

Port P2

Port 2:V (P2.x)(see Note 2)

±50

NOTES: 1.The leakage current is measured with V SS or V CC applied to the corresponding pin(s),unless otherwise noted.

2.The port pin must be selected as an input.

outputs --Ports P1and P2

PARAMETER

TEST CONDITIONS

V CC MIN TYP

MAX UNIT High level I OH(max)=--1.5mA (see Note 1)V CC --0.25V CC V OH High-level

output voltage I OH(max)=--6mA (see Note 2)3V V CC --0.6

V CC

V Low level voltage I OL(max)=1.5mA (see Note 1)V SS V SS +0.25V OL

Low-level

output I OL(max)=6mA (see Note 2)

V SS

V SS +0.6

NOTES: 1.The maximum total current,I OH(max)and I OL(max),for all outputs combined,should not exceed ±12mA to satisfy the

maximum specified voltage drop.

2.The maximum total current,I OH(max)and I OL(max),for all outputs combined,should not exceed ±48mA to satisfy the

maximum specified voltage drop.

output frequency

PARAMETER

TEST CONDITIONS

V CC MIN TYP

MAX UNIT f Px.y (1≤x ≤2,0≤y ≤7)C L =20pF,I L =±1.5mA 3V dc

12MHz f ACLK,f MCLK,f SMCLK

P1.1/TA0/MCLK

P1.5/TACLK/ACLK/S28

C L =20pF

12MHz

P15/TACLK/ACLK/S28f ACLK =f LFXT1=f XT140%60%Duty cycle P1.5/TACLK/ACLK/S28,f ACLK =f LFXT1=f LF 30%

70%

t of output C L =20pF f ACLK =f LFXT13V

50%Xdc

frequency

P1.1/TA0/MCLK,C L =20pF

f MCLK =f DCOCLK

50%--15ns

50%

50%+15ns

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)(continued)

outputs --Ports P1and P2(continued)

Figure 2

V OL --Low-Level Output Voltage --V 05

300.0

0.5 1.0 1.5 2.0 2.5

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

O L I --T y p i c a l L o w -l e v e l O u t p u t C u r r e n t --m A

Figure 3

V OL --Low-Level Output Voltage --V

010

0.0

0.5 1.0 1.5 2.0 2.5 3.0 3.5

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

O L I --T y p i c a l L o w -l e v e l O u t p u t C u r r e n t --m A

Figure 4

V OH --High-Level Output Voltage --V

--30--25

--20

--15

--10

--5

0.0

0.5 1.0 1.5 2.0

2.5

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

O L I --T y p i c a l H i g h -l e v e l O u t p u t C u r r e n t --m A

Figure 5

V OH --High-Level Output Voltage --V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

NOTE A.One output loaded at a time