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T68R1MTC-8中文资料

￠DESCRIPTION

The T68K1M, T68S1M, and T68R1M device family is a low power and high performance CMOS SRAM organized as 131,072 words by 8 bits. It operates from 2.7V to 3.6V, 2.2V to

2.7V, and 1.65V to 2.2V. Easy memory expansion is provided by an active LOW chip enable 1

(/CE1), active HIGH chp enable 2 (CE2) and active LOW output enable (/OE) and three-state I/O drivers. Four control pins (/CE1, CE2, /OE, and /WE) fully control the operation mode of the T68 K/S/R 1M device family. An active LOW write enable signal (/WE active low) controls the write/read operation of the memory. When /CE1 and /WE inputs go LOW and CE2 input goes HIGH simultaneously, the device is in write mode and data on the 8 data pins (IO1~IO8) is written into the memory location specified by the address on address pins (A0~A16). When /CE1 and /OE inputs go LOW and CE2 and /WE input stay in HIGH state, the device is in read mode and data in the specified memory address is driven onto the 8 data pins. The 8 data pins will be in high-impedance state if both /OE and /WE pins are in HIGH (inactive) state. The T68 K/S/R 1M device family has an automatically power-down feature when the chip is deselected (/CE1 pin HIGH or CE2 pin LOW). The T68 K/S/R 1M device family is available in JEDEC standard 32-pin 450-mil SOP, 32-pin 8mmx20mm plastic TSOP, 32-pin 8mmx13.4mm plastic STSOP, and 36-ball 6mmx8mm BGA package, also for DICE.

￠FEATURES

— Operation voltage………………T68K1M…………………………….................2.7V ~ 3.6V

T68S1M……………………………………….. 2.2V ~ 2.7V

T68R1M………………………….................. 1.65V ~ 2.2V — Low active power and standby power

— High access times: 70ns/85ns/100ns

— TTL-compatible inputs and outputs

— Easy memory expansion with /CE1, CE2 and /OE

— Low data retention voltage…………………………..2.0V (for K), 1.5V (for S), 1.0V (for R)

— Auto power down when deselected

T68 K/S/R 1M

Power Dissipation Part Number V CC Range Speed

Operating Temperature

Operating (I CC2, Max.)

Standby (I SB1, Max.)

Package Type

T68K1MGC -7/-8 SOP-32 T68K1MTC -7/-8 TSOP-32

T68K1MSC -7/-8 STSOP-32 T68K1MBC -7/-8 BGA-36

T68K1MDC -7/-8 2.7V~3.6V

20mA

3uA

Dice T68S1MGC -7/-8 SOP-32 T68S1MTC -7/-8 TSOP-32

T68S1MSC -7/-8 STSOP-32 T68S1MBC -7/-8 BGA-36 T68S1MDC -7/-8 2.2V~2.7V

70ns/ 85ns

20mA

3uA

Dice T68R1MGC -8/-10 SOP-32 T68R1MTC -8/-10

TSOP-32 T68R1MSC -8/-10 STSOP-32 T68R1MBC -8/-10

BGA-36 T68R1MDC -8/-10

1.65V~

2.2V 85ns/ 100ns Commercial (+0o

C~+70o

15mA

2uA

Dice

Power Dissipation Part Number V CC Range Speed

Operating Temperature

Operating (I CC2, Max.)

Standby (I SB1, Max.)

Package Type T68K1MGE -7/-8 SOP-32 T68K1MTE -7/-8 TSOP-32

T68K1MSE -7/-8 STSOP-32 T68K1MBE -7/-8 BGA-36

T68K1MDE -7/-8 2.7V~3.6V 20mA 3uA Dice T68S1MGE -7/-8 SOP-32 T68S1MTE -7/-8 TSOP-32

T68S1MSE -7/-8 STSOP-32 T68S1MBE -7/-8 BGA-36 T68S1MDE -7/-8 2.2V~2.7V

70ns/ 85ns

20mA

3uA

Dice T68R1MGE -8/-10 SOP-32 T68R1MTE -8/-10

TSOP-32 T68R1MSE -8/-10 STSOP-32 T68R1MBE -8/-10 BGA-36 T68R1MDE -8/-10

1.65V~

2.2V 85ns/ 100ns Extended (-25o

C~+85o

15mA

2uA

Dice

￠ PRODUCT FAMILY

T68 K/S/R 1M

Power Dissipation Part Number

V CC Range

Speed

Operating Temperature

Operating (I CC2, Max.)

Standby (I SB1, Max.)

Package Type

T68K1MGI -7/-8 SOP-32 T68K1MTI -7/-8 TSOP-32

68K1MSI -7/-8 STSOP-32 T68K1MBI -7/-8 BGA-36

T68K1MDI -7/-8 2.7V~3.6V

20mA

3uA

Dice T68S1MGI -7/-8 SOP-32

T68S1MTI -7/-8 TSOP-32

T68S1MSI -7/-8 STSOP-32 T68S1MBI -7/-8 BGA-36 T68S1MDI -7/-8 2.2V~2.7V

70ns/ 85ns

20mA

3uA

Dice T68R1MGI -8/-10 SOP-32 T68R1MTI -8/-10 TSOP-32 T68R1MSI -8/-10 STSOP-32 T68R1MBI -8/-10 BGA-36 T68R1MDI -8/-10

1.65V~

2.2V 85ns/ 100ns

Industrial (-40o

C~+85o

15mA

2uA

Dice

T68 K/S/R 1M

￠ PIN CONFIGURATION

T68 K/S/R 1M ￠LOGIC BLOCK

￠(PIN DESCRIPTION)

Pin Name Function

A0 ~ A16 Address Input Pins

IO1 ~ IO8 Data Input/Output Pins

/CE1 Chip Enable 1 Input Pin

CE2 Chip Enable 2 Input Pin

/OE Output Enable Input Pin

/WE Write Enable Input Pin

V CC Power Supply Pin

V SS Ground Pin

T68 K/S/R 1M

Mode /CE1 CE2 /WE /OE I/O1~8 Power Deselected H X (1)

X X High-Z Standby Deselected X L X X High-Z Standby Write L H L X Input Active Read L H H L Output Active Output Disabled

High-Z

Active

1. ’X’ means don’t care. Must be in high or low state.

Symbol Parameter

Rating

Unit -0.5 ~ Vcc.max+1V (2)

V V CC

Power Supply Voltage (to V SS )

-0.5 ~ Vcc.max+0.3V (3) V -0.5 ~ Vcc+0.5V (2)

V V IN /V OUT Input / Output Voltage -0.5 ~ Vcc+0.3V (3)

V I OUT Output Current into Outputs (LOW) 20 mA P D Power Dissipation 1.0 W

T STG

Storage Temperature

-65 ~ +150

T SOLDER Soldering Temperature and Time

260 O

C , 10sec (Lead Only)

C-Grade

0 ~ 70 E-Grade -25 ~ 85 T A

Operating Temperature

I-Grade

-40 ~ 85

1. Stresses greater than those listed in the Absolute Maximum Ratings table may cause permanent damage

to the device.Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum ratings conditions for extended periods may affect reliability. 2. For K and S family. 3. For R family.

￠ TRUTH TABLE

￠ ABSOLUTE MAXINUM RATINGS (1)

T68 K/S/R 1M

Symbol Parameter Min. Max. Condition C IN

Input Capacitance

8pF C IO Input/Output Capacit ance -

10pF

Unmeasured pins set

to 0V

Symbol

Parameter Test Condition Min. Typ. Max. Unit

T68K1M 2.0

- 3.6 T68S1M 1.5 - 2.7 V DR V CC for Data Retention

T68R1M

Standby Mode 1.0

- 2.2 V

C-Grade - - 2 E-Grade - - 3 T68K1M

V CC =2.0V and CMOS Standby mode (1)

I-Grade - - 3 C-Grade

- - 1 E-Grade - - 2 T68S1M

V CC =1.5V and CMOS Standby mode (1)

I-Grade - - 2 C-Grade

- - 1 E-Grade - - 2 I DR

Data Retention

Current

T68R1M

V CC =1.0V and CMOS Standby mode (1)

I-Grade

- - 2 uA

T SDR Data Retention Setup Time

0 - - ns T RDR Data Retention Recovery Time

See data retention waveform

T RC

Note: 1. Standby mode: /CE1≥Vcc-0.2V or CE2≤ Vss+0.2V

Symbol

Parameter

Rating Unit T68K1M

2.7 ~

3.6 V T68S1M 2.2 ~ 2.7 V V CC

T68R1M

Supply Voltage 1.65 ~ 2.2

V V SS

Ground 0 V T68K1M

2.2 ~ V CC +0.5 V T68S1M 2.0 ~ V CC +0.5 V V IH

T68R1M Input High Voltage

1.4 ~ V CC +0.5 V T68K1M

-0.5 ~ 0.6 V T68S1M -0.5 ~ 0.6 V V IL

T68R1M

Input Low Voltage -0.5 ~ 0.4

￠ RECOMMENDED DC OPERATING RANGE

￠ CAPACITANCES (1)

￠ DATA RENTATION CHARACTERISTICS

T68 K/S/R 1M

Symbol Parameter

T est Condition

Min Typ Max Unit I LI Input Leakage Current V IN = V SS to V CC

-1 - 1 μA I LO

Output Leakage Current

/CE1=V IH CE2=V IL or /OE=V IH

or /WE=V IL , V IO =V SS to V CC

-1 - 1 μA

T68K1M - 3(1)

6 T68S1M

- 3(1) 6 I CC1

T68R1M /CE1≤0.2V, CE2≥V CC -0.2V,

V IN ≤0.2V or V IN ≥V CC -0.2V

Cycle time = 1μs, 100%duty,

I IO =0mA

- 2(1) 4 mA

T68K1M - 15(1) 20 T68S1M

- 15(1) 20 I CC2

Average Operating Current

T68R1M /CE1=V IL , CE2=V IH , V IN =V IH or

V IN =V IL,

Cycle time = min, 100% duty,

I IO =0mA - 10(1) 15 mA

T68K1M IOL = 2.0mA

- - 0.4 T68S1M IOL = 0.5mA - - 0.4 V OL

Output Low Voltage

T68R1M IOL = 0.2mA - - 0.4 V

T68K1M IOH = -1.0mA

2.2 - - T68S1M IOH = -0.5mA 2.0 - - V OH

Output High Voltage

T68R1M IOH = -0.1mA

1.4 - - V

T68K1M

- - 0.2 T68S1M

- - 0.2 I SB

TTL Standby Current

T68R1M

/CE1=V IH or CE2= V IL ,

other inputs = V IH or V IL

- - 0.2 mA

T68K1M - 1.0(1) 3 T68S1M - 1.0(1) 3 I SB1 CMOS Standby Current T68R1M /CE1≥V CC -0.2V or CE2≤V SS +0.2V , other inputs = 0 to V CC

0.8(1)

μA

Note: 1. Ta=25o

C, V CC =3.0V (K), V CC =2.5V (S), and V CC =1.8V (R), not 100% tested .

￠ DC ELECTRICAL CHARACTERISTICS

T68 K/S/R 1M

Speed Bin

-7 (70ns) -8(85ns) -10(100ns) Symbol

Parameter List

Min

Max Min Max Min Max Units

t RC Read Cycle Time 70 - 85 - 100 - ns t AA Address Access Time - 70 - 85 - 100 ns t CO Chip Select to Output - 70 - 85 - 100 ns t OE Output Enable to Valid Output - 35 - 40 - 50 ns t LZ Chip Select to Low-Z Output 10 - 10 - 10 - ns t OLZ Output Enable to Low-Z Output 5 - 5 - 5 - ns t HZ Chip Disable to High-Z Output 0 25 0 25 0 30 ns t OHZ Output Disable to High-Z Output 0 25 25 30 ns t OH

Output Hold From Address

Speed Bin

-7 (70ns) -8(85ns) -10 (100ns) Symbol

Parameter List

Min

Max Min Max Min Max Units

t WC Write Cycle Time

70 - 85 - 100 - ns t CW Chip Select to End of Write 60 - 70 - 80 - ns t AS Address Setup Time

0 - 0 - 0 - ns t AW Address Valid to End of Write 60 - 70 - 80 - ns t WP Write Pulse Width 55 - 60 - 70 - ns t WR Write Recovery Time 0 - 0 - 0 - ns t WHZ Write to Output High-Z 0 25 0 25 0 30 ns t DW Data to Write Time Overlap 30 - 35 - 40 - ns t DH Data Hold from Write Time 0 - 0 - 0 - ns t OW

End Write to Output Low-Z

ns ￠ AC ELECTRICAL CHARACTERISTICS

? TEST CONDITIONS

Input Pulse Level: 0.2Vcc(??V iL ), 0.8Vcc(?ùV IH ) Input Rising and Falling Time: 5ns

Input and Output Reference Voltage: 0.9V(R), 1.1V(S), 1.5V (K) Output Load: C L = 30pF + one TTL gate

? READ CYCLE

? WRITE CYCLE

T68 K/S/R 1M

￠ TIMING DIAGRAMS

? TIMEING WAVEFORM OF READ CYCLE (1)

(Address Controlled, /CE1=/OE=VIL, CE2=/WE=VIH)

? TIMEING WAVEFORM OF READ CYCLE (2) (/WE=VIH)

T68 K/S/R 1M ?TIMING WAVEFORM OF WRITE CYCLE (1) (/WE Controlled)

? TIMING WAVEFORM OF WRITE CYCLE (2) (/CE1 OR CE2 Controlled)

T68 K/S/R 1M

? DATA RETENTION WAVEFORM (1) (/CE1 Controlled)

? DATA RETENTION WAVEFORM (2) (CE2 Controlled)

T68 K/S/R 1M ￠ PACKAGE DIMENSION

T68 K/S/R 1M