MM54C244中文资料

TL F 5905

MM54C240 MM74C240Inverting MM54C244 MM74C244Non-Inverting Octal Buffers and Line Drivers with TRI-STATE Outputs

February 1988

MM54C240 MM74C240Inverting

MM54C244 MM74C244Non-Inverting

Octal Buffers and Line Drivers with TRI-STATE Outputs

General Description

These octal buffers and line drivers are monolithic comple-mentary MOS (CMOS)integrated circuits with TRI-STATE outputs These outputs have been specially designed to drive highly capacitive loads such as bus-oriented systems These devices have a fan out of 6low power Schottky loads A high logic level on the output disable control input G makes the outputs go into the high impedance state For improved TTL input compatibility see MM74C941

Features

Y Wide supply voltage range (3V to 15V)Y High noise immunity (0 45V CC typ)Y Low power consumption

Y High capacitive load drive capability Y TRI-STATE outputs Y Input protection Y TTL compatibility

Y 20-pin dual-in-line package

Y

High speed 25ns (typ ) 10V 50pF (MM74C244)

Logic and Connection Diagrams

MM54C240 MM74C240

TL F 5905–1

MM54C240 MM74C240Dual-In-Line Package

TL F 5905–2

Top View

Order Number MM54C240or MM74C240

MM54C244 MM74C244TL F 5905–3

MM54C244 MM74C244Dual-In-Line Package

TL F 5905–4

Top View

Order Number MM54C244or MM74C244

TRI-STATE is a registered trademark of National Semiconductor Corporation C 1995National Semiconductor Corporation

RRD-B30M105 Printed in U S A

Absolute Maximum Ratings(Note1)

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin b0 3V to V CC a0 3V Operating Temperature Range

MM54C240 MM54C244b55 C to a125 C MM74C240 MM74C244b40 C to a85 C Storage Temperature Range b65 C to a150 C Power Dissipation

Dual-In-Line700mW Small Outline500mW Operating V CC Range3V to15V Absolute Maximum V CC18V Lead Temperature(Soldering 10seconds)260 C

DC Electrical Characteristics Min Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V IN(1)Logical‘‘1’’Input Voltage V CC e5V3 5V

V CC e10V8 0V

V IN(0)Logical‘‘0’’Input Voltage V CC e5V1 5V

V CC e10V2 0V

V OUT(1)Logical‘‘1’’Output Voltage V CC e5V I O e b10m A4 5V

V CC e10V I O e b10m A9 0V

V OUT(0)Logical‘‘0’’Output Voltage V CC e5V I O e10m A0 5V

V CC e10V I O e10m A1 0V I OZ TRI-STATE Output Current V CC e10V OD e V IH g10m A I IN(1)Logical‘‘1’’Input Current V CC e15V V IN e15V0 0051 0m A I IN(0)Logical‘‘0’’Input Current V CC e15V V IN e0V b1 0b0 005m A I CC Supply Current V CC e15V0 05300m A CMOS LPTTL INTERFACE

V IN(1)Logical‘‘1’’Input Voltage54C V CC e4 5V V CC b1 5V

74C V CC e4 75V V CC b1 5V

V IN(0)Logical‘‘0’’Input Voltage54C V CC e4 5V0 8V

74C V CC e4 75V0 8V

V OUT(1)Logical‘‘1’’Output Voltage54C V CC e4 5V I O e b450m A V CC b0 4V

74C V CC e4 75V I O e b450m A V CC b0 4V

54C V CC e4 5V I O e b2 2mA2 4V

74C V CC e4 75V I O e b2 2mA2 4V

V OUT(0)Logical‘‘0’’Output Voltage54C V CC e4 5V I O e2 2mA0 4V

74C V CC e4 75V I O e2 2mA0 4V OUTPUT DRIVE(See54C 74C Family Characteristics Data Sheet)(Short Circuit Current)

I SOURCE Output Source Current V CC e5V V OUT e0V

b14b30mA (P-Channel)T A e25 C

V CC e10V V OUT e0V

b36b70mA

T A e25 C

I SINK Output Sink Current V CC e5V V OUT e V CC

1220mA (N-Channel)T A e25 C

V CC e10V V OUT e V CC

4870mA

T A e25 C

Note1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed Except for‘‘Operating Range’’they are not meant to imply that the devices should be operated at these limits The table of‘‘Electrical Characteristics’’provides conditions for actual device operation

2

AC Electrical Characteristics T A e25 C C L e50pF unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

t PD(1) t PD(0)Propagation Delay

(Data In to Out)

MM54C240 MM74C240V CC e5V C L e50pF6090ns

V CC e10V C L e50pF4070ns

V CC e5V C L e150pF80110ns

V CC e10V C L e150pF6090ns

MM54C244 MM74C244V CC e5V C L e50pF4570ns

V CC e10V C L e50pF2550ns

V CC e5V C L e150pF6090ns

V CC e10V C L e150pF4070ns

t1H t0H Propagation Delay Output R L e1k C L e50pF

Disable to High Impedance V CC e5V4580ns

State(from a Logic Level)V CC e10V3560ns

t H1 t H0Propagation Delay Output R L e1k C L e50pF

Disable to Logic Level V CC e5V5090ns

(from High Impedance State)V CC e10V3060ns

t T(HL) t T(LH)Transition Time V CC e5V C L e50pF4580ns

V CC e10V C L e50pF3060ns

V CC e5V C L e150pF75140ns

V CC e10V C L e150pF50100ns

C P

D Power Dissipation(Note3)

Capacitance

(Output Enabled per Buffer)

MM54C240 MM74C240100pF

MM54C244 MM74C244100pF

(Output Disabled per Buffer)

MM54C240 MM74C24010pF

MM54C244 MM74C2440pF C IN Input Capacitance V IN e0V f e1MHz T A e25 C

10pF (Any Input)

C O Output Capacitance V IN e0V f e1MHz T A e25 C

10pF (Output Disabled)

AC Parameters are guaranteed by DC correlated testing

Note1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed Except for‘‘Operating Range’’they are not meant to imply that the devices should be operated at these limits The table of‘‘Electrical Characteristics’’provides conditions for actual device operation Note2 Capacitance is guaranteed by periodic testing

Note3 C PD determines the no load AC power consumption of any CMOS device For complete explanation see54C 74C Family Characteristics Application Note AN-90

Typical Application

TL F 5905–5

3

Truth Tables

MM54C240 MM74C240

ODA IA OA

1X Z 1X Z 001 010

ODB IB OB

1X Z

1X Z

001

010 MM54C244 MM74C244

ODA IA OA

1X Z

1X Z

000

011 1e High

0e Low

X e Don’t Care

Z e TRI-STATE ODB IB OB

1X Z 1X Z 000 011

Typical Performance Characteristics

N-Channel Output Drive

at25 C

TL F 5905–6P-Channel Output Drive

at25 C

TL F 5905–7

MM54C240 MM74C240

Propagation Delay vs

Load Capacitance

TL F 5905–8

MM54C244 MM74C244

Propagation Delay vs

Load Capacitance

TL F 5905–9 4

AC Test Circuits and Switching Time Waveforms

t pd0 t pd1

TL F 5905–10

CMOS to CMOS

TL F 5905–11 t1H and t H1t1H t H1

TL F 5905–12

TL F 5905–13

Note V OH is defined as the DC output high voltage when the device is loaded with

a1k X resistor to ground

t0H and t H0t0H t H0

TL F 5905–14

TL F 5905–15

Note V OL is defined as the DC output low voltage when the device is loaded with a

1k X resistor to V CC

Note Delays measured with input t r t f s20ns

5

M M 54C 240 M M 74C 240I n v e r t i n g M M 54C 244 M M 74C 244N o n -I n v e r t i n g O c t a l B u f f e r s a n d L i n e D r i v e r s w i t h T R I -S T A T E O u t p u t s

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number MM54C240J MM54C244J MM74C240J or MM74C244J

See NS Package Number J20A

Molded Dual-In-Line Package (N)

Order Number MM54C240N MM54C244N MM74C240N or MM74C244N

See NS Package Number N20A

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness

be reasonably expected to result in a significant injury to the user

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